Data processing systems, such as a System-on-a-Chip (SoC) may contain multiple processor cores, multiple data caches and shared data resources. In a shared memory system for example, each of the processor cores may read and write to a single shared address space. Cache coherency is an issue in any system that contains one or more caches and more than one device sharing data in a single cached area. There are two potential problems with a system that contains caches. First, memory may be updated by another device after a cached device has taken a copy. At this point, the data within the cache is out-of-date or invalid and no longer contains the most up-to-date data. Second, systems that contain write-back caches must deal with the case where the device writes to the local cached copy at which point the memory no longer contains the most up-to-date data. A second device reading memory will see out-of-date data.
The data processing system may be arranged as a number of nodes coupled together via an interconnect system to form a network. One example of a protocol for maintaining cache coherency uses snoop requests. When a node of a network wishes to access data associated with a particular address, a snoop message is sent to other nodes that have a copy of requested data stored in a local cache.
However, the connected nodes may have different data bus widths. The presence of nodes having different data bus widths can result in timing and bus utilization inefficiencies.
The accompanying drawings provide visual representations which will be used to more fully describe various representative embodiments and can be used by those skilled in the art to better understand the representative embodiments disclosed and their inherent advantages. In these drawings, like reference numerals identify corresponding elements.
While this invention is susceptible of embodiment in many different forms, there is shown in the drawings and will herein be described in detail specific embodiments, with the understanding that the present disclosure is to be considered as an example of the principles of the invention and not intended to limit the invention to the specific embodiments shown and described. In the description below, like reference numerals may be used to describe the same, similar or corresponding parts in the several views of the drawings.
In this document, relational terms such as first and second, top and bottom, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. The terms “comprises,” “comprising,” “includes,” “including,” “has,” “having,” or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element preceded by “comprises . . . a” does not, without more constraints, preclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.
Reference throughout this document to “one embodiment,” “certain embodiments,” “an embodiment,” “implementation(s),” “aspect(s),” or similar terms means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of such phrases or in various places throughout this specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments without limitation.
The term “or” as used herein is to be interpreted as an inclusive or meaning any one or any combination. Therefore, “A, B or C” means “any of the following: A; B; C; A and B; A and C; B and C; A, B and C.” An exception to this definition will occur only when a combination of elements, functions, steps or acts are in some way inherently mutually exclusive. Also, grammatical conjunctions are intended to express any and all disjunctive and conjunctive combinations of conjoined clauses, sentences, words, and the like, unless otherwise stated or clear from the context. Thus, the term “or” should generally be understood to mean “and/or” and so forth.
All documents mentioned herein are hereby incorporated by reference in their entirety. References to items in the singular should be understood to include items in the plural, and vice versa, unless explicitly stated otherwise or clear from the text.
Recitation of ranges of values herein are not intended to be limiting, referring instead individually to any and all values falling within the range, unless otherwise indicated, and each separate value within such a range is incorporated into the specification as if it were individually recited herein. The words “about,” “approximately,” “substantially,” or the like, when accompanying a numerical value, are to be construed as indicating a deviation as would be appreciated by one of ordinary skill in the art to operate satisfactorily for an intended purpose. Ranges of values and/or numeric values are provided herein as examples only, and do not constitute a limitation on the scope of the described embodiments. The use of any and all examples, or exemplary language (“e.g.,” “such as,” or the like) provided herein, is intended merely to better illuminate the embodiments and does not pose a limitation on the scope of the embodiments. No language in the specification should be construed as indicating any unclaimed element as essential to the practice of the embodiments.
For simplicity and clarity of illustration, reference numerals may be repeated among the figures to indicate corresponding or analogous elements. Numerous details are set forth to provide an understanding of the embodiments described herein. The embodiments may be practiced without these details. In other instances, well-known methods, procedures, and components have not been described in detail to avoid obscuring the embodiments described. The description is not to be considered as limited to the scope of the embodiments described herein.
In the following description, it is understood that terms such as “first,” “second,” “top,” “bottom,” “up,” “down,” “above,” “below,” and the like, are words of convenience and are not to be construed as limiting terms. Also, the terms apparatus and device may be used interchangeably in this text.
As utilized herein, the terms “coupled”, “connected,” and/or similar terms are used generically. It should be understood that these terms are not intended as synonyms. Rather, “connected” is used generically to indicate that two or more components, for example, are in direct physical, including electrical, contact; while, “coupled” is used generically to mean that two or more components are potentially in direct physical, including electrical, contact; however, “coupled” is also used generically to also mean that two or more components are not necessarily in direct contact, but nonetheless are able to co-operate and/or interact. The term “coupled” is also understood generically to mean indirectly connected, for example, in an appropriate context.
The various embodiments and examples of the present disclosure as presented herein are understood to be illustrative of the present disclosure and not restrictive thereof and are non-limiting with respect to the scope of the present disclosure.
Further particular and preferred aspects of the present disclosure are set out in the accompanying independent and dependent claims. Features of the dependent claims may be combined with features of the independent claims as appropriate, and in combinations other than those explicitly set out in the claims.
The present disclosure is directed towards achieving an efficient trade-off between signal latency and data bus utilization in a data processing apparatus, such as a System-on-a-Chip (SoC).
A data processing apparatus may use multiple processor devices inside a chip to scale up performance and reduce latency. A program or task can be broken down into independent steps that can be executed in parallel by multiple devices. When the devices need to share data or control information, they communicate with one another through an on-chip interconnect.
Shared data is often stored off-chip in a main memory (such as DRAM) which is slow to access and consumes a lot of power. Efficiency is improved by using local L2 caches in each processor device that are accessible by other on-chip processor devices. This speeds up the inter-processor communication and reduces power consumption.
However, a mechanism is needed to ensure that any processor gets the latest data, rather than out-of-date or stale data. One approach is to use one or more home nodes in the interconnect to keep track of cache contents and manage memory access requests. A home node is a data handling module that can be considered to be within the interconnect or attached to it. Each home node manages requests for a region of the shared memory. A processing device sends data requests to the appropriate home node, and the home node manages how the request is processed. The processing device is referred to as a requestor node. The home node may serialize requests from all requestor nodes and execute them in serial order so as to maintain data coherency.
The memory space is divided between home nodes and is further divided into units called cache lines. For example, a cache line may contain 32, 64, or 128 bytes of data depending upon the design of the system. Coherency is managed at this level, so data is stored as cache lines in the local caches of processing devices and, when data is requested from a home node, a complete cache line is returned, containing the data associated with the requested address.
When a requestor node wants to access data in a cache line, it sends a request to the home node of the interconnect that is associated with that address. The home node maintains a record, in the form of a snoop filter, for example, of which nodes have a copy of the cache line in a local cache and sends a message, called a snoop request, to the identified node or nodes (the target nodes) requesting the data. Data not stored in local cache may be retrieved from the main memory via a memory controller, for example.
Data is transferred through the interconnect on data buses of a certain width. In addition, each node has a data bus of a certain width. These data bus widths may not be the same. In addition, the bus widths are usually not wide enough to transfer a complete cache line in a single parallel transfer. The cache line must then be split into multiple sections, called ‘beats’ and sent serially. For example, a 64 byte cache line (512 bits) could be sent as four 128-bit beats on a 128-bit data bus, or as two 256-bit beats on a 256-bit data bus. This serialization of the data transfer introduces a delay or latency into the system. Further, when the bus widths are not all the same, bus utilization depends upon how data is split and combined.
In accordance with embodiments of the disclosure, a home node of a data processing apparatus that includes a number of devices coupled via an interconnect is configured to provide efficient transfer of data to a first device from a second device. The home node is configured dependent upon data bus widths of the first and second devices and dependent upon the data bus width of the interconnect. Data is transferred as a cache line serialized into a number of data beats. The home node may be configured to minimize the number of data transfers on the third data bus or to minimize latency in the transfer of the critical beat of the cache line.
The devices may be coupled, via interconnect system 110 and one or more home nodes 112 (HNs) to each other and to data resources such as memory controller 114 for accessing shared memory 116. Devices 102, 104, 106 and 108 are able to generate data access requests and are referred herein as requestor nodes (RNs). When multiple nodes share a data or memory resource, a coherent protocol may be used, and devices may be referred to as fully coherent (e.g. RNF and HNF). Other devices may provide connections to another integrated circuit. Note that many elements of a SoC, such as clocks, have been omitted from
Nodes that generate requests for data transactions, such as ‘load’ and ‘store’, for example, are referred to a requestor node and are end points for such transactions. Nodes that respond to the requests are referred to as target nodes. For example, in
In a data transaction, the requestor node creates a message, comprising one or more packets, and injects it into the interconnect for transmission to its destination. A packet can contain a memory address, data from memory, or both, and may also hold control or routing bits. A control packet, such as a data read request, may contain only address information and control bits. In an on-chip network, a ‘packet’ is the meaningful unit of the upper-layer protocol, such as the cache-coherence protocol.
A packet may be broken into a number of flow-control digits or ‘flits’. A packet can contain a head flit, a body flit, and tail flit. The head denotes the beginning of a packet, containing routing and control information, the body contains the payload of the packet, and the tail denotes when the entire packet has been received. While individual packets may follow different routes in a network, the component flits of a packet are transmitted in sequence over a common route. Thus, a “flit” is the smallest unit of flow control maintained by the network. Generally, a packet consists of one or more number of flits, so if the packet size is larger than one flit, then the packet is split into multiple flits.
A physical channel may contain a data bus, which consists of lines dedicated to data transfer, together with additional lines dedicated to control data and metadata. In one embodiment, the data is divided into a number of chunks and the metadata includes ‘data-validity bits’ that indicate whether a corresponding data chunk contains valid data or not. As discussed below, the ability to transfer data beats that contain both valid and invalid chunks enables data transfer latency to be reduced. Typically, a ‘flit’ will contain a data beat in addition to other information that is transmitted in parallel. For example, the additional information may be validity bits that indicate which parts for data beat are valid and which are invalid. Herein, the action of sending a data beat and sending a flit are considered to be synonymous.
In a cache, data is typically stored as lines of data, for example 64 bytes of data, together with an address tag or line address. For an N-bit address and cache lines of 64 bytes, bits [N−1:6] of the address may be used as the cache line tag or address. The lower six bits of the address (bits [5:0]) denote the offset or position of the data within the cache line. Other length cache lines may be used.
In response to a data read request, a complete cache line is returned. Unless the data bus is the same width as a cache line, the data is sent as a number of data beats. For example, a 128-bit bus can sent 16 bytes at a time, so a 64 byte line is sent as four beats. Beat 0 contains data bytes with indices 15→0 (hexadecimal indices 0x00 to 0x0f), beat 1 contains data bytes with indices 31→16 (hexadecimal indices 0x10 to 0x10, beat 2 contains data bytes with indices 47→32 (hexadecimal indices 0x20 to 0x2f), and beat 3 contains data bytes with indices 63→48 (hexadecimal indices 0x30 to 0x3f). Thus, bits [5:4] of the requested data address indicate which beat contains the requested data bytes.
The time it takes for a flit or message to traverse the interconnect, from the time of injection to the time it is processed at its destination is referred to as latency. The total latency has three major components:
In order to reduce serialization latency, nodes are configured to send the beat containing the requested data bytes first, when responding to a request. The remaining beats may then be sent in ‘wrap’ order to facilitate circular addressing.
Referring again to
Data combiner module 118 can combine multiple incoming flits containing narrow beats (say 128-bit) into a single flit containing a wider beat (say 256-bit) provided that all narrow beats are contiguous in time, do not cross the wider beat boundary, and arrive in a given time window. If incoming (narrower) beats do not arrive in correct order as required by the data combiner, the outgoing (wider) data bus will carry partially-formed data beats thereby resulting in sub-optimal data bus utilization.
In a similar manner, wider beat 210 may be split into narrower beats 202 and 204 by a splitter module and wider beat 212 may be split into narrower beats 206 and 208.
An interconnect system may contain Requestor Nodes (RNFs) with different data bus widths. For example, in
Cache coherency is an issue in any system that contains one or more caches and more than one device sharing data in a single data resource. There are two potential problems with a system that contains caches. Firstly, memory may be updated by another device after a cached device has taken a copy. At this point, the data within the cache is out-of-date or invalid and no longer contains the most up-to-date data. Secondly, systems that contain write-back caches must deal with the case where the device updates the local cached copy, at which point the memory no longer contains the most up-to-date data. A second device reading memory will see out-of-date (stale) data. Cache coherency may be maintained through the exchange of ‘snoop’ messages between the processing devices, such as nodes 102, 104, 106 and 108, for example.
To maintain coherence, each processing device includes a snoop control unit that issues and receives coherence requests and responses, snoop messages, via the interconnect system 110 from other devices.
Snoop requests and responses are managed by home node 112. Home node 112 receives a data read request on interconnect bus 122 or 124, generates corresponding snoop messages on snoop buses 126 and 128, receives data on interconnect buses 130 and/or 132, and returns the data to the requestor node on buses 134 and/or 136. Data not found in any local caches of the target node may be retrieved from other locations, such as a memory via memory controller 114.
In some embodiments, snoop filter 138 is used to reduce the number of snoop messages by tracking which local caches have copies of data and filtering out snoop messages to other local caches.
In the example system shown in
In the example discussed below with reference to
If the home node determines that node RNF-128 has a copy of the requested data, the ADDR is passed as a snoop request (SNP_REQ [01]) 304 towards snoop target RNF-128 without any changes. The response data (SNP_RSP_DATA) is sent as four beats (306, 308, 310 and 312) to the data combiner. A snoop target sends the response data in wrap order, starting with the critical beat first. In this example, the critical beat information is in beat 1 (306), so this beat is sent first followed by the other beats (308, 310, 312) in wrap or cyclic order. If the critical beat happens to be misaligned to wider data bus (e.g. 256 bits) width, the data combiner module will not be able to combine multiple narrow beats into a single wide beat efficiently, thereby resulting in sub-optimal data bus utilization. In the example shown, the data combiner receives beat 1 (306) and waits to see if it can be combined with the next beat. The next beat is beat 2 (308) which cannot be combined, so beat 1 is sent in first flit 314. First flit 314 thus contains a single narrower beat. Beat 3 (310) arrives next and may be combined with beat 2 (308). Thus, second flit 316 contains two narrower beats. Beat 0 (312) arrives last. Since no additional beats are received within a designated time window, third flit 318 is sent containing the single remaining beat.
The home node (HNF-256) performs the final combination of data and it will wait for all sub-beats to arrive before combining them to form the critical beat. As a result, the critical beat (beat 1) is delivered to requestor in flit 320 at time T2, which is later than the delivery of the non-critical beats in flit 322. The transaction latency is the time from T1 until T2.
There are two issues with above transaction flow:
In accordance with a first embodiment of the disclosure, a HNF in an interconnect system is configured to detect the data bus widths of a requestor, a snoop target, and the interconnect system and, based on various data bus widths combination, determine whether and how to align the incoming requested address before sending the address towards snoop target.
The home node HNF-256 determines that snoop target bus (128-bit) is narrower than the Requestor/Interconnect data-bus widths (256-bit), so the home nodes HNF-256 aligns the snoop address to a 256-bit boundary and sends snoop request 404 (SNP_REQ [00]). Thus, the snoop address is the requested address except that ADDR[4] is set to zero to align the address to a 256-bit boundary. Thus the snoop request indicates a request for data in the same cache line, but located in beat 0, rather than beat 1. The snoop target RNF-128, thinking beat 0 is the critical beat, responds with data beats 406, 408, 410 and 412, in contiguous and naturally aligned order. This enables the data combiner to efficiently combine narrow beats into fully-populated flits 414 and 416 when transferring data towards the home node HNF-256. The actual critical beat data (beat 1) is first to reach requestor node in flit 418. The remaining data arrives in flit 420. This scheme minimizes the critical beat latency while maximizing data-bus efficiency, since only two flits (414 and 416) are sent from the home node HNF-256 to the requestor RNF-256.
Snoop address alignment, as described above, solves two issues:
1) The critical beat (beat1) arrives at the requestor first, while non-critical beats arrive later (beat2/beat3). Therefore, the critical beat does not get exposed to any non-critical beat latency.
2) Between the data combiner module and HNF-256, only two 256-bits data beats (414 and 416) are used to transport four beats of 128 bits each, thereby optimizing data bus utilization.
However, there are other scenarios where alignment of a snoop address will result in the best utilization of the data bus, but it may not be ideal for minimizing critical beat latency.
In the transaction shown in
HNF-256 is configured for minimum latency, so as soon as flit 614 is received containing critical beat 1, flit 620 is generated, even though the data beat is not completely filled. Signaling bits, such as data validity bits, are used to indicate to a recipient that the data beat is partially filled and which part of the data should be ignored. Flit 622 is generated when flit 616 is received and flit 624 is generated when flit 618 is received.
As before, the 256-bit beats are separated in the data splitter into split four 128-bit beats (626, 628, 630 and 632) in wrap order with the critical beat being sent first. In this way latency is minimized, since the critical beat 626 (beat 1) arrives at requestor first. However, bus utilization is not optimized since three flits (614, 616 and 618 or 620, 622 and 624) are used for transport in the interconnect.
The approaches described above enable a user or designer to configure an interconnect system for optimal latency or for optimal bus utilization. In some cases these may be achieved together. In one embodiment, the configuration may be performed dynamically using software controlled configuration registers, for example.
If the full critical word is not available in the cache line buffer in the home node, as depicted by the negative branch from decision block 810, or if the system is not optimized for minimum latency, as depicted by the negative branch from decision block 808, flow continues to decision block 816. If the cache line buffer has sufficient data available to fully populate the interconnect bus width, as depicted by the positive branch from decision block 816, the buffered data is forwarded to the requestor node at block 818. If the cache line buffer does not contain sufficient data to fill an outgoing beat, as depicted by the negative branch from decision block 816, no action is taken until additional snoop data is received and the method ends at termination block 814.
Thus, in accordance with various embodiments of the disclosure, a home node (HNF) is configured to respond to the data request dependent upon the following configuration parameters:
Based upon the above information, the home node determines if, and how, to align the address in the snoop request and whether to send partial critical data beat to requestor. The actions of the home node are summarized in Table 1 below.
One benefit of the approach discussed above is improved data bus utilization. Table 2 summarizes the improvement in an example data processing apparatus having
1. Requestor bus width (REQ_BW)=256 bits.
2. Snoop target bus width (SNP_BW)=128 bits.
3. Interconnect bus width (ICN_BW)=256 bits.
Assuming equal distribution of address offsets within cache lines, there is 20% savings on Data Bus utilization. That is, 20% less snoop response data traffic on the interconnect data bus between the Data Combiner and home node (HNF).
Those skilled in the art will recognize that the present invention may be implemented using a programmed processor, reconfigurable hardware components, dedicated hardware components or combinations thereof. Similarly, general purpose computers, microprocessor based computers, micro-controllers, optical computers, analog computers, dedicated processors and/or dedicated hard wired logic may be used to construct alternative equivalent embodiments of the present invention.
Dedicated or reconfigurable hardware components may be described by instructions of a Hardware Description Language. These instructions may be stored on non-transient computer readable medium such as Electrically Erasable Programmable Read Only Memory (EEPROM); non-volatile memory (NVM); mass storage such as a hard disc drive, floppy disc drive, optical disc drive; optical storage elements, magnetic storage elements, magneto-optical storage elements, flash memory, core memory and/or other equivalent storage technologies without departing from the present invention. Such alternative storage devices should be considered equivalents.
The various representative embodiments, which have been described in detail herein, have been presented by way of example and not by way of limitation. It will be understood by those skilled in the art that various changes may be made in the form and details of the described embodiments resulting in equivalent embodiments that remain within the scope of the appended claims.
Number | Name | Date | Kind |
---|---|---|---|
5966729 | Phelps | Oct 1999 | A |
6128707 | Arimilli | Oct 2000 | A |
6298424 | Lewchuk | Oct 2001 | B1 |
6519685 | Chang | Feb 2003 | B1 |
6546447 | Buckland et al. | Apr 2003 | B1 |
6598123 | Anderson | Jul 2003 | B1 |
6799252 | Bauman | Sep 2004 | B1 |
6810467 | Khare | Oct 2004 | B1 |
6868481 | Gaither | Mar 2005 | B1 |
7117311 | Rankin | Oct 2006 | B1 |
7117312 | Cypher | Oct 2006 | B1 |
7240165 | Tierney | Jul 2007 | B2 |
7325102 | Cypher | Jan 2008 | B1 |
7613882 | Akkawi | Nov 2009 | B1 |
7685409 | Du | Mar 2010 | B2 |
7698509 | Koster | Apr 2010 | B1 |
7836144 | Mannava | Nov 2010 | B2 |
7925840 | Harris et al. | Apr 2011 | B2 |
7937535 | Ozer | May 2011 | B2 |
8392665 | Moga et al. | Mar 2013 | B2 |
8423736 | Blake | Apr 2013 | B2 |
8638789 | Pani | Jan 2014 | B1 |
8935485 | Jalal | Jan 2015 | B2 |
9058272 | O'Bleness et al. | Jun 2015 | B1 |
9166936 | Stovall | Oct 2015 | B1 |
9507716 | Salisbury | Nov 2016 | B2 |
9575893 | Lin et al. | Feb 2017 | B2 |
9639469 | Moll et al. | May 2017 | B2 |
9652404 | Pierson et al. | May 2017 | B2 |
9727466 | Tune et al. | Aug 2017 | B2 |
9767026 | Niell et al. | Sep 2017 | B2 |
9817760 | Robinson et al. | Nov 2017 | B2 |
9830265 | Rowlands et al. | Nov 2017 | B2 |
9830294 | Mathewson et al. | Nov 2017 | B2 |
9870209 | Kelm et al. | Jan 2018 | B2 |
20020087811 | Khare et al. | Jul 2002 | A1 |
20020147889 | Kruckemyer et al. | Oct 2002 | A1 |
20020184460 | Tremblay | Dec 2002 | A1 |
20030028819 | Chiu | Feb 2003 | A1 |
20030070016 | Jones et al. | Apr 2003 | A1 |
20030105933 | Keskar | Jun 2003 | A1 |
20030115385 | Adamane | Jun 2003 | A1 |
20030131202 | Khare | Jul 2003 | A1 |
20030140200 | Jamil et al. | Jul 2003 | A1 |
20030163649 | Kapur | Aug 2003 | A1 |
20030167367 | Kaushik | Sep 2003 | A1 |
20040003184 | Safranek | Jan 2004 | A1 |
20040117561 | Quach | Jun 2004 | A1 |
20040193809 | Dieffenderfer et al. | Sep 2004 | A1 |
20050005073 | Pruvost et al. | Jan 2005 | A1 |
20050160430 | Steely, Jr. et al. | Jul 2005 | A1 |
20050201383 | Bhandari et al. | Sep 2005 | A1 |
20060080508 | Hoover et al. | Apr 2006 | A1 |
20060080512 | Hoover et al. | Apr 2006 | A1 |
20060136680 | Borkenhagen | Jun 2006 | A1 |
20060224835 | Blumrich et al. | Oct 2006 | A1 |
20060224836 | Blumrich et al. | Oct 2006 | A1 |
20060224838 | Blumrich | Oct 2006 | A1 |
20060224840 | Blumrich et al. | Oct 2006 | A1 |
20070005899 | Sistla | Jan 2007 | A1 |
20070073879 | Tsien | Mar 2007 | A1 |
20070079044 | Mandal et al. | Apr 2007 | A1 |
20070186054 | Kruckemyer | Aug 2007 | A1 |
20070239941 | Looi | Nov 2007 | A1 |
20080005485 | Gilbert | Jan 2008 | A1 |
20080005486 | Mannava et al. | Jan 2008 | A1 |
20080120466 | Oberlaender | May 2008 | A1 |
20080209133 | Ozer et al. | Aug 2008 | A1 |
20080243739 | Tsien | Oct 2008 | A1 |
20080244193 | Sistla et al. | Oct 2008 | A1 |
20080320232 | Vishin et al. | Dec 2008 | A1 |
20080320233 | Kinter | Dec 2008 | A1 |
20090158022 | Radhakrishnan et al. | Jun 2009 | A1 |
20090300289 | Kurts | Dec 2009 | A1 |
20110179226 | Takata | Jul 2011 | A1 |
20120099475 | Tokuoka | Apr 2012 | A1 |
20120144064 | Parker | Jun 2012 | A1 |
20120198156 | Moyer | Aug 2012 | A1 |
20130042070 | Jalal et al. | Feb 2013 | A1 |
20130042078 | Jalal et al. | Feb 2013 | A1 |
20130051391 | Jayasimha | Feb 2013 | A1 |
20140032853 | Lih | Jan 2014 | A1 |
20140052905 | Lih et al. | Feb 2014 | A1 |
20140082297 | Solihin | Mar 2014 | A1 |
20140095801 | Bodas et al. | Apr 2014 | A1 |
20140095806 | Fajardo | Apr 2014 | A1 |
20140095808 | Moll et al. | Apr 2014 | A1 |
20140181394 | Hum et al. | Jun 2014 | A1 |
20140189239 | Hum | Jul 2014 | A1 |
20140223104 | Solihin | Aug 2014 | A1 |
20140281180 | Tune | Sep 2014 | A1 |
20140317357 | Kaplan | Oct 2014 | A1 |
20140372696 | Tune et al. | Dec 2014 | A1 |
20150074357 | McDonald et al. | Mar 2015 | A1 |
20150095544 | Debendra | Apr 2015 | A1 |
20150103822 | Gianchandani | Apr 2015 | A1 |
20150127907 | Fahim et al. | May 2015 | A1 |
20150286577 | Solihin | Oct 2015 | A1 |
20150324288 | Rowlands | Nov 2015 | A1 |
20160041936 | Lee et al. | Feb 2016 | A1 |
20160055085 | Salisbury et al. | Feb 2016 | A1 |
20160062889 | Salisbury | Mar 2016 | A1 |
20160062890 | Salisbury | Mar 2016 | A1 |
20160062893 | Tune | Mar 2016 | A1 |
20160117249 | Lin et al. | Apr 2016 | A1 |
20160147661 | Ambroladze | May 2016 | A1 |
20160147662 | Drapala | May 2016 | A1 |
20160188471 | Forrest et al. | Jun 2016 | A1 |
20160210231 | Huang et al. | Jul 2016 | A1 |
20160216912 | Muralimanohar | Jul 2016 | A1 |
20160283375 | Das Sharma | Sep 2016 | A1 |
20170024320 | Forrest et al. | Jan 2017 | A1 |
20170091101 | Lin et al. | Mar 2017 | A1 |
20170168939 | Jalal et al. | Jun 2017 | A1 |
20170185515 | Fahim et al. | Jun 2017 | A1 |
Entry |
---|
A. Moshovos, G. Memik, B. Falsafi and A. Choudhary, “JETTY: filtering snoops for reduced energy consumption in SMP servers,” Proceedings HPCA Seventh International Symposium on High-Performance Computer Architecture, Monterrey, 2001, pp. 85-96. |