Claims
- 1. A data processor comprising:an instruction decoder for decoding an instruction including a plurality of operation fields and an execution order specifying field which specifies the order of execution of the plurality of operation fields; an execution unit which receives decoded results from said instruction decoder, for performing operations specified by the plurality of operation fields, said execution unit performing the operations in parallel when said execution order specifying field has a first value, and performing the operations serially when said execution order specifying field has a second value, wherein said execution order specifying field includes a plurality of sub-fields provided corresponding to the plurality of operation fields and arranged separately and adjacently to the corresponding operation fields in said instruction.
- 2. The data processor of claim 1, wherein each sub-field in the execution order specifying field and the corresponding operation field has N bytes in total.
- 3. The data processor of claim 1, wherein each sub-field has one bit.
- 4. A data processor comprising:an instruction decoder for decoding a plurality of operation fields and an execution order specifying field which specifies the order of execution of the plurality of operation fields; and an execution unit which receives decoded results from said instruction decoder, for performing operations specified by the plurality of operation fields, said execution unit performing the operations in parallel when said execution order specifying field has a first value, and performing the operations serially when said execution order specifying field has a second value, wherein said execution order specifying field includes a plurality of sub-fields provided corresponding to the plurality of operation fields and arranged separately and adjacently to the corresponding operation fields.
- 5. The data processor of claim 4, wherein each sub-field in the execution order specifying field and the corresponding operation field has N bytes in total.
- 6. The data processor of claim 4, wherein each sub-field has one bit.
Priority Claims (1)
Number |
Date |
Country |
Kind |
7-176380 |
Jul 1995 |
JP |
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Parent Case Info
This application is a divisional of application Ser. No. 09/056,650, filed Apr. 8, 1998, U.S. Pat. No. 6,115,806, which is a continuation of 08/574,282 filed Dec. 18,1995, U.S. Pat. No. 5,761,470.
US Referenced Citations (11)
Foreign Referenced Citations (2)
Number |
Date |
Country |
3-147021 |
Jun 1991 |
JP |
6-309166 |
Nov 1994 |
JP |
Non-Patent Literature Citations (1)
Entry |
“Performance Evaluation of Superscalar Processor, 'SHIMPU' based on the SIMP (Single Instruction Stream/Multiple Instruction Pipeline Architecture”, JSPP “Parallel Processing Symposium”, '90, May 1990, pp. 337-344, by Kuga et al., (Interdisciplinary Graduate School of Engineering Sciences, Kyushu University). |
Continuations (1)
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Number |
Date |
Country |
Parent |
08/574282 |
Dec 1995 |
US |
Child |
09/056650 |
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US |