DDR COUNTER CIRCUITS, ANALOG TO DIGITAL CONVERTERS, IMAGE SENSORS AND DIGITAL IMAGING SYSTEMS INCLUDING THE SAME

Abstract

A counter circuit for an analog to digital converter includes: a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of a reset counting phase, but a same or different state at start of a signal, counting phase depending on the state of the output clock at the end of the reset counting phase.

Description

BACKGROUND

An image sensor converts an optical image into an electrical signal. Types of image sensors include charge-coupled devices (CCDs) and complementary-metal-oxide-semiconductor (CMOS) image sensors. Image sensors are commonly used in digital cameras as well as other imaging devices.

Image sensors include pixels, which accumulate charge when illuminated by light. Conventionally, pixels accumulate charge in an analog circuit for a continuous period of time referred to as an exposure time. The accumulated charge is transferred to an analog-to-digital (A/D) converter (ADC), which converts the accumulated charge into a digital value for that pixel. A conventional image sensor outputs a two-dimensional (2D) array of digital values.

SUMMARY

At least one example embodiment provides a counter circuit for an analog to digital converter (ADC). The counter circuit includes: a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of a reset counting phase, but a same or different state at start of a signal counting phase depending on the state of the output clock at the end of the reset counting phase.

At least one other example embodiment provides an analog to digital converter. The analog to digital converter includes: a comparator circuit; a counter bank; and a line memory. The comparator circuit is configured to generate a comparison signal corresponding to each column of a pixel array. Each comparison signal is generated based on a comparison between an input signal corresponding to a column of the pixel array and a ramp signal. The counter bank is configured to convert each of the generated comparison signals into a digital output signal. The counter bank includes at least one counter circuit having a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of a reset counting phase, but a same or different state at start of a signal counting phase depending on the state of the output clock at the end of the reset counting phase. The line memory is configured to store the digital outputs from the counter bank.

At least one other example embodiment provides an image sensor. The image sensor includes an active pixel array; a line driver; and an analog to digital converter. The active pixel array includes a plurality of pixels arranged in an array. The line driver is configured to select rows of pixels for output by the active pixel array.

The analog to digital converter is configured to convert outputs from the active pixel array into digital output code. The analog to digital converter includes: a comparator circuit; a counter bank; and a line memory. The comparator circuit is configured to generate a comparison signal corresponding to each column of a pixel array. Each comparison signal is generated based on a comparison between an input signal corresponding to a column of the pixel array and a ramp signal. The counter bank is configured to convert each of the generated comparison signals into a digital output signal. The counter bank includes at least one counter circuit having a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of a reset counting phase, but a same or different state at start of a signal counting phase depending on the state of the output clock at the end of the reset counting phase. The line memory is configured to store the digital outputs from the counter bank.

At least one other example embodiment provides a digital imaging system. The digital imaging system includes: a processor configured to process captured image data; and an image sensor configured to capture image data by converting optical images into electrical signals. The image sensor includes an active pixel array; a line driver; and an analog to digital converter. The active pixel array includes a plurality of pixels arranged in an array. The line driver is configured to select rows of pixels for output by the active pixel array.

The analog to digital converter is configured to convert outputs from the active pixel array into digital output code. The analog to digital converter includes: a comparator circuit; a counter bank; and a line memory. The comparator circuit is configured to generate a comparison signal corresponding to each column of a pixel array. Each comparison signal is generated based on a comparison between an input signal corresponding to a column of the pixel array and a ramp signal. The counter bank is configured to convert each of the generated comparison signals into a digital output signal. The counter bank includes at least one counter circuit having a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of a reset counting phase, but a same or different state at start of a signal counting phase depending on the state of the output clock at the end of the reset counting phase. The line memory is configured to store the digital outputs from the counter bank.

According to at least some example embodiments, the counter circuit may further include: a plurality of counter stages connected in series with the latch stage. Each of the plurality of counter stages may be configured to toggle a state of an output clock in response to a change in state of the output clock from a preceding stage.

Each of the plurality of counter stages may include: a bit-wise inversion circuit configured to selectively peform a bit-wise inversion operation on the output clock from a previous counter stage in response to at least one bit-wise inversion signal, and to output an inverted state of the output clock from a previous counter stage; and a counter cell configured to toggle a state of an output clock in response to a change in state of the output from the bit-wise inversion circuit.

The latch stage may further include: a first latch configured to output a first latch output clock based on the input clock; a logic gate configured to generate the latch stage output clock by performing a logic operation on first latch output clock and a second latch output clock; and a second latch configured to output the second latch output clock based on the latch stage output clock.

Additionally, the latch stage may include: an inverter configured to invert a state of the latch stage output clock and output the inverted state of the latch stage output clock to the second latch. The second latch may be configured to output the second latch output clock based on the inverted state of the latch stage output clock.

According to at least some example embodiments, the counter circuit may include: a plurality of counter stages connected in series with the latch stage. Each of the plurality of counter stages may be configured to output one of an up counting output clock and a down counting output clock in response to an output clock from a preceding counter stage. The up counting output and the down counting output clock may have opposite states.

The counter circuit may further include: a selection circuit configured to separate the latch stage from the plurality of counter stages in response to a latch output selection signal.

Each of the plurality of counter stages may include: a counter cell configured to output the up counting output clock and the down counting output clock in response to the output clock from a preceding counter stage; and a multiplexer configured to selectively output one of the up counting output clock and the down counting output clock to a subsequent counter stage in response to a count signal.

According to at least some example embodiments, the counter bank may further include: a plurality of counter circuits. Each of the plurality of counter circuits may correspond to a column of the pixel array. Each of the plurality of counter circuits may include a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of the reset counting phase, but a same or different state at start of the signal counting phase depending on the state of the output clock at the end of the reset counting phase.

BRIEF DESCRIPTION OF THE DRAWINGS

Example embodiments will become more appreciable through the description of the drawings in which:

FIG. 1 is a block diagram of an image sensor according to an example embodiment;

FIGS. 2A and 2B are block diagrams showing more detailed illustrations of analog-to-digital converters (ADCs) according to example embodiments;

FIG. 3 illustrates a digital imaging system according to an example embodiment;

FIG. 4 shows a conventional ripple counter;

FIG. 5 shows a double data rate (DDR) ripple counter according to an example embodiment;

FIG. 6 shows a correlated double sampling (CDS) subtraction by an up/down counter;

FIG. 7 shows a conventional up/down counter;

FIG. 8 shows CDS subtraction by bit-wise inversion (BWI);

FIG. 9 shows a counter with a bit-wise inversion function and an example implementation of a BWI block according to an example embodiment;

FIG. 10 shows a timing diagram for CDS using bit-wise inversion according to an example embodiment;

FIG. 11 shows an example first stage of a DDR counter according to an example embodiment;

FIG. 12 shows a timing diagram of a least significant bit (LSB) bitwise operation according to an example embodiment;

FIG. 13 shows an architecture for a DDR counter with bit-wise inversion according to an example embodiment;

FIG. 14 shows an example first stage for a DDR UP/DOWN FF-based counter according to an example embodiment;

FIG. 15 shows a timing diagram of a LSB bitwise operation for an UP/DOWN flipflop (FF)-based DDR counter according to an example embodiment; and

FIG. 16 shows an architecture for an UP/DOWN FF-based DDR counter according to an example embodiment.

DETAILED DESCRIPTION

Example embodiments will now be described more fully with reference to the accompanying drawings. Many alternate forms may be embodied and example embodiments should not be construed as limited to example embodiments set forth herein. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity, and like reference numerals refer to like elements.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.

It will be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, there are no intervening elements present. Other words used to describe the relationship between elements should be interpreted in a like fashion (e.g., “between” versus “directly between,” “adjacent” versus “directly adjacent,” etc.).

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments. As used herein, the singular fauns “a,” “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “includes” and/or “including,” when used herein, specify the presence of stated features, integers, steps, operations, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and groups thereof.

Unless specifically stated otherwise, or as is apparent from the discussion, terms such as “processing” or “computing” or “calculating” or “determining” or “displaying” or the like, refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical, electronic quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

At least one example embodiment provides a ripple-counter circuit. Example embodiments may also provide counters and counter circuits with digital gains correlated to a ramp signal.

As will be described in more detail below, example embodiments may be implemented in conjunction with a Gray code counter (GCC) and/or a per-column binary counter. As discussed herein, example embodiments may be implemented as a double data rate (DDR) counter, which may further improve power consumption.

In another example, a per-column implementation may perform bit-wise inversion for correlated double sampling (CDS) subtraction. In addition, the same or substantially the same digital gain concepts may be applied to any ripple counter.

FIG. 1 illustrates a complementary-metal-oxide-semiconductor (CMOS) image sensor according to an example embodiment.

Referring to FIG. 1, a timing unit or circuit 106 controls a line driver 102 through one or more control lines CL. In one example, the timing unit 106 causes the line driver 102 to generate a plurality of read and reset pulses. The line driver 102 outputs the plurality of read and reset pulses to a pixel array 100 over a plurality of read and reset lines RRL. Although this disclosure refers to “read and reset lines” RRL as well as “reset signals” and “read and reset pulses,” it should be noted that pixel reset and pixel readout are performed by a sequence of pulses on the same pixel controls (e.g., transfer, reset and select).

The pixel array 100 includes a plurality of pixels arranged in an array of rows ROW_1-ROW_N and columns COL_1-COL_N. Each of the plurality of read and reset lines RRL corresponds to a row of pixels in the pixel array 100. In FIG. 1, each pixel may be an active-pixel sensor (APS), and the pixel array 100 may be an APS array.

In more detail with reference to example operation of the image sensor in FIG. 1, read and reset pulses for an i-th row ROW_i (where i={1, . . . , N}) of the pixel array 100 are output from the line driver 102 to the pixel array 100 via an i-th one of the read and reset lines RRL. In one example, the line driver 102 applies a reset signal to the i-th row ROW_i of the pixel array 100 to begin an exposure period. After a given, desired or predetermined exposure time, the line driver 102 applies a read signal to the same i-th row ROW_i of the pixel array 100 to end the exposure period. The application of the read signal also initiates reading out of pixel information (e.g., exposure data) from the pixels in the i-th row ROW_i.

The analog-to-digital converter (ADC) 104 converts the output voltages from the i-th row ROW_i of readout pixels into a digital signal (or digital data). The ADC 104 may perform this conversion either serially or in parallel. An ADC 104 having a column parallel-architecture converts the output voltages into a digital signal in parallel. The ADC 104 then outputs the digital data (or digital code) DOUT to a next stage processor such as an image signal processor (ISP) 108, which processes the digital data DOUT to generate an image. In one example, the ISP 108 may also perform image processing operations on the digital data including, for example, gamma correction, auto white balancing, application of a color correction matrix (CCM), and handling chromatic aberrations.

FIGS. 2A and 2B show more detailed example illustrations of the ADC shown in FIG. 1.

Referring to FIG. 2A, a ramp generator 1040 generates or ramp signal VRAMP and outputs the generated ramp signal VRAMP to the comparator bank 1042. As shown in FIGS. 3-5, the ramp signal VRAMP is voltage signal which changes over time. The comparator bank 1042 compares the ramp signal VRAMP with each output from the pixel array 100 to generate a plurality of comparison signals VCOMP.

In more detail, the comparator bank 1042 includes a plurality of comparators 1042_COMP. Each of the plurality of comparators 1042_COMP corresponds to one of columns COL_1-COL_N of pixels P in the pixel array 100. In example operation, each comparator 1042_COMP generates a comparison signal VCOMP by comparing the output of a corresponding pixel to the ramp signal VRAMP. The toggling time of the output of each comparator 1042_COMP is correlated to the pixel output voltage.

The comparator bank 1042 outputs the comparison signals VCOMP to a counter bank 1044, which converts the comparison signals VCOMP into digital output signals.

In more detail, the counter bank 1044 includes a counter for each of columns COL_1-COL_N of the pixel array 100 and each counter converts a corresponding comparison signal VCOMP into a digital output signal. Counter circuits of the counter bank 1044 according to example embodiments will be discussed in more detail later. The counter bank 1044 outputs the digital output signals to a line memory 1046.

The line memory 1046 stores the digital data from the counter bank 1044 while output voltages for a next row (e.g., ROW_i+1) of pixels are converted into digital output signals.

Referring to FIG. 2B, in this example the comparator 1042 outputs the comparison signals VCOMP to the line memory 1048 as opposed to the binary counter bank 1044 shown in FIG. 2A. Otherwise, the ramp generator 1040 and the comparator bank 1042 are the same as described above with regard to FIG. 2A.

A Gray code counter (GCC) 1050 is coupled to the line memory 1048. In this example, the GCC 1050 generates a sequentially changing Gray code.

The line memory 1048 stores the sequentially changing Gray code from the GCC 1050 at a certain time point based on the comparison signals VCOMP received from the comparator bank 1042. The stored Gray code represents the intensity of light received at the pixel or pixels.

FIG. 3 is a block diagram illustrating a digital imaging system according to an example embodiment.

Referring to FIG. 3, a processor 302, an image sensor 300, and a display 304 communicate with each other via a bus 306. The processor 302 is configured to execute a program and control the digital imaging system. The image sensor 300 is configured to capture image data by converting optical images into electrical signals. The image sensor 300 may be an image sensor as described above with regard to FIGS. 1, 2A or 2B. The processor 302 may include the image signal processor 108 shown in FIG. 1, and may be configured to process the captured image data for storage in a memory (not shown) and/or display by the display unit 304. The digital imaging system may be connected to an external device (e.g., a personal computer or a network) through an input/output device (not shown) and may exchange data with the external device.

For example, the digital imaging system shown in FIG. 3 may embody various electronic control systems including an image sensor (e.g., a digital camera), and may be used in, for example, mobile phones, personal digital assistants (PDAs), laptop computers, netbooks, tablet computers, MP3 players, navigation devices, household appliances, or any other device utilizing an image sensor or similar device.

Referring back to FIGS. 2A and 2B, in either architecture the counter 1044/1050 begins running when the ramp signal VRAMP starts falling. When the output VCOMP of a comparator 1042_COMP toggles, the ramp code for the corresponding pixel is (VSTART-VIN), where VSTART is the start voltage of the ramp signal VRAMP and VIN is the voltage input to the comparator 1042_COMP from the pixel array 100. The resultant digital output code DOUT is stored in the line buffer (for each column separately) and read out by an image signal processor.

FIG. 4 illustrates a conventional ripple counter circuit, which may be included in the counter 1044 and 1050 shown in FIGS. 2A and 2B.

As shown in FIG. 4, the counter circuit includes a plurality of T-flip-flops T-FF0, T-FF1, T-FF2, T-FF3, . . . , T-FF(N−1) connected in series with one another. In the counter circuit shown in FIG. 4, the power P₀ consumed by the first flip-flop T-FF0 is given by Equation (1) shown below.

P ₀ =f×V _dd ² ×C _TFF   (1)

Equation (1), f is the frequency of the input clock D_CLK_f, V_dd is the supply voltage to the first flip-flop T-FF0 and C_TFF is the effective capacitance of the first flip-flop T-FF0.

Because each of flip-flops T-FF1, T-FF2, T-FF3, . . . , T-FFN−1 switches at half the frequency of the preceding flip-flop, the total power consumption P_tot for the counter circuit shown in FIG. 4 is given by Equation (2) assuming all counters are identical.

$\begin{array}{cc}{P}_{\mathrm{tot}}=\sum _{i=1}^NP_i=V_{\mathrm{dd}}^2C_{\mathrm{TFF}}\sum _{i=1}^N\frac{f}{2^i}=2{\mathrm{fV}}_{\mathrm{dd}}^2C_{\mathrm{TFF}}\left(1-\frac{1}{2^{N+2}}\right)\le 2P_0& \left(2\right)\end{array}$

Example embodiments provide double data rate (DDR) counter circuits in which the first counter stage is replaced by a latch circuit such that the input clock is used as the least significant bit (LSB) D<0> of the output data, and the input clock rate is reduced by about half. By replacing the first counter stage with a latch circuit, the power consumption of the counter circuit may also be reduced by at least about 50%. But, the actual reduction in power consumption may depend on the number of bits in the counter and/or the complexity of the latch circuit. The power consumption may be further reduced by lowering the frequency of clock generator (PLL) (not shown) and/or lowering power consumption on the wire connecting the PLL to the counter circuit.

FIG. 5 illustrates an example embodiment of a double data rate (DDR) counter circuit in which the initial stage 50 is a latch stage, rather than a counter stage. The counter circuit shown in FIG. 5, along with the other example embodiments discussed herein may be implemented as a counter circuit in the per-column binary counter 1044 and/or the GCC 1050 shown in FIGS. 2A and 2B.

Referring to FIG. 5, the counter circuit includes a plurality of (e.g., N) stages 50, 51, 52, 53, . . . , 5(N−1) connected in series. The initial or latch stage 50 includes a latch circuit 50L, whereas each of the plurality of subsequent stages 51, 52, 53, . . . , 5(N−1) include a respective one of a plurality of counter cells T-FF51, T-FF52, T-FF53, T-FF5(N−1). In this example, each of the counter cells T-FF51, T-FF52, T-FF53, . . . , T-FF5(N−1) is a T-flip-flop. Because T-flip-flops and T-flip-flop circuits are generally known, a detailed discussion is omitted.

In the counter circuit shown in FIG. 5, the latch circuit 50L is configured to generate, between a reset counting phase and a signal counting phase of an image sensor, a latch stage output clock Q₀ based on a state of an input clock D_CLK_f/2 such that the latch stage output clock Q₀ and the input clock D_CLK_f/2 have a same state at the start of the reset counting phase and a same or different state at the start of the signal counting phase depending on the state of the latch stage output clock Q₀ at the end of the reset counting phase.

In example operation, the latch circuit 50L outputs the latch stage output clock Q₀ while enabled, but stores the state of the input clock D_CLK_f/2 in response to the falling edge of stop signal STOP (e.g., when the latch, circuit 50L stops running or is disabled). While enabled, the latch stage output clock Q₀ transitions (e.g., from high ‘H’ to low ‘H’ or from low to high) in response to a transition or change in state of the input clock D_CLK_f/2. The latch circuit 50L outputs the latch stage output clock Q₀ to the first counter cell T-FF51 of the first counter stage 51.

The first counter stage 51 generates a first counter stage output clock Q₁ based on the latch stage output clock Q₀. In so doing, the first counter cell T-FF51 toggles the state (e.g., from low to high or high to low) of the first counter stage output clock Q₁ based on a change in the state of the latch stage output clock Q₀. For example, the first counter cell T-FF51 toggles the state of the first counter stage output clock Q₁ as the latch stage output clock Q₀ rises (e.g., in response to a transition from low to high). The first counter cell T-FF51 outputs the first counter stage output clock Q₁ to the second counter cell T-FF52 of the second counter stage 52.

The second stage 52 generates a second counter stage output clock Q₂ based on the first counter stage output clock Q₁. In so doing, the second counter cell T-FF52 toggles the state (e.g., from low to high or high to low) of the second counter stage output clock Q₂ based on a change in the state of the first counter stage output clock Q₁. For example, the second counter cell T-FF52 toggles the state of the second counter stage output clock Q₂ as the first counter stage output clock Q₁ rises (e.g., in response to a transition from low to high). The second stage 52 outputs the second counter stage output clock Q₁ to the third counter cell T-FF53 of the third counter stage 53.

Each subsequent counter stage 53-5(N−1) generates a corresponding counter stage output clock Q₃, Q_N−1 based on a counter stage output clock from a preceding counter stage in the same or substantially the same manner as described above to generate a resultant digital output code DOUT (including D<0>, D<1>, D<2>, D<3>, . . . , D<N−1>, where D<0> is the LSB), which is stored in a line buffer (for each column separately), and read out by an image signal processor.

As mentioned above and as can be appreciated by comparing FIGS. 4 and 5, the DDR counter circuit shown in FIG. 5 differs from conventional counter circuits at least in that the first stage includes a latch circuit, and the frequency of the input clock is reduced by about half. By replacing the initial counter stage with a latch stage, power consumption may be reduced by about 50%.

Moving forward, a counter circuit normally has the ability to subtract a reset reading from the signal reading in order to apply digital correlated double sampling (CDS) in image sensors. This may be achieved by an UP/DOWN counter circuit, which counts down during a reset counting phase (e.g., during reset voltage conversion), but counts up during a signal counting phase (e.g., during signal voltage conversion). An example timing diagram illustrating this counting function is shown in FIG. 6, and an example counter circuit capable of performing this UP/DOWN counting is shown in FIG. 7.

Referring to FIG. 7, the counter circuit includes a plurality of counter stages 70, 71, 72, . . . , 7(N−1) connected in series with one another.

Each of the counter stages 70 through 7(N−1) includes a counter cell T-FF7 and a multiplexer MUX. Each counter cell T-FF7 is a special flip-flop circuit capable of outputting both an up output clock Q_n and a down output clock Q_n, where n is 0, 1, . . . , (N−1).

The first counter stage 70 is configured to output first up output clock Q₀ and first down output clock Q₀ based on the input clock CLK₀. The first multiplexer MUX selectively outputs one of the first up output clock Q₀ and first down output clock Q₀ as the first counter stage output clock CLK₁ based on a count signal UP/DOWN.

In each subsequent one of the counter stages 71 through 7(N−1), the counter cell T-FF7 is configured to output the up output clock Q_n and the down counter output clock Q_n based on the counter stage output clock from a preceding counter stage. The multiplexer MUX in each counter stage then selectively outputs one of the up counter output clock Q_n and the down counter output clock Q_n to a subsequent counter stage as the counter stage output clock CLK_n+1 based on the count signal UP/DOWN.

In more detail referring to FIGS. 6 and 7, during the reset counting phase, the multiplexers MUX output the down counter clock Q_n such that the counter circuit counts down during the reset counting phase. By contrast, during the signal counting phase, the multiplexers MUX of each counter stage 70 through 7(N−1) output counter clock Q_n such that the counter circuit counts up during a signal counting phase.

In an alternative example, bit-wise inversion (BWI) is used between the reset counting phase and the signal counting phase. FIG. 9 is an example ripple counter circuit configured to support subtraction, which is required for digital CDS, by bitwise inversion. FIG. 8 illustrates CDS subtraction by bitwise inversion. FIG. 10 is a timing diagram illustrating example operation of the counter circuit shown in FIG. 9.

Referring to FIG. 9, the counter circuit includes a plurality of counter stages 90, 91, 92, . . . , 9(N−1) connected in series. The first counter stage 90 includes a counter cell (e.g., T flip-flop) T-FF9, whereas each of the counter stages 91, 92, . . . , 9(N−1) includes a bitwise inversion circuit BWI coupled to a counter cell T-FF9 such that each pair of adjacent counters is separated by a bit-wise inversion cell BWI.

During normal operation (e.g., the counting phase), first bitwise inversion clock CONV1 is “0”, whereas second bitwise inversion clock CONV2 is “1”. In this case, the bitwise inversion cell BWI acts as an inverter. An example bitwise inversion operation is described below. For the sake of brevity and clarity, example bitwise inversion operation will be discussed with regard to counter stage 91. However, each counter cell may operate in the same or substantially the same manner.

Initially, first bitwise inversion clock CONV1 transitions to “1”, which pulls down the output of bitwise inversion cell BWI (of counter stage 91) to “0”. Because the counter cell T-FF9 is assumed to be sensitive only to the rising edge of its input clock, the first bitwise inversion clock CONV1 does not cause any toggling of counter cell T-FF9.

The second bitwise inversion clock CONV2 then transitions to “0”, which has no effect on the output from the bitwise inversion cell BWI.

The first bitwise inversion clock CONV1 also falls to “0.” At this point, the output from the bitwise inversion cell BWI rises, which causes a transition in the output of the counter cell T-FF9. The second bitwise inversion clock CONV2 then rises, which causes the bitwise inversion cell BWI to again operate as an inverter. The output of the bitwise inversion cell BWI either remains at “1” or falls to “0”, depending on its input. In any case, this does not cause any change in the output of the counter cell T-FF9, which is only sensitive to rising edges.

As mentioned above, FIG. 8 illustrates CDS subtraction by bitwise inversion, and FIG. 10 is a timing diagram illustrating example operation of the counter circuit shown in FIG. 9.

Referring to FIGS. 8 and 10, initially, the counter circuit is set (to all “1” values) by a reset RST pulse.

Reset counting is then applied by enabling the input clock CLK0 input into the first stage 90 of the counter circuit. In one example, N clock cycles (e.g., 0 to N−1) are counted. Bitwise inversion, as described above, is then applied. The output code then goes from N−1 to −N.

Signal counting is then enabled by re-enabling the input clock CLK₀. In this case, the clock is enabled for M clock cycles, which causes the final output code to be M−N.

By using the counter circuit architecture shown in FIG. 9, the counter circuit may be composed of standard T-flip-flops as well as BWI circuits for the one-time inversion of all bits of the counter circuit. In this example, only one rising-edge in the input clock CLK_n of each counter cell T-FF9 need be generated. The BWI circuit requires two pulses: (1) the falling edge of CONV2, which disconnects the counter output clock Q_n from a subsequent counter stage; and (2) the falling edge of CONV1, which causes a rising edge in the counter stage output clock, thus inverting the next counter stage.

At least one example embodiment provides a counter circuit using BWI in which the first counter stage is replaced by a latch circuit. At least one other example embodiment provides a first latch circuit for replacing the first counter stage of such a BWI counter circuit.

FIG. 11 illustrates a latch circuit according to an example embodiment. FIGS. 12a and 12b are timing diagrams for explaining example operation of the latch circuit shown in FIG. 11. More specifically, FIG. 12a illustrates a situation in which the latch stage output clock Q₀ is a high state (e.g., a logic ‘1’) after the reset counting phase, whereas FIG. 12b illustrates a situation in which the output Q₀ of the circuit is a low state (e.g., a logic ‘0’) after the reset counting phase. In each of FIGS. 12a and 12b the latch stage output clock Q₀ and the input clock CLK have the same state at the start of the reset counting phase. FIG. 13 illustrates a counter circuit including the latch circuit shown in FIG. 11.

Referring to FIG. 11, the latch circuit includes a first latch L1 coupled to a first input of an exclusive-OR (XOR) logic gate X1. The output of the XOR gate X1 is coupled to a next counter stage and an input of an inverter I1. The output of the inverter I1 is coupled to an input of a second latch L2. The output of the second latch L2 is coupled to a second input of the XOR gate X1.

In the circuit shown in FIG. 11, the inverter I1, the second latch L2 and the XOR gate X1 facilitate bitwise inversion of the LSB, which is carried out between the reset and signal counting phases.

The second latch L2 stores the value of latch stage output clock Q₀, which is the LSB value of the reset signal at the time of the bit-wise inversion operation (e.g., transitions of CONV1 and CONV2). Because the input clock CLK always starts counting at the same level (e.g., CLK=0), and the SET pulse forces the second latch output clock PARITY to ‘1’, there are two possible options:

• • (1) If Q₀=‘0’, the PARITY value is changed to ‘0’, and the XOR gate X1 inverts Q₀ to ‘1’; or
  • (2) If Q₀=‘1’, the PARITY value stays at ‘1’, and setting the output of the latch L1 to ‘0’ inverts Q₀ to ‘0’.

The latch circuit shown in FIG. 11 may be added to accommodate an N-bit counter that implements the DDR input clock and bit-wise inversion, as shown in FIG. 13.

Referring more specifically to FIGS. 11 and 12a, at the start of the reset counting phase, the latch stage output clock Q₀ and the input clock CLK have the same state (e.g., a low state or ‘0’).

At the end of the reset counting phase, the enable signal EN transitions from a high state to a low state (e.g., falling edge of the enable signal EN), which disables the first latch L1 and causes the first latch L1 to store the state (e.g., a high state) of the input clock CLK when the enable signal EN transitioned. In so doing, the first latch L1 continually outputs first latch output clock CLKL1 having a low state (e.g., the opposite state of the input clock CLK at the time the first latch L1 was disabled).

Prior to the signal counting phase and while the first latch L1 is still disabled, the first latch output clock CLK_L1 transitions from the high state to the low state in synchronization with the falling edge of the first bitwise inversion clock CONV1.

The XOR gate X1 generates a first stage output clock Q₀ based on the first latch output clock CLK_L1 and a second latch output clock PARITY from the second latch L2. The second latch output clock PARITY will be discussed in more detail later.

As shown in FIG. 12a, the state of the first stage output clock Q₀ at the end of the reset counting phase is the same as the input clock CLK, but opposite to state of the first latch output clock CLK_L1. Prior to the signal counting phase, the first latch output clock CLK_L1 transitions from the high state to the low state at the rising edge of the second selection signal SEL2. By transitioning from the high state to the low state prior to the signal counting phase, the state of the latch stage output clock Q₀ and the input clock CLK are the same at the beginning of the signal counting phase.

Still referring to FIG. 11, in addition to being output to a first counter stage, the latch stage output clock Q₀ is inverted by inverter I1 and input to the second latch L2.

The second latch L2 generates the second latch output clock PARITY based on the inverted input from the inverter I1. Referring again to FIG. 12a, prior to the reset counting phase, the second latch output clock PARITY transitions from a low state to a high state at a rising edge (e.g., transition from a low to a high state) of the set signal SET input to the second latch L2. The second latch output clock PARITY is input to the XOR gate X1.

The timing diagram shown in FIG. 12b illustrates a similar operation of the circuit shown in FIG. 11. Thus, the differences between the timing diagrams shown in FIGS. 12a and 12b will be discussed herein for the sake of brevity.

As shown in FIG. 12b, the latch stage output clock Q₀ and the input clock CLK have the same state at the start of the reset counting phase. At the end of the reset counting phase, the enable signal EN transitions from a high state to a low state (e.g., falling edge of the enable signal EN), which disables the first latch L1 and causes the first latch L1 to store the state (e.g., a low state) of the input clock CLK when the enable signal EN transitioned from the high state to the low state. In so doing, the first latch L1 continually outputs first latch output clock CLK_L1 having a high state (e.g., the opposite state of the input clock CLK at the time the first latch L1 is disabled).

As shown in FIG. 12b, the state of the latch stage output clock Q₀ at the end of the reset counting phase is the opposite to the input clock CLK, but the same as the state of the first latch output clock CLK_L1 (which is in, e.g., a high state).

Prior to the signal counting phase, the first stage output clock Q₀ transitions from the low state to the high state in synchronization with the falling edge of a second bitwise inversion clock CONV2. By transitioning from the low state to the high state prior to the signal counting phase, the state of the first stage output clock Q₀ and the input clock CLK are opposite at the start of the signal counting phase.

FIG. 13 illustrates an example embodiment of a counter including the latch circuit shown in FIG. 11. The counter shown in FIG. 13 is a DDR counter.

As shown in FIG. 13, a latch stage 1300 replaces a conventional first counter stage as shown, for example, in FIG. 9.

In the example embodiment shown in FIG. 13, the latch stage 1300 includes a latch circuit, which operates as described above with regard to FIGS. 11, 12a and 12b, and outputs the latch stage output clock Q₀ to first counter stage 1301.

The latch stage 1300 is coupled to a plurality of subsequent counter stages 1301, 1302, 1303, . . . , 130(N−1), each of which includes a respective counter cell (e.g., T-flip-flop) T-FF1301, T-FF1302, T-FF1303, . . . , T-FF130(N−1) and respective bit-wise inversion circuit BWI-1301, BWI-1302, BWI-1303, . . . , BWI-130(N−1). The subsequent counter stages 1301, 1302, 1303, . . . , 130(N−1) are connected in series with each other and with the latch stage 1300.

The first bitwise inversion circuit BWI-1301 of the first counter stage 1301 selectively inverts the state of the latch stage output clock Q₀ based on first and second bitwise inversion signals CONV1 and CONV2 in order to perform desired bitwise addition or subtraction. The first bitwise inversion circuit BWI-1301 outputs the selectively inverted latch stage output clock Q₀ to the first counter cell T-FF1301.

The first counter cell T-FF1301 of the first counter stage 1301 generates a first counter stage output clock Q₁ based on the output from the bitwise inversion circuit BWI-1301. In so doing, the first counter cell T-FF1301 toggles the state (e.g., from low to high or high to low) of the first counter stage output clock Q₁ based on a change in the state of the output from the BWI inversion circuit BWI-1301. For example, the first counter cell T-FF1301 toggles the state of the first counter stage output clock Q₁ as the output from the BWI inversion circuit BWI-1301 rises (e.g., in response to a transition from a low state to a high state). The first counter cell T-FF 1301 outputs the first counter stage output clock Q₁ to a second counter stage 1302.

Each of the subsequent counter stages 1302, 1303, . . . , 130(N−1) operates in a manner similar to that described above with regard to first counter stage 1301 to generate a resultant digital output code DOUT, which is stored in a line buffer (for each column separately), and read out by an image signal processor.

FIG. 14 illustrates a first latch stage for a counter circuit according to another example embodiment. The example embodiment shown in FIG. 14 is similar to the example embodiment shown in FIG. 11, except that the circuit shown in FIG. 14 further includes a switch S. The switch S enables the circuit to be implemented in conjunction with an UP/DOWN based FF counter. Because the operation of the circuit shown in FIG. 14 is similar to the operation of the circuit shown in FIG. 11, only a relatively brief discussion of the circuit shown in FIG. 14 and the timing diagrams shown in FIGS. 15a and 15b is provided.

The switch S allows LSB bitwise inversion to occur prior to an UP counting operation carried out by the following counter stages of the counter. In this case, the starting phase of the UP counting (e.g., rising edge of the UP signal) is aligned with the end of the LSB BWI (e.g., rising edge of the latch output selection signal SEL).

FIGS. 15 a and 15b are timing diagrams for describing example operation of the counter circuit shown in FIG. 14.

Referring to FIGS. 14 and 15a, the latch stage output clock Q₀ has the same state as the input clock CLK at the start of the reset counting phase. At the end of the reset counting phase, the enable signal EN transitions from a high state to a low state (e.g., falling edge of the enable signal EN), which disables the first latch L1 and causes the first latch L1 to store the state (e.g., a high state) of the input clock CLK when the enable signal EN transitioned. In so doing, the first latch L1 continually outputs first latch output clock CLK_L1 having a low state (e.g., the opposite state of the input clock CLK at the time the first latch L1 is disabled).

In the example shown in FIG. 15a, the state of the latch stage output clock Q₀ at the end of the reset counting phase is the same as the input clock CLK, but opposite to state of the first latch output clock CLK_L1.

Prior to the signal counting phase, the latch stage output clock Q₀ transitions from the high state to the low state in synchronization with the falling edge of the first bitwise inversion signal CONV1. By transitioning from the high state to the low state prior to the signal counting phase, the state of the latch stage output clock Q₀ and the input clock CLK are the same at the start of the signal counting phase.

As shown in FIG. 15a, the latch output selection signal SEL is enabled prior to the signal counting phase and in synchronization with the enabling (rising edge) of the up counting signal UP.

Turning to FIGS. 14 and 15b, at the end of the reset counting phase, the enable signal EN transitions from a high state to a low state (e.g., falling edge of the enable signal EN), which disables the first latch L1 and causes the first latch L1 to store the state (e.g., a low state) of the input clock CLK when the enable signal EN transitioned. In so doing, the first latch L1 continually outputs first latch output clock CLK_L1 having a high state (e.g., the opposite state of the input clock CLK at the time the first latch L1 is disabled).

In the example shown in FIG. 15b, the state of the first stage output clock Q₀ at the end of the reset counting phase is the same as the input clock CLK, but opposite to state of the first latch output clock CLK_L1.

Prior to the signal counting phase, the latch stage output clock Q₀ transitions from the low state to the high state in synchronization with the falling edge of the second conversion signal CONV2. By transitioning from the low state to the high state prior to the signal counting phase, the states of the first stage output clock Q₀ and the input clock CLK are opposite at the start of the signal counting phase.

In the case shown in FIG. 15b, the remaining portions of the circuit shown in FIG. 14 operate as described above with regard to FIG. 15a.

FIG. 16 illustrates an example embodiment of a counter circuit including the latch circuit shown in FIG. 14. The counter circuit shown in FIG. 16 is an UP/DOWN-based FF DDR counter.

As shown in FIG. 16, the latch stage 1600 replaces a conventional first counter stage as shown, for example, in FIG. 7.

In the example embodiment shown in FIG. 16, the latch stage 1600 includes a latch circuit, which operates as described above with regard to FIGS. 14, 15a and 15b, and outputs the latch stage output clock Q₀ to a subsequent counter stage 1601.

The latch stage 1600 is coupled to a plurality of subsequent counter stages 1601, 1602, 1603, . . . , 160(N−1), each of which includes a respective counter cell (e.g., T-flip-flop) T-FF1601, T-FF1602, T-FF1603, . . . , T-FF160(N−1) and a respective multiplexer MUX1601, MUX1602, MUX1603, . . . , MUX160(N−1). The subsequent counter stages 1601, 1602, 1603, . . . , 160(N−1) are connected in series with each other and with the latch stage 1600.

The first counter cell T-FF 1601 generates a first up counter output clock Q₁ and a first down counter output clock Q₁ based on the latch stage output clock Q₀. In so doing, the first counter cell T-FF1601 toggles the state (e.g., from low to high or high to low) of the first up counter output clock Q₁ and the first down counter output clock Q₁ based on a change in the state of the latch stage output clock Q₀. For example, the first counter cell T-FF1601 toggles the state of the first up counter output clock Q₁ and the first down counter output clock Q₁ as the latch stage output clock Q₀ rises (e.g., in response to a transition from a low state to a high state). The first counter cell T-FF1601 outputs the first up counter output clock Q₁ and the first down counter output clock Q₁ to a first multiplexer MUX1601.

The first multiplexer MUX1601 selectively outputs one of the first up counter output clock Q₁ and the first down counter output clock Q₁ to the second counter stage 1602 as a second counter stage output clock CLK1 based on a count signal UP/DOWN to perform desired addition or subtraction. For example, to perform addition the first multiplexer MUX1601 outputs the first up counter output clock Q₁. To perform subtraction, the first multiplexer MUX1601 outputs the first down counter output clock Q₁.

Each of the subsequent counter stages 1602, 1603, . . . , 160(N−1) operates in a manner similar to that described above with regard to the first counter stage 1601 to generate a resultant digital output code DOUT, which is stored in a line buffer (for each column separately), and read out by an image signal processor.

Example embodiments of counter circuits described herein may be implemented in conjunction with the counters 1044 and 1050 shown in FIGS. 2A and 2B.

At least some example embodiments provide ripple-counter circuits capable of applying digital gain for some or all counting phases allowing for linear output data.

The foregoing description of example embodiments has been provided for purposes of illustration and description. It is not intended to be exhaustive or limiting. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment. Rather, where applicable, individual elements or features are interchangeable and may be used in a selected embodiment, even if not specifically shown or described. The same may also be varied in many ways. All such modifications are intended to be included within the scope of this disclosure.

Claims

1. A counter circuit for an analog to digital converter, the counter circuit comprising: a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of a reset counting phase, but a same or different state at start of a signal counting phase depending on the state of the output clock at the end of the reset counting phase.

2. The counter circuit of claim 1, further comprising: a plurality of counter stages connected in series with the latch stage, each of the plurality of counter stages being configured to toggle a state of an output clock in response to a change in state of the output clock from a preceding stage.

3. The counter circuit of claim 2, wherein each of the plurality of counter stages comprises: a bit-wise inversion circuit configured to selectively perform a bit-wise inversion operation on the output clock from a previous counter stage in response to at least one bit-wise inversion signal, and to output an inverted state of the output clock from a previous counter stage; anda counter cell configured to toggle a state of an output clock in response to a change in state of the output from the bit-wise inversion circuit.

4. The counter circuit of claim 1, wherein the latch stage further comprises: a first latch configured to output a first latch output clock based on the input clock;a logic gate configured to generate the latch stage output clock by performing a logic operation on first latch output clock and a second latch output clock; anda second latch configured to output the second latch output clock based on the latch stage output clock.

5. The counter circuit of claim 4, wherein the latch stage further comprises: an inverter configured to invert a state of the latch stage output clock and output the inverted state of the latch stage output clock to the second latch; wherein the second latch is configured to output the second latch output clock based on the inverted state of the latch stage output clock.

6. The counter circuit of claim 1, further comprising: a plurality of counter stages connected in series with the latch stage, each of the plurality of counter stages being configured to output one of an up counting output clock and a down counting output clock in response to an output clock from a preceding counter stage, the up counting output and the down counting output clock having opposite states.

7. The counter circuit of claim 6, further comprising: a selection circuit configured to separate the latch stage from the plurality of counter stages in response to a latch output selection signal.

8. The counter circuit of claim 6, wherein each of the plurality of counter stages comprises: a counter cell configured to output the up counting output clock and the down counting output clock in response to the output clock from a preceding counter stage; anda multiplexer configured to selectively output one of the up counting output clock and the down counting output clock to a subsequent counter stage in response to a count signal.

9. An analog to digital converter comprising: a comparator circuit configured to generate a comparison signal corresponding to each column of a pixel array, each comparison signal being generated based on a comparison between an input signal corresponding to a column of the pixel array and a ramp signal;a counter bank configured to convert each of the generated comparison signals into a digital output signal, the counter bank including at least one counter circuit of claim 1; anda line memory configured to store the digital outputs from the counter bank.

10. The analog to digital converter of claim 9, wherein the counter circuit further comprises: a plurality of counter stages connected in series with the latch stage, each of the plurality of counter stages being configured to toggle a state of an output clock in response to a change in state of the output clock from a preceding stage.

11. The analog to digital converter of claim 10, wherein each of the plurality of counter stages comprises: a bit-wise inversion circuit configured to selectively perform a bit-wise inversion operation on the output clock from a previous counter stage in response to at least one bit-wise inversion signal, and to output an inverted state of the output clock from a previous counter stage; anda counter cell configured to toggle a state of an output clock in response to a change in state of the output from the bit-wise inversion circuit.

12. The analog to digital converter of claim 9, wherein the latch stage comprises: a first latch configured to output a first latch output clock based on the input clock;a logic gate configured to generate the latch stage output clock by performing a logic operation on first latch output clock and a second latch output clock; anda second latch configured to output the second latch output clock based on the latch stage output clock.

13. The analog to digital converter of claim 12, wherein the latch stage further comprises: an inverter configured to invert a state of the latch stage output clock and output the inverted state of the latch stage output clock to the second latch; wherein the second latch is configured to output the second latch output clock based on the inverted state of the latch stage output clock.

14. The analog to digital converter of claim 9, wherein the counter circuit comprises: a plurality of counter stages connected in series with the latch stage, each of the plurality of counter stages being configured to output one of an up counting output clock and a down counting output clock in response to an output clock from a preceding counter stage, the up counting output and the down counting output clock having opposite states.

15. The analog to digital converter of claim 14, wherein the latch stage comprises: a selection circuit configured to separate the latch stage from a plurality of counter stages in response to a latch output selection signal.

16. The analog to digital converter of claim 14, wherein each of the plurality of counter stages comprises: a counter cell configured to output the up counting output clock and the down counting output clock in response to an output clock from a preceding counter stage; anda multiplexer configured to selectively output one of the up counting output clock and the down counting output clock to a subsequent counter stage in response to a count signal.

17. The analog to digital converter of claim 9, wherein the counter bank further comprises: a plurality of counter circuits, each of the plurality of counter circuits corresponding to a column of the pixel array; wherein each of the plurality of counter circuits includes a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of the reset counting phase, but a same or different state at start of the signal counting phase depending on the state of the output clock at the end of the reset counting phase.

18. An image sensor comprising: an active pixel array including a plurality of pixels arranged in an array;a line driver configured to select rows of pixels for output by the active pixel array; andthe analog to digital converter of claim 9 configured to convert outputs from the active pixels into digital output code.

19. The image sensor of claim 18, wherein the counter circuit further comprises: a plurality of counter stages connected in series with the latch stage, each of the plurality of counter stages being configured to toggle a state of an output clock in response to a change in state of the output clock from a preceding stage.

20. The image sensor of claim 19, wherein each of the plurality of counter stages comprises: a bit-wise inversion circuit configured to selectively perform a bit-wise inversion operation on the output clock from a previous counter stage in response to at least one bit-wise inversion signal, and to output an inverted state of the output clock from a previous counter stage; anda counter cell configured to toggle a state of an output clock in response to a change in state of the output from the bit-wise inversion circuit.

21. The image sensor of claim 18, wherein the latch stage comprises: a first latch configured to output a first latch output clock based on the input clock;a logic gate configured to generate the latch stage output clock by performing a logic operation on first latch output clock and a second latch output clock; anda second latch configured to output the second latch output clock based on the latch stage output clock.

22. The image sensor of claim 21, wherein the latch stage further comprises: an inverter configured to invert a state of the latch stage output clock and output the inverted state of the latch stage output clock to the second latch; wherein the second latch is configured to output the second latch output clock based on the inverted state of the latch stage output clock.

23. The image sensor of claim 18, wherein the counter circuit further comprises: a plurality of counter stages connected in series with the latch stage, each of the plurality of counter stages being configured to output one of an up counting output clock and a down counting output clock in response to an output clock from a preceding counter stage, the up counting output and the down counting output clock having opposite states.

24. The image sensor of claim 23, wherein the latch stage comprises: a selection circuit configured to separate the latch stage from a plurality of counter stages in response to a latch output selection signal.

25. The image sensor of claim 23, wherein each of the plurality of counter stages comprises: a counter cell configured to output the up counting output clock and the down counting output clock in response to an output clock from a preceding counter stage; anda multiplexer configured to selectively output one of the up counting output clock and the down counting output clock to a subsequent counter stage in response to a count signal.

26. The image sensor of claim 18, wherein the counter bank further comprises: a plurality of counter circuits, each of the plurality of counter circuits corresponding to a column of the pixel array; wherein each of the plurality of counter circuits includes a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of the reset counting phase, but a same or different state at start of the signal counting phase depending on the state of the output clock at the end of the reset counting phase.

27. A digital imaging system comprising: a processor configured to process captured image data; andthe image sensor of claim 18 configured to capture image data by converting optical images into electrical signals.

28. The digital imaging system of claim 27, wherein the counter circuit further comprises: a plurality of counter stages connected in series with the latch stage, each of the plurality of counter stages being configured to toggle a state of an output clock in response to a change in state of the output clock from a preceding stage.

29. The digital imaging system of claim 28, wherein each of the plurality of counter stages comprises: a bit-wise inversion circuit configured to selectively perform a bit-wise inversion operation on the output clock from a previous counter stage in response to at least one bit-wise inversion signal, and to output an inverted state of the output clock from a previous counter stage; anda counter cell configured to toggle a state of an output clock in response to a change in state of the output from the bit-wise inversion circuit.

30. The image sensor of claim 27, wherein the latch stage comprises: a first latch configured to output a first latch output clock based on the input clock;a logic gate configured to generate the latch stage output clock by performing a logic operation on first latch output clock and a second latch output clock; anda second latch configured to output the second latch output clock based on the latch stage output clock.

31. The digital imaging system of claim 30, wherein the latch stage further comprises: an inverter configured to invert a state of the latch stage output clock and output the inverted state of the latch stage output clock to the second latch; wherein the second latch is configured to output the second latch output clock based on the inverted state of the latch stage output clock.

32. The digital imaging system of claim 27, wherein the counter circuit comprises: a plurality of counter stages connected in series with the latch stage, each of the plurality of counter stages being configured to output one of an up counting output clock and a down counting output clock in response to an output clock from a preceding counter stage, the up counting output and the down counting output clock having opposite states.

33. The digital imaging system of claim 32, wherein the latch stage comprises: a selection circuit configured to separate the latch stage from a plurality of counter stages in response to a latch output selection signal.

34. The digital imaging system of claim 32, wherein each of the plurality of counter stages comprises: a counter cell configured to output the up counting output clock and the down counting output clock in response to an output clock from a preceding counter stage; anda multiplexer configured to selectively output one of the up counting output clock and the down counting output clock to a subsequent counter stage in response to a count signal.

35. The digital imaging system of claim 27, wherein the counter bank further comprises: a plurality of counter circuits, each of the plurality of counter circuits corresponding to a column of the pixel array; wherein each of the plurality of counter circuits includes a latch stage configured to generate a latch stage output clock based on a state of an input clock such that the latch stage output clock and the input clock have a same state at start of the reset counting phase, but a same or different state at start of the signal counting phase depending on the state of the output clock at the end of the reset counting phase.