Decode circuitry for bipolar random access memory

Abstract

An N-bit binary address decoder suitable for use in an emitter-coupled logic bipolar random access memory (RAM) is provided. Each of the N address input signals is applied to an input terminal and is level shifted and applied to the input node of an emitter-coupled logic inverter. The outputs of the emitter-coupled logic inverter are the collectors of the emitter-coupled transistors on which complementary output signals representative of the corresponding binary address input signal are produced. The complementary output signals generated by the N inverters are connected to 2.sup.N AND gates to form the possible 2.sup.N minterm combinations. Each of the AND gates includes a load resistor coupled to a power supply and N Schottky diodes having their anodes coupled to the load resistor and their cathodes coupled to the corresponding address inverter output terminals. The anodes of the input diodes of each AND gate are also connected to the base of a transistor, the emitter of which produces the signal representing the corresponding minterm function generated by that AND gate.

Description

BACKGROUND OF THE INVENTION

Previous decoding circuits for emitter-coupled logic (ECL) memory required two "levels" of standard ECL gating to form the OR/NOR implementation of the address minterms. (A minterm of N variables is a Boolean product of these N variables, with each variable present in either its true or its complemented form.) In the logic circuitry previously used to decode the binary address inputs to an ECL memory, the address inputs are applied directly to ECL inverter circuits having load resistors connected between the collectors of the emitter-coupled transistors and the positive power supply conductor. This causes one stage of the delay of the decoding circuit. The differential collector outputs are coupled to the bases of emitter follower output transistors having multiple emitters. The multiple emitters from each address inverter are then emitter OR'ed (i.e., connected together) with the output emitters of the emitter followers of the other address inverters to provide the possible maxterms. (A number of N variables is a Boolean sum of these N variables, where each variable is present in either its true or its complemented form.) The maxterm nodes thus formed are than coupled to, respectively, 2.sup.N emitter coupled logic inverters to provide the 2.sup.N minterm functions, which provide the decoded outputs. Here N is the number of address inverters in the group. Because of circuit constraints and topological constraints, which reduce circuit speed, the maximum size of the maxterm groups is usually limited to three address input variables. The outputs of the "OR'ed" combination groups are provided as inputs to multiple input NOR gates, and the output is used to drive the selected memory row or column.

SUMMARY OF THE INVENTION

It is an object of this invention to provide a circuit which provides a high speed AND function and a circuit which provides a high speed OR function.

Another object of the invention is to provide a decode circuit function requiring only one gate delay.

It is another object of the invention to provide a high speed decode system for an emitter-coupled logic random access memory.

It is another object of the invention to provide a high speed emitter-coupled logic decode gate requiring a reduced number of components and a dissipating reduced amount of power.

It is another object of the invention to provide a decode circuit by coupling an output of an emmitter-coupled logic current switch to an input of a diode logic AND gate.

Briefly described, the invention provides an N-input high speed emitter-coupled logic decoder for selecting one out of 2.sup.N combinations of N variables which include N emitter-coupled logic inverters each including first and second emitter-coupled transistors and a current source connected to the coupled emitters. Complementary output signals are provided, respectively, at the collectors of the first and second transistors. The decoder also includes 2.sup.N N-input diode AND gates, each having an emitter follower output transistor connected thereto. The N complementary outputs of the N emitter-coupled logic inverters are connected to the various cathodes of the diodes to form the 2.sup.N possible minterm combinations. The emitter follower outputs may then be used to drive row selection circuitry of column selection circuitry of an ECL random access memory array.

BRIEF DESCRIPTION OF THE DRAWING

FIG. 1 is a schematic diagram of an N-bit decoder circuit according to the invention.

FIG. 2 is a block diagram of a memory circuit utilizing the N-bit decoder circuit of FIG. 1.

DESCRIPTION OF THE INVENTION

FIG. 1 is a schematic diagram of a decoder circuit suitable for selecting rows or columns of an array of random access memory (RAM) storage cells. Referring to the Figure, decoder 10 includes N-input buffer circuits including circuits 12, 16 and 20, each of which are emitter followers. Each of the emitter followers has its output coupled to the input of an emitter-coupled logic (ECL) inverter circuits. ECL inverter circuit 14, has its input connected to the output of emitter follower 12, inverter circuit 18 has its input connected to the output of emitter follower 16, and inverter 22 has its input connected to the output of emitter follower 20.

Each of the inverters 14, 18 and 22 produce complementary output signals at the collectors of their emitter-coupled transistors. Decoder 10 also includes N AND gates including AND gates 24, 26 and 28, each of which has N-input diodes having their anodes connected together and coupled to one terminal of a load resistor, the opposite terminal of which is coupled to a V.sub.CC supply voltage conductor 65. AND gates 24, 26 and 28 include, respectively, output driver transistors 62, 63 and 65, the emitters of which each provide one of 2.sup.N combinations of the N-input variables A.sub.O, A.sub.1 . . . A.sub.N.

The structure of one of the input buffers, one of the address inverters, and one of the AND gates will now be described in detail. The structures of the remaining gates, buffers and inverters, are entirely similar.

Emitter follower 12 includes transistor 32 which has its collector connected to V.sub.CC conductor 65, its base connected to address input conductor 30 and its emitter connected to current source 34. Address inverter 14 includes transistors 36 and 38 having their emitters coupled together to current source 37. Transistor 36 has its base connected to the emitter of emitter follower transistor 32 and its collector connected to A.sub.1 conductor 44. Transistor 38 has its base connected to reference voltage conductor 40 and its collector connected to A.sub.1 conducter 42. Similarly, the collectors of the emitter-coupled transistors of address inverter 18 are connected to A.sub.2 conductor 48 and A.sub.2 conductor 46. The collectors of te emitter-coupled transistors of address inverter 22 are, respectively, coupled to A.sub.N conductor 52 and A.sub.N conductor 50.

AND gate 24 includes Schottky diodes 54, 56 and 58 having their anodes connected together to one terminal of load resistor 60, the other terminal of which is connected to V.sub.CC conductor 65. The anodes of Schottky diodes 54, 56 and 58 are connected to the base of emitter follower output transistor 62, which has its collectors connected to V.sub.CC conductor 65 and its emitter connected to output conductor 66. (The emitter load circuit coupled to the emitter follower transistor is not shown.) Diode 54 has its cathode connected to A.sub.1 conductor 44, diode 56 has its cathode connected to A.sub.2 conductor 48, and diode 58 has its cathode connected to A .sub.N conductor 52. Hence, the voltage on output conductor 66 represents the minterm combination A.sub.1, A.sub.2 . . . A.sub.N. Similarly, the cathodes of the input diodes of the other AND gates are connected to the various other possible combinations of the address and address complement conductors.

The operation of the circuit depicted in the Figure may be described by considering the operation for the case wherein all of the address input signals A.sub.1, A.sub.2 . . . A.sub.N are at a logical O level, i.e., at a relatively low voltage level. It is assumed for this discussion that V.sub.CC is at ground potential, V.sub.EE is at -5.2 volts, a logical O is -1.6 volts, a logical 1 is -0.8 volts, and V.sub.REF (the reference voltage) is at -1.2 volts. Then, for each of the emitter followers 12, 16, and 20, the output voltage will be approximately -2.4 volts, causing Q.sub.1 of the corresponding address inverter to be off. The current I.sub.G for each of the address inverters will thus be flowing through Q.sub.2. Thus, part of the current I.sub.G of inverter 14 will flow through diode D.sub.1 of diode AND gate 26, tending to turn transistor 63 off. (The current I.sub.G of inverter 14 splits among all diodes D.sub.1, some of which are not shown, connected to A.sub.1 conductor 44). Part of I.sub.G of inverter 18 will flow through diode D.sub.2 of diode AND gate 28, thereby tending to turn transistor 65 off. Diode AND gates 26 and 28 are thereby unselected. However, no current (except negligible leakage currents) flow through diodes D.sub.1, D.sub.2 . . . D.sub.N of diode AND gate 24. Therefore, all of the current through resistor 60 flows into the base of transistor 62 causing diode AND gate 24 to be selected, the voltage on the emitter of output transistor 62 representing the minterm combination A.sub.1, A.sub.2 . . . A.sub.N. Other combinations of the input variables A.sub.1, A.sub.2 . . . A.sub.N each result in the selection of one and only one of the other diode AND gates.

The speed of operation of the above-described decode circuit is extremely fast, and is approximately equivalent to one average ECL gate delay, since the diode AND gate essentially functions as the load circuitry for the emitter-coupled transistors Q.sub.1 and Q.sub.2 of the ECL inverters. Thus, the inventive logic circuitry provides one less gate delay than the previously described prior art decoding circuitry. Further, it has been found that the topology of the interconnecting schemes involving the A.sub.1, A.sub.1, A .sub.2, etc. conductors is much more efficient than the interconnection scheme for emitter OR'ing as previously described for the prior art systems. Further, the power dissipation for the present decoder is far less than the prior scheme, since the current which flows through the unselected AND gates also flows through the ECL inverters; in the prior art scheme, the emitter OR'ed conductors representing the various maxterms were limited to approximately three input variables, and a current dissipating inverter and emitter follower had to be provided for each group of three input variables, further increasing power dissipation.

Although any kind of diodes may be used in diode AND gates, use of Schottky diodes is advantageous because of the high speed, high yield, and high density of Schottky diodes.

FIG. 2 shows a block diagram including a memory system which utilizes the decode circuit of FIG. 1. In FIG. 2, memory 100 includes an array of N rows and M columns of bipolar memory cells such as 110, 120 and 130. Such bipolar memory cells are well known in the art. For example, see U.S. Pat. No. 3,538,348 by Hillis et al. Also see FIG. 2 of U.S. Pat. No. 3,919,566 by the inventors of the present application and filed on the same date as the parent application of the present application. Each column of storage cells is coupled to one or more bit sense lines, such as 108, or 109, which in turn are coupled to column selection and input output circuitry such as 104 and 105. The column selection function performed by circuitry 104 and 105 is controlled by column decoder circuitry 10", which is substantially similar to the decode circuitry of FIG. 1. Each row of storage cells is coupled to a selection conductor such as 106 or 107, which in turn is coupled, respectively, to a row selection circuit, such as 102 or 103. Selection circuits 102 and 103 may, for example, consist of transistors 54 and 60 in FIG. 2 of Pat. No. 3,919,566 mentioned above. The inputs of row selection circuits 102 and 103 are connected to outputs of decoder circuit 10', which again, is substantially similar to the decoder circuit described with reference to FIG. 1.

In summary, the invention provides circuitry which allows easy implementation of large binary address decoders using ECL compatible circuitry. ECL gates coupled with a Schottky diode and decoder results in a very fast decode function which reduces the circuit delay of the entire coding function to that of a single gate. The replacement of many transistors required by the prior art approach and the use of topologically dense Schottky diodes results in a higher circuit yield and reduced die area. The concept of the present invention will find application for binary address decoding in many large bipolar memories and in high speed implementations of the AND and OR functions in ECL random logic circuits.

While the invention has been described with reference to a particular embodiment thereof, those skilled in the art will recognize that variations in arrangement and placement of components may be made to suit various requirements within the scope of the invention.

Claims

1. In an array of binary storage cells arranged as 2.sup.N rows selectable by means of signals applied to N row address inputs and 2.sup.M columns selectable by signals applied to M column address inputs, M and N being integers, row decode means comprising:

N inverter means, each including a first transistor having its base coupled to a respective one of said row address inputs, and a second transistor having its base connected to a reference voltage conductor, and its emitter connected to the emitter of said first transistor and to a current source, for generating signals representative of the logical complements of said row address input signals at the collectors of said respective first transistors and for generating signals representative of said respective row address input signals at the collectors of said respective second transistors;

2.sup.N gate means coupled to said N inverter means for selecting a different one of said 2.sup.N rows, each of said 2.sup.N gate means including

a. N diodes, each having its anode connected to the anodes of the other of said diodes and to the base of an output transistor and to a load resistor, each of said output resistors having its emitter coupled to a respective one of said rows;

b. each of said diodes having its cathode coupled to one and only one of said collectors, so that signals produced at the bases of each of said output transistors represent, respectively, the 2.sup.N combinations of said N row address signals.