Claims
- 1. A decoder circuit used in a semiconductor memory device, comprising:
- first and second voltage terminals;
- a NOR gate circuit comprising:
- a common output node;
- a plurality of first transistors of a first channel conductivity type connected in parallel between said first voltage terminal and said common output node for receiving address signals, and effecting an inverting logic operation, respectively; and
- a second transistor of a second channel conductivity type, connected between said second voltage terminal and said common node, for positively feeding back a signal produced on said common output node;
- an inverter circuit, having an input node connected to said common output node and having an output node operatively connected to said second transistor, for producing an inverted signal of said signal on said common output node at said output node;
- a third transistor, operatively connected between said second voltage terminal and said common output node, for conductively connecting the second voltage terminal to the common output node for a predetermined period in response to the changing of the address signals; and
- an output circuit comprising fourth and fifth transistors of the first channel conductivity type connected in series between said first and second voltage terminals, said fourth transistor having a gate connected to said common output node, said fifth transistor having a gate connected to the output node of said inverter circuit, and said second transistor pulling up the voltage at said common output node by which said fourth transistor is driven when all of said first transistors turn off.
- 2. A decoder circuit as claimed in claim 1, wherein said second transistor is of a P-channel MOS type and said first transistors are of an N-channel MOS type.
- 3. A decoder circuit, comprising:
- a NOR gate comprising gate transistors operatively connected to effect an inverting logic operation, operatively connectable to receive address signals and commonly connected to a common node;
- a load transistor operatively connected to the common node;
- transistory signal generation means, operatively connected to the common node, for generating a transitory signal on the common node when at least one of the address signals change;
- feedback means, operatively connected to said load transistor and the common node, for feeding back and latching the transitory signal, through said load transistor as a selection signal on the common node and outputting an inverted selection signal, said load transistor and said feedback means enhancing a leading edge of the selection signal; and
- an output circuit, connected to said common node and said feedback means, for producing an output signal from the signal on the common node and the inverted selection signal, said output circuit comprising first and second output transistors connected in series, said first output transistor having a gate connected to said common node, and said second output transistor having a gate connected to receive the inverted selection signal, said load transistor pulling up the voltage at said common node by which said first output transistor is driven when all said gate transistors turn off.
- 4. A decoder circuit as claimed in claim 3, wherein said feedback means comprises an inverter circuit connected to the common node and said load transistor.
- 5. A decoder circuit as claimed in claim 3, wherein said transitory signal generation means comprises:
- a clock pulse controlled transistor operatively connected to the common node; and
- clock pulse generation means, operatively connected to said clock pulse controlled transistor and connectable to receive the address signals, for generating a transitory control signal turning on said clock pulse controlled transistor when at least one of the address signals change.
- 6. A decoder as claimed in claim 5, wherein said clock pulse generation means comprises:
- an OR gate operatively connected to said clock pulse controlled transistor; and
- clock pulse generator circuits operatively connected to said OR gate and each operatively connectable to receive one of the address signals.
Priority Claims (1)
Number |
Date |
Country |
Kind |
57-226607 |
Dec 1982 |
JPX |
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Parent Case Info
This is a continuation of co-pending application Ser. No. 560,173 filed on Dec. 12, 1983 now abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (1)
Number |
Date |
Country |
113481 |
Jul 1982 |
JPX |
Non-Patent Literature Citations (1)
Entry |
Pashley et al., "A 16K.times.1b Static RAM"; Session 1X: Static RAMs; IEEE-ISSCC'79, 2/15/1979; Digest of Tech. Papers. |
Continuations (1)
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Number |
Date |
Country |
Parent |
560173 |
Dec 1983 |
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