BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a schematic of a delay analyzing apparatus according to an embodiment of the present invention;
FIG. 2 is a schematic of a circuit element library;
FIG. 3A is a circuit diagram of an analysis target circuit according to the embodiment;
FIG. 3B is a schematic of critical paths;
FIG. 4 is a schematic of a timing list;
FIG. 5 is a block diagram of a delay analyzing apparatus 500 according to the embodiment;
FIG. 6 is a schematic of a probability density distribution of the delay;
FIG. 7 is a graph of an average delay value with respect to the number of path;
FIG. 8 is a schematic of a partial circuit according to the embodiment;
FIG. 9 is a schematic for explaining a probability density distribution and an accumulated probability distribution of the delay;
FIG. 10 is a chart of the probability density distribution calculated from the average delay distribution shown in FIG. 7;
FIG. 11 is a schematic of an option added to an execution command of a timing analysis;
FIG. 12 is a flowchart of a delay analyzing process by the delay analyzing apparatus 500;
FIG. 13 is a flowchart of a critical path detecting process;
FIG. 14 is a flowchart of a probability density distribution calculating process for the critical paths;
FIG. 15 is a flowchart of a partial circuit creating process; and
FIG. 16 is a flowchart of a probability density distribution calculating process for the entire circuit.