Patent Application
20080309391
The present invention relates to a delay circuit and related method thereof, and particularly relates to a delay circuit utilizing a mapping table to select proper number of delay stages, and related method thereof.
One example of the above-mentioned defects is that the delay circuit will be non-monotonic. Such disadvantages are especially apparent for a high resolution delay circuit. In this situation, chose more delay stages but may provide a less delay amounts, therefore a serious mismatching problem will occur.
One embodiment of the present invention discloses a delay circuit, which comprises: a map delay module and a delay mapping unit. The map delay module is used for delaying an input data signal to generate an output data signal according to a mapped delay selection signal. The delay mapping unit is coupled to the map delay module and used for generating the mapped delay selection signal according to an input selection signal and at least a mapping value.
A signal delay method corresponding to this delay circuit is also disclosed, which comprises: mapping an input selection signal to select at least one delay stage of a delay circuit according to at least a mapping value.
According to the above-mentioned circuit and method, a desired delay amount can be obtained. Also, a monotonic delay circuit can be obtained accordingly. Preferably, the steps of generating the mapping table and selecting a desired number of delay stages can be performed by the same circuit.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
a illustrates a block diagram of a delay circuit according to an embodiment of the present invention.
b is a flow chart illustrating the operations of the delay circuit 200 in the first mode.
c is a flow chart illustrating the operations of the delay circuit 200 in the second mode.
Certain terms are used throughout the description and following claims to refer to particular components. As one skilled in the art will appreciate, electronic equipment manufacturers may refer to a component by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms “include” and “comprise” are used in an open-ended fashion, and thus should be interpreted to mean “include, but not limited to . . . ”. Also, the term “couple” is intended to mean either an indirect or direct electrical connection. Accordingly, if one device is coupled to another device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.
a illustrates a block diagram of a delay circuit 200 according to an embodiment of the present invention that used to generate a mapping table and select a proper number of delay stages according to the mapping table. The delay circuit 200 comprises: a delay measurement unit 201, a storage device 203, a delay mapping unit 205, and a map delay module 207. The delay measurement unit 201 is utilized for generating a mapping table MT, a map enable signal MES, a ring enable signal RES, and a delay selection signal DS according to a reference signal RS and a reference clock signal RCLK. The storage device 203 (for example, a register or a memory), which is coupled to the delay measurement unit 201, is used for storing the mapping table MT from the delay measurement unit 201. The delay mapping unit 205, which is coupled to the storage device 203 and the delay measurement unit 201, is controlled by the map enable signal MES for generating a mapped selection signal MDS according to the delay selection signal DS in a first mode (mapping table generating mode) and according to an input selection signal IDS and a mapping value of the mapping table in a second mode (normal mode). The map delay module 207, which is coupled to the delay measurement unit 201 and the delay mapping unit 205, is controlled by the ring enable signal RES for generating the reference signal RS corresponding to the mapped selection signal MDS in the first mode and for delaying an input data signal Datain to generate an output data signal Dataout corresponding to the mapped selection signal MDS in the second mode.
Briefly, the operation of the delay circuit 200 can be summarized as a method comprising two steps: The first step generates a mapping table according to a reference signal RS from a delay circuit in a first mode. The second step maps an input selection signal IDS to select a proper number of delay stages of the map delay module 207 according to a mapping value of the mapping table MT in the second mode.
b is a flow chart illustrating the operations of the delay circuit 200 in the first mode (mapping table generating mode). The steps comprise:
The map enable signal MES controls the delay mapping unit 205 to generate a mapped selection signal MDS according to the delay selecting signal DS.
In other mode, the input delay selection signal IDS is transformed to the mapped selection signal MDS according to a mapping table MT stored in the storage device 203. Therefore the number of stages selected by the mapped selection signal MDS and the input delay selection signal IDS may be different in other mode. However, in this mode, the number of delay stages selected by the mapped selection signal MDS equals to the number of the delay selection signal DS.
The ring enable signal RES controls the map delay module 207 to generate the reference signal RS corresponding to the delay stage N selected by the mapped selection signal MDS.
The reference signal RS, which is a periodical signal in this embodiment, can indicate the real delay amount of each delay stage of the map delay module 207. The detail structure of the map delay module 207 and how the reference signal RS is generated will be described as below.
Obtain the real delay amount of the delay stage selected by the delay stage N selected by the mapped selection signal MDS according to the reference signal RS and the reference clock signal RCLK.
Determine if the delay stage N selected by the mapped selection signal MDS is a final delay stage of the delay circuit. If yes, go to step 2009, if not, N=N+1, and return to step 2003.
The delay mapping unit 201 generates the mapping table MT according to the real delay amounts of all delay stages.
In one embodiment, the mapping table MT is generated according to which number of the delay stages has real delay amount having minimum difference from the delay amount of the original selected delay stage. For example, if the input delay selection signal IDS selects 3 delay stages having a delay amount of 1 us, and the real delay amount of 3 delay stages is 0.6 us, the real delay amount of 5 delay stages is 1.1 us. Than the mapping table will map 3 delay stages to 5 delay stages, that is, mapped selection signal MDS will select 5 delay stages instead of 3 stages. It should be noted that, such mechanism is only for example and does not mean to limit the scope of the present invention. Other mechanism based on this concept should also fall in the scope of the present invention. Also, the mapping table MT is generated according to all delay stages of the delay circuit in one embodiment, but the mapping table can be generated according to only part of the delay stages.
The mapping table MT not only can be generated to indicate the real delay amount of the map delay module 207, but also can be generated to meet different requirements. For example, a delay circuit in the map delay module 207 can be a monotonic delay chain according to the mapping table. Also, the mapping table can make the delay stages of the delay circuit in the map delay module 207 have a minimum delay amount difference with each other. The detail description of theses examples will be shown in the following.
In the first mode, the control signal MES controls the delay mapping unit 205 to enable the delay selection signal DS to be sent for selecting the number of delay stages of the map delay module 207, such that the map delay module 207 can generate a reference signal RS (a periodical signal in this embodiment, but this is not a limitation of the present invention) corresponding to the selected number of delay stages. The reference signal RS can indicate the real delay of the selected number of delay stages. Then the delay measurement unit 201 generates a mapping table MT according to the reference signal RS.
c is a flow chart illustrating the operations of the delay circuit 200 in the second mode (normal mode). The steps comprise:
The map enable signal MES controls the delay mapping unit 205 to generate the mapped selection signal MDS according to an input selection signal IDS and a mapping value from the mapping table MT stored in the storage device 203.
In this mode, the mapped selection signal MDS is according to the input delay selection signal IDS instead of the delay selection signal DS, and the number of stages selected by the mapped selection signal MDS and the input delay selection signal IDS may be different.
Select delay stages of the map delay module 207 according to the mapped selection signal MDS.
The ring enable signal RES controls the map delay module 207 to delay an input data signal Datain to generate an output data signal Dataout according to the delay stages selected by the mapped selection signal MDS, instead of generating the reference signal RS.
In the second mode, the delay mapping unit 205 maps the input selection signal IDS to a mapped selection signal MDS according to a mapping value of the mapping table MT to select a proper number of delay stages, such that a desired delay amount or a desired delay circuit type can be provided. For example, if the number of the original delay stages selected by the input selection signal IDS is 2, and the mapped delay stage number corresponding to the original delay stage number selected by the mapped selection signal MDS is 3, then the mapping value is 3.
It should be noted that the present invention is not limited to have all the devices disclosed in
Furthermore, the delay circuit 200 is not limited to be applied to a single delay mapping unit.
It should be noted that, although the map delay module 207 further includes an inverter 505 to match the structure of the delay chain 501 for generating the reference signal RS, the inverter 505 can be omitted if the structure of the delay circuit is different.
The periodical counter is reset to a negative value near 0, and the reference counter is set to 0. Then, a selected number of delay stages is selected by the delay selection signal DS, and the mapped delay circuit 207 outputs the periodical signal (the reference signal RS) corresponding to the selected delay stages to the periodical counter 603, such that the periodical counter 603 will count up. The enable signal generator controls the enable signal ES to be 1 for enabling the reference counter 607 to count up when the periodical counter value reaches 0. The enable signal ES is set to 0 to stop the reference counter 607 and the control signal RES is set to 0 when the periodical counter 603 reaches a specific value. After a period of time, the control unit 601 resets the periodical counter 603 to a negative value near 0, sets the delay selection signal DS as 0 (that is, makes the mapped delay circuit provide a periodical signal with no delay amount), and sets the ring enable signal RES to 1. Then the same operation as described above is performed, but this time the reference counter 607 counts down.
In this way, the counter difference value CD between the periodical signal corresponding to the selected number of delay stages and the periodical signal corresponding to no delay stage is obtained. If the period of the reference clock signal is tr, the ideal CD is 2 td/tr. By repeating the above-mentioned operation, all counter difference values CD between the periodical signals corresponding to all the delay stages and the periodical signal corresponding to no delay stage can be obtained. After that, the control unit 601 can generate a mapping table MT according to the counter difference values DC. It should be noted that, although the counter difference values DC indicate the relations between the delay stages in this embodiment, the delay amount of the delay stages can also be obtained according to the counter difference values DC if the delay amount of delay stages is known.
It should be noted that the devices and the operation shown in
As part or all of the counter difference values CD are obtained, a mapping table MT can be determined according to desired results. Table 1 is an example of a table illustrating the relation between ideal CDs and actual CDs.
The order of ideal CDs makes the delay circuit a monotonic delay circuit, but the order of actual CDs does not. Therefore, if the delay circuit is desired to be a monotonic delay circuit, a mapping table shown in Table 2 will be obtained. Although the input selection signal IDS selects 2 delay stages, the mapping value is 3. Similarly, although the input selection signal IDS selects 3 delay stages, the mapping value is 2. In this way, each number of the selected delay stages will have a delay amount having a minimum error from the ideal delay amount. Also, the delay circuit after mapping is a monotonic delay circuit in the embodiment shown in Table 2.
Additionally, if the design of the circuit cannot allow all the counter difference values CD to be recorded, each number of selected delay stages is desired to have a delay amount having a minimum error from the ideal delay amount. Other kinds of mapping table different from the mapping table shown in Table 2 can be generated. For example, only delay stages with a larger actual CD than ideal CD can be selected as the delay stage for mapping. Table 3 illustrates such a kind of mapping table, which references the relation shown in Table 1. In this case, although the error between the ideal CD and the actual CD is 32, the delay circuit will still be a monotonic delay circuit, and the space for recording the counter difference values can be decreased.
If the delay chain is a high resolution delay chain, the storage device can only contain a simplified mapping table instead of a mapping table corresponding to all delay stages to save the storage space. Table 4 illustrates relations between ideal CDs and actual CDs for a high resolution delay chain. The delay chain includes 16 delay stages, but the number of the ideal CDs is only 4. Therefore, the actual CD of 1 delay stage is compared with the first ideal CD 20, the actual CD of 2 delay stages is compared with the first ideal CD 40 etc. A mapping table can then be generated accordingly.
Table 5 is a mapping table example for a high resolution delay chain corresponding to Table 4. In this case, an original delay stage is mapped to a closest delay stage having an actual CD larger than the ideal counter difference of the original delay stage. The delay circuit is a monotonic delay circuit according to the mapping table shown in Table 5. In this case, the input selection signal IDS is multiplied by a predetermined parameter n (4 in this embodiment) to generate the mapped selection signal MDS for selecting mapped delay stages.
Such mapped delay circuit will have larger errors for delay amount, however. Therefore, in order to decrease the difference between the original delay stages and mapped delay stages, the delay chain 1200 can comprise a main delay chain 1201 for providing a main delay amount according to the input selection signal IDS, and an offset delay chain to provide an offset delay amount according to an offset selection signal for amending the difference between the actual delay amount and the ideal delay amount, as shown in
The multiplier 1305, which is coupled to the adder 1307, is used for generating the multiplied input selection signal MIDS. The adder 1307 is used for combining the multiplied input selection signal MIDS and the offset delay selection signal OS to generate the combined input selection signal CIDS.
Moreover, the delay circuit 1200 shown in
The methods corresponding to the above mentioned circuits can be obtained according to the above-mentioned description, and are therefore omitted for brevity.
According to the above-mentioned circuits and methods, not only can a desired delay amount be obtained by mapping, but a mapping table can also be generated according to the reference signal generated from the delay circuit to be mapped. Also, a monotonic delay circuit can be obtained accordingly. Preferably, the steps of generating the mapping table and selecting desired delay stages by mapping can be performed by the same circuit.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention.
