using a separate time interval to calibrate the delay

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HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE

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H03K2005/0011using a separate time interval to calibrate the delay

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Patents Grantslast 30 patents

Information Patent Grant
High speed on-chip precision buffer with switched-load rejection
- Patent number 10,367,486
- Issue date Jul 30, 2019
- Linear Technology Holding LLC
- Stephen Todd Van Duyne
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low frequency variation calibration circuitry
- Patent number 10,224,908
- Issue date Mar 5, 2019
- Altera Corporation
- Joshua David Fender
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Receiver, system including the same, and calibration method thereof
- Patent number 9,059,825
- Issue date Jun 16, 2015
- SK Hynix Inc.
- Han-Kyu Chi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor device including analog circuit and digital circuit
- Patent number 8,278,989
- Issue date Oct 2, 2012
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- Hiromasa Noda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DLL circuit
- Patent number 8,106,694
- Issue date Jan 31, 2012
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- Tae Kyun Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
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Delay-locked loop circuit controlled by column strobe write latency
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- Issue date Nov 1, 2011
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- Yang-ki Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
DLL circuit
- Patent number 7,969,213
- Issue date Jun 28, 2011
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- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay circuit and related method thereof
- Patent number 7,830,192
- Issue date Nov 9, 2010
- Mediatek, Inc.
- Chang-Po Ma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay circuit and related method
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- Issue date Aug 24, 2010
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- Chang-Po Ma
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Information Patent Grant
High resolution delay adjustor
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- Issue date Apr 6, 2010
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- Chao-Cheng Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Process variation tolerant circuit with voltage interpolation and v...
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- Issue date Feb 23, 2010
- President and Fellows of Harvard College
- Xiaoyao Liang
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Information Patent Grant
System and method for calibrating an adjustable delay time for a de...
- Patent number 7,578,163
- Issue date Aug 25, 2009
- Alcatel-Lucent Canada Inc
- Henry Steven Greidanus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device with delay section
- Patent number 7,548,099
- Issue date Jun 16, 2009
- Elpida Memory, Inc.
- Minari Arai
- G11 - INFORMATION STORAGE
Information Patent Grant
Network interface card (NIC) with phase lock rise time control gene...
- Patent number 7,352,755
- Issue date Apr 1, 2008
- International Business Machines Corporation
- Hayden Clay Cranford, Jr.
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Information Patent Grant
System and method for calibrating an adjustable delay time for a de...
- Patent number 7,283,917
- Issue date Oct 16, 2007
- Alcatel Canada Inc.
- Henry Steven Greidanus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor memory device with delay section
- Patent number 7,263,009
- Issue date Aug 28, 2007
- Elpida Memory, Inc.
- Minari Arai
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for calibrating delay lines
- Patent number 7,254,505
- Issue date Aug 7, 2007
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- Ronnie E. Owens
- G01 - MEASURING TESTING
Information Patent Grant
Substantially temperature independent delay chain
- Patent number 7,218,161
- Issue date May 15, 2007
- Macronix International Co., Ltd.
- Chung Kuang Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for automatically correcting timers
- Patent number 7,028,210
- Issue date Apr 11, 2006
- Siemens Energy & Automation, Inc.
- Charles Johnson
- G04 - HOROLOGY
Information Patent Grant
DAC/Driver waveform generator with phase lock rise time control
- Patent number 6,721,379
- Issue date Apr 13, 2004
- International Business Machines Corporation
- Hayden Clay Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Delay control circuit with internal power supply voltage control
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- Issue date Dec 2, 2003
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- Takahiro Seki
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Output buffer with timing feedback
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- Issue date May 22, 2001
- Intel Corporation
- Gregory F. Taylor
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Method and apparatus for controlling timing of digital components
- Patent number 6,166,576
- Issue date Dec 26, 2000
- Micron Technology, Inc.
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Clock skew circuit
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- Texas Instruments Incorporated
- Brian L. Brown
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Information Patent Grant
Delay matching circuit
- Patent number 5,376,848
- Issue date Dec 27, 1994
- Motorola, Inc.
- C. Christopher Hanke
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Pulse signal delay device, and pulse signal phase detector and cloc...
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- Issue date Jan 12, 1993
- Matsushita Electric Industrial Co., Ltd.
- Takeshi Morimoto
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Digital delay line with inverter tap resolution
- Patent number 5,095,233
- Issue date Mar 10, 1992
- Motorola, Inc.
- Laurin Ashby
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-correcting digitally controlled timing circuit
- Patent number 4,868,430
- Issue date Sep 19, 1989
- NCR Corporation
- John W. Stewart
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
HIGH SPEED ON-CHIP PRECISION BUFFER WITH SWITCHED-LOAD REJECTION
- Publication number 20190131959
- Publication date May 2, 2019
- Linear Technology Holding LLC
- Stephen Todd VAN DUYNE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RECEIVER, SYSTEM INCLUDING THE SAME, AND CALIBRATION METHOD THEREOF
- Publication number 20150139289
- Publication date May 21, 2015
- SK HYNIX INC.
- Han-Kyu CHI
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DLL CIRCUIT
- Publication number 20110221496
- Publication date Sep 15, 2011
- Tae Kyun KIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUIT AND DIGITAL CIRCUIT
- Publication number 20110131440
- Publication date Jun 2, 2011
- Elpida Memory, Inc.
- Hiromasa NODA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DLL CIRCUIT
- Publication number 20100156487
- Publication date Jun 24, 2010
- Tae Kyun KIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DELAY-LOCKED LOOP CIRCUIT CONTROLLED BY COLUMN STROBE WRITE LATENCY
- Publication number 20100156488
- Publication date Jun 24, 2010
- Samsung Electronics Co., Ltd.
- Yang-ki Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DELAY CIRCUIT AND RELATED METHOD THEREOF
- Publication number 20090322397
- Publication date Dec 31, 2009
- Chang-Po Ma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DELAY CIRCUIT AND RELATED METHOD
- Publication number 20090278549
- Publication date Nov 12, 2009
- Chang-Po Ma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Process Variation Tolerant Circuit With Voltage Interpolation And V...
- Publication number 20090134707
- Publication date May 28, 2009
- Xiaoyao Liang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DELAY CIRCUIT AND RELATED METHOD THEREOF
- Publication number 20080309391
- Publication date Dec 18, 2008
- Chang-Po Ma
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
High resolution delay adjustor
- Publication number 20080048748
- Publication date Feb 28, 2008
- Realtek Semiconductor Corp.
- Chao-Cheng Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor device with delay section
- Publication number 20070291559
- Publication date Dec 20, 2007
- Elpida Memory, Inc.
- Minari Arai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for calibrating an adjustable delay time for a de...
- Publication number 20070131019
- Publication date Jun 14, 2007
- Henry Steven Greidanus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND APPARATUS FOR CALIBRATING DELAY LINES
- Publication number 20070005285
- Publication date Jan 4, 2007
- Ronnie E. Owens
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor memory device with delay section
- Publication number 20060227631
- Publication date Oct 12, 2006
- Elpida Memory, Inc.
- Minari Arai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Substantially temperature independent delay chain
- Publication number 20060038600
- Publication date Feb 23, 2006
- Chung Kuang Chen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for automatically correcting timers
- Publication number 20040236976
- Publication date Nov 25, 2004
- Charles Johnson
- G04 - HOROLOGY
Information Patent Application
Fully digitally controlled delay element with wide delay tuning ran...
- Publication number 20040064749
- Publication date Apr 1, 2004
- Byron D. Grossnickle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DAC/driver waveform generator with phase lock rise time control
- Publication number 20030198237
- Publication date Oct 23, 2003
- International Business Machines Corporation
- Hayden Clay Cranford
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
System and method for calibrating an adjustable delay time for a de...
- Publication number 20030106361
- Publication date Jun 12, 2003
- Henry Steven Greidanus
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor device
- Publication number 20030030483
- Publication date Feb 13, 2003
- Takahiro Seki
- H03 - BASIC ELECTRONIC CIRCUITRY

using a separate time interval to calibrate the delay

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

High speed on-chip precision buffer with switched-load rejection

Low frequency variation calibration circuitry

Receiver, system including the same, and calibration method thereof

Semiconductor device including analog circuit and digital circuit

DLL circuit

Delay-locked loop circuit controlled by column strobe write latency

DLL circuit

Delay circuit and related method thereof

Delay circuit and related method

High resolution delay adjustor

Process variation tolerant circuit with voltage interpolation and v...

System and method for calibrating an adjustable delay time for a de...

Semiconductor device with delay section

Network interface card (NIC) with phase lock rise time control gene...

System and method for calibrating an adjustable delay time for a de...

Semiconductor memory device with delay section

Method and apparatus for calibrating delay lines

Substantially temperature independent delay chain

System and method for automatically correcting timers

DAC/Driver waveform generator with phase lock rise time control

Delay control circuit with internal power supply voltage control

Output buffer with timing feedback

Method and apparatus for controlling timing of digital components

Clock skew circuit

Delay matching circuit

Pulse signal delay device, and pulse signal phase detector and cloc...

Digital delay line with inverter tap resolution

Self-correcting digitally controlled timing circuit

Patents Applicationslast 30 patents

HIGH SPEED ON-CHIP PRECISION BUFFER WITH SWITCHED-LOAD REJECTION

RECEIVER, SYSTEM INCLUDING THE SAME, AND CALIBRATION METHOD THEREOF

DLL CIRCUIT

SEMICONDUCTOR DEVICE INCLUDING ANALOG CIRCUIT AND DIGITAL CIRCUIT

DLL CIRCUIT

DELAY-LOCKED LOOP CIRCUIT CONTROLLED BY COLUMN STROBE WRITE LATENCY

DELAY CIRCUIT AND RELATED METHOD THEREOF

DELAY CIRCUIT AND RELATED METHOD

Process Variation Tolerant Circuit With Voltage Interpolation And V...

DELAY CIRCUIT AND RELATED METHOD THEREOF

High resolution delay adjustor

Semiconductor device with delay section

System and method for calibrating an adjustable delay time for a de...

METHOD AND APPARATUS FOR CALIBRATING DELAY LINES

Semiconductor memory device with delay section

Substantially temperature independent delay chain

System and method for automatically correcting timers

Fully digitally controlled delay element with wide delay tuning ran...

DAC/driver waveform generator with phase lock rise time control

System and method for calibrating an adjustable delay time for a de...

Semiconductor device