Claims
- 1. A circuit arrangement for delaying electrical signals including:a delay cell; and a control circuit, said control circuit including an operational amplifier with an output coupled to the delay cell, and a pair of inputs; a series connected P-Channel and N-Channel devices operatively coupled to one of the pair of inputs; an input node for receiving a control signal operatively connected to the N-Channel device; a resistive network coupled to another of the pair of inputs; and a current mirror operatively coupled to the input node and the resistive network.
- 2. The circuit arrangement of claim 1 wherein the delay cell includes:a differential pair of N-Channel devices; a pair of pull-up P-Channel devices, each one of said pair connected to each one of the N-Channel devices; an N-Channel device operatively coupling the differential pair of N-Channel devices to a first potential; a pair of output ports, each one operatively positioned between one of the differential pair of N-Channel devices and one of the pair of pull-up P-Channel devices; a first capacitor coupling one of the pair of output ports to the first potential; and a second capacitor coupling another of the pair of output ports to the first potential.
- 3. A control circuit for use with a delay cell including:an operational amplifier with an output and a pair of inputs; a series connected P-Channel and N-Channel devices operatively coupled at a point between said devices to one of the pair of inputs; an input node for receiving a control signal operatively connected to the N-Channel device; a resistive network operatively coupled to another one of the pairs of inputs; and a current mirror operatively coupled to the input node and the resistive network wherein the resistive network and current mirror coact to set an output signal from said operational amplifier at a predetermined voltage level.
- 4. The circuit arrangement of claims 1 or 3 wherein the resistive network includes at least two series connected resistors.
- 5. The circuit arrangement of claim 4 wherein the current mirror includes a pair of P-Channel devices operatively connected in a parallel configuration; andan N-Channel device operatively coupled to the P-Channel devices.
CROSS REFERENCE TO RELATED PATENT APPLICATION
The present patent application relates to patent application Ser. No. 09/160,927 filed currently herewith and assigned to the assignee of the present invention.
US Referenced Citations (11)