Dense high performance JFET compatible with NPN transistor formation and merged BIFET

Abstract

A high performance JFET structure and process are disclosed which are compatible with high performance NPN transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and gate in the P-type base region of what would otherwise have been an NPN transistor. Both an NPN type BIFET and an PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

Description

FIELD OF THE INVENTION

The invention broadly relates to semiconductor structures and more particularly relates to junction field effect transistors.

BACKGROUND OF THE INVENTION

Previous methods for fabricating JFET's in the same silicon integrated circuit process with NPN transistors have used an N-type epitaxial layer as the N channel region where P+ base regions acted as the gate and N+ contacts as the source and drain regions.

This approach pays a penalty in device size and performance as the N-type epitaxial layer with its large tolerance in thickness and resistivity, dominated the JFET characteristics.

M. N. Phan, et al, "A Fast 1024-Bit Bipolar RAM Using JFET Load Devices", 1977 IEEE International Solid State Circuit Conference, Digest of Technical Papers, pp. 7071 and 238 discloses the formation of an N-epitaxial layer on top of a P-type substrate, through which a recessed oxidation isolation is formed which goes through the epitaxial layer and into the substrate. The process of oxidation at the epitaxial layer/substrate interface depletes the substrate surface of the boron P-type dopant, thereby forming an N-type channel along the bottom of the recessed oxide, which becomes the channel of the JFET. This JFET process, which is compatible with a bipolar process, contributes no control over the transconductance characteristics of the JFET device. Furthermore, the JFET device cannot be used as a switch since the entire epitaxial layer itself is the gate for the device and cannot be switched at a rapid enough rate to enable its use as a practical logical element.

B. Jayant Baliga, et al., "Gambi: Gate Modulated Bipolar Transistor", Solid State Electronics, 1975, Vol. 18, pp. 937,941, discloses a merged JFET device and bipolar transistor which merges the collector of the PNP transistor with the gate of the JFET. By reverse biasing the base/collector junction, the base current is pinched off in JFET fashion, using the N-type epitaxial layer as the channel. The JFET device is subject to the variability in the epitaxial layer thickness and doping levels which yields a JFET device having broad tolerances in the transconductance. The device can only be used as a bistable device and never as an active logic switch.

The device makes poor use of silicon area and has a different structure than that disclosed in the subject disclosures.

OBJECTS OF THE INVENTION

It is therefore an object of the invention to provide an improved junction field effect transistor device.

It is another object of the invention to provide a more dense junction field effect transistor device.

It is still another object of the invention to provide a junction field effect transistor device having reduced tolerances in its functional characteristics.

It is yet another object of the invention to provide a junction field effect transistor which can be readily fabricated in existing bipolar processes.

It is an object of the invention to provide an improved active load in a bipolar logic circuit.

It is still another object of the invention to provide a merged junction field effect transistor and a bipolar transistor device which permits the implementation of complex logic functions in a reduced area.

SUMMARY OF THE INVENTION

These and other objects, features and advantages of the invention are accomplished by the dense high performance JFET compatible with NPN and PNP transistor formation and merged drain BIFET, disclosed herein.

A high performance JFET structure and process are disclosed which are compatible with high performance NPN bipolar transistors. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion of what would otherwise have been an NPN transistor. In the BIFET merged device, the JFET and bipolar transistor share a common base and drain and a common collector and a gate in the P-type base region of what would otherwise have been an NPN transistor. Both NPN type BIFET and PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

The JFET, as an active load in a bipolar logic circuit, provides a controllable impedance for reduced power dissipation without greatly increasing the complexity of the bipolar process.

The merged JFET/bipolar device provides a very dense logic function when the JFET is used as a switch, yielding a 30% area reduction for the JFET/PNP and a 34% area reduction for the JFET/NPN, when compared with unmerged layouts. When the JFET is used as an active load device in a bipolar circuit, it provides a substantially reduced power dissipation characteristic over other types of loads. The JFET/bipolar structure is extendable to multiple JFET/PNP devices for the implementation of complex logic functions.

DESCRIPTION OF THE FIGURES

These and other objects, features and advantages of the invention will be more fully appreciated with reference to the accompanying figures.

FIG. 1 is a doping profile of an NPN transistor after processing, as described in copending U.S. patent application, Ser. No. 829,302, in FIG. 3I.

FIG. 2A is a cross-sectional view of the JFET device prior to the implantation of the channel region, this figure corresponding to the NPN transistor structure of FIG. 3I in the referenced copending application, with the omission of the collector diffusion 38 and the extension of the base region 40 to envelope the N+ difusion 56.

FIG. 2B is a cross-sectional view of the structure of FIG. 2A, after the ion-implanted channel region 80 has been introduced.

FIG. 3 is a doping profile of the structure of FIG. 2B showing the N channel region 80 formed in the NPN base region 40.

FIG. 4 is an electrical circuit schematic of the merged PNP/JFET device forming the logical function NAND.

FIG. 5 is a cross-sectional view of a conventional, double diffused PNP device and the N channel JFET invention, where the PNP device is fabricated in the referenced copending application FIGS. 3A through 3I and the JFET device is as shown in FIG. 2B, herein.

FIG. 6 is a cross-sectional view of the merged PNP and JFET device which has been accomplished by combining the common N-epitaxial regions of the PNP base and JFET drain in FIG. 5, where the drain is now formed by the deep N-type region 36.

FIG. 7 is a plan view of the structure shown in FIG. 6.

FIG. 8 is an electrical schematic showing the formation of multiple JFET device and/or multiple emitter/collector PNPs for expanded logic function.

FIG. 9 is a cross-sectional view of a conventional NPN and the N channel JFET invention device where the NPN transistor is fabricated by the same process as shown in FIGS. 3A through 3I of the referenced copending patent application, with the omission of the reach through 38, and the JFET is fabricated as was disclosed in FIG. 2B, herein.

FIG. 10 is a cross-sectional view of the merged NPN and N channel JFET of FIG. 9, where the reach through collector 38 has been combined to serve as the NPN collector and the source of the JFET.

FIG. 11 is a plan view of the structure shown in FIG. 10.

FIG. 12 is an electrical circuit schematic of the merged NPN and N channel JFET structure for accomplishing a complex logical function of a NAND, and other complex logical functions.

FIG. 13 is an electrical schematic showing that more than one JFET and/or more than one bipolar transistor can be placed in parallel to form expanded logical gates for a complex logical function.

FIG. 14 is a cross-sectional view of a JFET as a variable load when merged with an NPN bipolar transistor.

FIG. 15 is an electrical schematic of the merged JFET load and NPN transistor.

DISCUSSION OF A PREFERRED EMBODIMENT

Previous methods for fabricating JFET's in the same silicon integrated circuit process with NPN bipolar transistors have used the N-type epitaxial layer as the N channel region where P+ base regions acted as the gate and N+ contacts the source and drain regions.

This approach pays a penalty in device size and performance as the N-type epitaxial layer with its large tolerance in thickness and resistivity, dominated the JFET characteristics. The process described here takes advantage of the double boron implant, defining the P-type base region proposed in the simplified NPN processes with ion-implanted structures to fabricate with one additional mask and implant step a high performance JFET, with very controllable characteristics. The sequence follows conventional masking and process techniques through epitaxial growth and reoxidation. The base and emitter structure can be fabricated using standard diffusion and masking techniques, however, better control of the JFET is obtained when the emitter-base is implanted as outlined in FIGS. 3A through 3I of copending U.S. patent application, Ser. No. 829,302, filed Aug. 31, 1977 by D. L. Bergeron, et al., and assigned to the instant assignee, and the implanted structure will be discussed here.

FIG. 1 shows a doping concentration profile of the implanted emitter base structure after complete processing. FIG. 2A corresponds to the NPN transistor structure of FIG. 3I in the referenced copending application, with the omission of the collector diffusion 38 and the extension of the base region 40 to envelop the N+ diffusion 56. In FIG. 2A, N+ diffusions 56 and 54 form the drain and source regions of the JFET, respectively. The P-type region 40 is the JFET gate and the P+ region 68 is the gate contact. All other numbered structures in FIG. 2A correspond to the same numbered structures in FIG. 3I of the referenced application. FIG. 2B shows the subsequent photoresist layer masking 82 and implant step used to form the JFET channel 80. The channel implant 80 need only be juxtaposed to N+ regions 56 and 54. The channel length is defined by the spacing between regions 54 and 56. The channel width is defined by implant mask layer 84. FIG. 3 shows a doping concentration profile of the JFET detailing the N-type region formed by the .about.400 Kev low dose phosphorus or other N-type implant. The dose is used to determine the extent to which the P-type base region 40 is compensated and hence the gate threshold voltage of the JFET. FIG. 3 indicates the peak of the phosphorous is implanted to lie in the region between the two peaks of the double boron implant used to define the base region 40 of the NPN. Such a structure has very controllable characteristics and is limited by the control of dose and energy used to define the P base and N-channel regions.

Dense JFET arrays are possible since they can be placed in a common N-type epitaxial region.

The high performance JFET structure and process described above is compatible with high performance NPN and PNP transistors. The JFET can be employed as a switched device or as an active load in a bipolar logic circuit and is formed in the P-type base diffusion 40 of what would otherwise have been an NPN transistor. The high performance JFET is merged in a bipolar/FET device which forms a dense, two level logic function. In the BIFET merged device, the JFET and bipolar transistor share common elements in order to reduce the number of interconnection contact windows and the required silicon area. Both NPN type BIFET and PNP type BIFET are disclosed. The merged JFET and bipolar transistor provide better than a 30% area reduction when compared to their non-merged precursors.

As shown by the schematic of FIG. 4, the double diffused PNP and JFET can be connected to form a logical NAND function of inputs A and B. An implementation of that logic gate is shown in the cross-section of FIG. 5, where the conventional PNP device is fabricated as shown in FIGS. 3A through 3I of the referenced copending application. The JFET is shown in FIG. 2B, herein. By combining the common N-type epitaxial regions 4 and the PNP base contact 70, 34 and JFET drain 56 the physical size of the logic gate can be reduced by .about.30%. The cross-section of this merged structure is shown in FIG. 6 where the deep N region 36 forms the PNP base contact and JFET drain. The deep N region 36 can be used to form the JFET drain since it is self-aligned to and is isolated from the shallower N+ source region 54 by P gate region 40. The plan view is shown in FIG. 7 where the channel region 20 is shown bounded by the P gate region 40, and the drain/base contact 36, and source 54. This concept is extendable to form multiple JFET's and/or multiple emitter/collector PNP's for expanded logical functions. This would be done by repeating the layout of FIG. 7 in the vertical direction in a common epitaxial region. The schematic of such a cell is shown in FIG. 8. The common node F corresponds to the common epitaxial region.

This scheme can be also used to merge the source with the collector of a conventional NPN transistor to achieve the logical function shown in FIG. 12. An implementation of that logic gate using the conventional NPN device is shown in cross-section in FIG. 9. The NPN of FIG. 9 is formed as in FIGS. 3A through 3I of the referenced copending application. The JFET is formed as shown in FIG. 2B, herein. By combining the reach through collector 38 to serve as both the NPN collector and source of the JFET, the physical size of the logic gate can be reduced by approximately 34% as shown in cross-section of FIG. 10 and plan view of FIG. 11. The reduction comes from the elimination of the separate source contact region 56 and the intervening isolation 42 and epitaxial region.

Combinations of the above schemes can be used to fabricate several combinations of logical functions with significant savings in silicon area.

FIG. 13 shows the electrical schematic of several merged NPN and JFET transistors in accordance with the invention.

Further, the JFET can be used as a variable load when merged with the NPN by electrically tying the gate to the merged collector/source. This is shown in cross-section in FIG. 14 and in circuit schematic of FIG. 15. The JFET becomes nonconductive (pinched off) when the NPN collector is low (conductive). The JFET is conductive when the NPN collector is high (non-conductive).

The JFET, as an active load in a bipolar logic circuit, provides a controllable impedance for reduced power dissipation with a minimal increase of the complexity of the bipolar process.

The merged JFET/bipolar device provides a very dense logic function when the JFET is used as the switch, yielding a 30% area reduction for the JFET/PNP and a 34% area reduction for the JFET/NPN, when compared with unmerged layouts. When the JFET is used as an active load device in a bipolar circuit, it provides a substantially reduced power dissipation characteristic over other types of load. The JFET/bipolar structure is extendable to multiple JFET/bipolar transistors for the implementation of complex logic functions.

While the invention has been particularly shown and described with reference to the preferred embodiment thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and details may be made therein without departing from the spirit and scope of the invention.

Claims

1. In an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type base regions of vertical NPN transistors, a Junction Field Effect Transistor (JFET) device formed in one of a second subplurality of said plurality of P-type regions, comprising:

an insulating layer on the surface of said one P-type region having first and second windows therein;

a first N-type region in said one P-type region formed through said first window for the JFET source;

a second N-type region spaced from said first N-type region in said one P-type region formed through said second window for the JFET drain;

an ion-implanted N-type channel region in said one P-type region connected to said source and drain regions;

said one P-type region serving as the gate for the JFET device;

said one P-type region extending horizontally beyond said first N-type region, with said first N-type region extending horizontally and vertically to separate said one P-type region into first and second P-type portions which are electrically isolated from one another, said first portion being said gate for said JFET device;

a third window in said insulating layer over said second P-type portion;

a third N-type region formed through said third window, as an emitter in an NPN transistor formed with said second P-type portion as the base and said first N-type region serving as the collector thereof;

whereby a series connected JFET and NPN bipolar transistor are formed with said first N-type diffusion serving as the output node thereof.

2. The device of claim 1 which further comprises:

a conductor connecting said first P-type portion to said first N-type region;

whereby said JFET operates as a self-biased load device connected in series with the collector of said NPN bipolar transistor.

3. In an integrated circuit having a plurality of P-type regions formed in the same process step, a first subplurality of which are P-type collector regions of double diffused lateral PNP transistors, a Junction Field Effect Transistor (JFET) device formed in one of a second subplurality of said plurality of P-type regions, comprising:

an insulating layer on the surface of said one P-type region having first and second windows therein;

a first N-type region in said one P-type region formed through said first window for the JFET source;

an insulating layer on the surface of said one P-type region having first and second windows therein;

a first N-type region in said one P-type region formed through said first window for the JFET source;

a second N-type region spaced from said first N-type region in said one P-type region formed through said second window for the JFET drain;

an ion-implanted N-type channel region in said one P-type region connected to said source and drain regions;

said one P-type region serving as the gate for the JFET device;

said one P-type region extending horizontally beyond said second N-type region, said second N-type region extending horizontally and vertically to separate said one P-type region into first and second P-type portions which are electrically isolated from one another, said first portion being said gate for said JFET device;

a third window in said insulating layer over said second P-type portions;

a third N-type region formed through said third window as a base region and a third P-type region formed through said third window and contained within said third N-type region as the emitter of a PNP lateral transistor, formed with said second P-type portion as the collector thereof;

whereby series connected JFET and lateral PNP bipolar transistors are formed.