1. Technical Field
The subject matter of this disclosure relates to solar energy technology, and in one or more embodiments to structures that mount devices that generate electrical power in response to light in energy conversion systems, e.g., concentrator photovoltaic (“CPV”) systems and modules.
2. Description of Related Art
Photovoltaic devices convert solar energy (or “sunlight”) into electricity. The rate of conversion of sunlight to electricity depends on the available area of the photovoltaic devices. Thus, photovoltaic devices that operate at levels of efficiency that are higher than other photovoltaic devices are able to achieve a higher rate of conversion for the same area. In one example, silicon-based photovoltaic devices have a level of efficiency of about 17% (i.e., these cells can convert 17% of the sunlight they receive into electricity).
Concentrator photovoltaic cells (also “CPV cells”) can generate electricity at a relatively higher level of efficiency than these silicon-based photovoltaic devices. CPV cells often comprise materials, e.g., gallium arsenide and/or germanium, in several layers with multiple junctions. This construction affords the CPV cells with levels of efficiency that are greater than the levels of efficiency of silicon-based photovoltaic devices. For example, multi junction CPV cells often exhibit levels of efficiency of greater than 40% because these devices can convert a greater portion of the solar spectrum into electricity.
These high levels of efficiency make multi junction photovoltaic devices advantageous for use in energy conversions systems. These systems often arrange hundreds (and/or even thousands) of photovoltaic devices in large arrays to capture and convert sunlight to electricity. Unfortunately, high material and manufacturing costs can prohibit implementation of multi junction photovoltaic devices in the large numbers necessary to allow energy conversion systems to generate electricity at adequate costs metrics. One solution to reduce the overall cost, however, is to concentrate sunlight from a large area onto a much smaller area which comprises the multi junction photovoltaic devices (e.g., the CPV cells). Concentrating the sunlight in this matter enables the multi junction photovoltaic devices to operate at levels of efficiency that are relatively greater than silicon-based photovoltaic devices. Because of the improvements in efficiency, the system requires fewer CPV cells to generate comparable amounts of electricity.
Concentrating systems, also known as concentrator photovoltaic (CPV) systems, may concentrate light using a number of different configurations. In one configuration, the system arranges lenses (e.g., refractive lenses) in an array. The lenses focus sunlight onto a corresponding array of CPV cells (also, a “cell receiver assembly (CRA)). In another configuration, the system includes a set of reflective mirrors that reflect a large area of sunlight onto a corresponding array of CPV cells (also called a “dense receiver array (“DRA”)). The DRA is smaller than the CRA because the DRA can incorporate the CPV cells onto a single substrate. However, although use of this single substrate can result in cost savings (e.g., on materials) as compared to the CRA, the DRA arrangement creates additional challenges associated with heat dissipation and, in one example, the need to include additional elements, e.g., by-pass diodes, because of the close packing density of CPV cells on the single substrate. Moreover, many DRAs lack the ability to arrange the CPV cells with sufficient density (i.e., to closely pack the array of CPV cells) to limit efficiency loss due to exposure of non-generating areas of the CPV cells to sunlight while also maintaining acceptable thermal performance.
This disclosure describes improvements to CPV systems and, in particular, to DRAs to provide adequate exposure of the solar reactive areas of photovoltaic devices, while maintaining adequate heat dissipation and electrical conduction. These improvements allow CPV systems that implement embodiments of the proposed components to convert solar energy to electricity more efficiently and cost-effectively. In one embodiment, the components incorporate one or more bypass elements (e.g., a diode) and a cooling mechanism within a single device to enable reliable but low-cost manufacturing processes. This disclosure also contemplates a substrate and a cell receiver assembly that supports the substrate, e.g., for use in concentrator photovoltaic (“CPV”) systems and modules.
As set forth in more detail below, examples of the substrate include an integrated bypass diode. The substrate can also support a plurality of photovoltaic devices (e.g., CPV cells) and, in other examples, chips, semiconductor chips, solar chips, etc. Construction of the substrate can position the photovoltaic devices to vary the configuration, e.g., to overlap with one or more adjacent photovoltaic devices to form a “shingled” pattern or configuration. These configurations maximize exposure of the solar sensitive portions of the photovoltaic devices to sunlight. In one embodiment, the components can comprise a CPV cell, a substrate manufactured to integrate the CPV cell and internally incorporate bypass elements, and a back metal layer (and/or array) designed to integrate with a cooling mechanism, e.g., a metal cooling fluid distribution plate.
Reference is now made briefly to the accompanying drawings, in which:
Where applicable like reference characters designate identical or corresponding components and units throughout the several views, which are not to scale unless otherwise indicated.
Embodiments of the receiver component 100 maintain performance of the power generating device 102 to accommodate for uneven distribution of sunlight across the photosensitive component 104. In one embodiment, construction of the power generating device 102 electrically couples adjacent photosensitive devices. Use of the bypass element 116 enables current to pass between these adjacently-coupled photosensitive device during, for example, periods of no and/or low sunlight that can inhibit one or more of the photosensitive devices from generating photocurrent. Examples of the bypass element 116 can comprise a diode device and like elements and components that restrict (and/or prevent) current flow in a first direction and allow (and/or enable) current flow in a second direction that is different from the first direction. As shown in
The cooling component 108 utilizes cooling fluid to regulate temperature during operation of the photosensitive device 104. The combination of cooling fluid with electrical components runs counter to more typical heat dissipation theory (which uses large, thermally- conductive heat sinks and/or fans to move air). These conventional methodologies are designed to avoid shorting and other complications that fluids (e.g., water) can cause, e.g., during operation of the power generating device 102. Examples of the cooling component 108 can form one or more fluid paths and/or channels that allow cooling fluid to flow about the receiver component 100. In one example, the cooling component 108 can have an inlet and an outlet to allow ingress of relatively cold cooling fluid from an external fluid supply and egress of relatively warmer cooling fluid from the cooling component 108. This configuration can maintain continuous flow of the cooling fluid to maximize thermal dissipation.
Although discussed relative to photosensitive components, construction of the receiver component 100 can accommodate devices other than photosensitive devices discussed herein. Integration of the bypass element and use of the cooling component can prove advantageous for many devices (e.g., semiconductor devices, semiconductor-based lasers, light-emitting diode (LED) devices, etc.). To this end, examples of the substrate component 106 with integrated bypass element 116 can find use in other applications, e.g., for supporting and mounting of semiconductor chips, processors, and like semiconductor devices. These configurations find benefit in the use the functionality of the bypass element 106 as it relates to coupling of adjacent semiconductor devices as well as the improved cooling capabilities that incorporation of the cooling component 108 offer to the proposed designs.
Examples of the substrate component 206 can include a base substrate that comprises one or more semiconductor substrate materials (e.g., silicon, SiC, germanium, etc.). The base substrate can be manufactured using standard integrated circuit (IC) manufacturing equipment and techniques. In this way, the substrate component 206 can include various types of integrated circuitry and circuitry elements (e.g., diodes, transistors, resistors, capacitors) and structural elements (e.g., in the structural layer 234) that connect the substrate component 206 with the cooling component 208.
Processing of the base substrate can utilize photo-resist, which allows the via elements 214 to be etched and used as connections with the bypass element 216. Examples of the via elements 214 can comprise metal (e.g., copper, tungsten, etc.). In one example, the via elements 214 may also find use to mechanically align and/or couple the substrate component 206 with the cooling mechanism 208. Further processing of the base substrate, e.g., with photo-resist, can form the bypass element 216 as a diode (also “a bypass diode”). This processing can includes steps to implant a region of the base substrate with p-type and n-type dopants to form the diode. For example, the steps can deposit adjacent n-type and p-type layers on the back side (e.g., the second side 230) of the base substrate and place the via elements 214, filled with conductive material (e.g., metal) in relation to the corresponding n-type and p-type layers.
After deposition of material to form the via elements 214 and/or the bypass diode, the back side (e.g., the second side 230) of the base substrate can be coated with a di-electric material (e.g., SiO2, Si3N4, etc.) to form the second insulating layer 234. This di-electric material can electrically isolate the base substrate from the cooling component 206. Further processing steps can deposit one or more additional material layers (e.g., copper, aluminum, silver, etc.) to form the structural layer 234. Deposition of these material layers may utilize electroplating to thicken the structural layer 234. The resulting layer can couple the substrate component 206 with the cooling mechanism 208, e.g., using solder, brazing, or other techniques.
Additional processing steps can deposit a di-electric material (e.g., SiO2, Si3N4, etc.) on the front side (e.g., the first side 228) of the base substrate to form the first insulating layer 224. Portions of this di-electric material can be removed to form patterned openings, which conductive material (e.g., copper, aluminum, silver, etc.) of the conductive layer 232 can fill to form pads and/or other circuitry (e.g., electrical components, connections, etc.). This circuitry can conduct electrical signals and, in one construction, the circuitry may interconnect, e.g., with the by-pass diode in the substrate component 206.
As also shown in
The front side (e.g., first side 228) of the base substrate can be patterned to form the mounting areas 340, 342. This pattern can be formed by removing material of the base substrate, e.g., by various techniques including mechanical (e.g., mechanical saw, laser, water jet, etc.) and chemical (e.g., etching). Di-electric material (e.g., SiO2, Si3N4, etc) forming the first insulating layer 334 can reside in the mounting areas 340, 342. In the present example, the mounting areas 340, 342 pitch and/or tilt the photovoltaic devices 344, 346. This configuration causes the second photovoltaic device 346 to overlap with the first photovoltaic device 344, thereby forming a “shingled” configuration. In one example, the device 302 can include a device connection (e.g., a device connection 371) that electrically couples the first photovoltaic device 344 to the second photovoltaic device 346.
During one manufacturing process, the photovoltaic device 344 can be mounted to the base substrate by depositing an interface medium (e.g., silver epoxy, solder, etc.) at the mounting area 340. The photovoltaic devices 344, 346 can be placed upon the interface medium, interconnection material can then be placed upon the mounting area 342, and the photovoltaic device 346 can be mounted in position. This process can continue until all mounting areas contain photovoltaic devices. As the photovoltaic devices are placed upon the corresponding mounting locations, the interconnecting medium will flow across the entire back-side of the photovoltaic cell while also flowing on top of the adjacent photovoltaic cell. Melting and cooling of the interconnection medium can make connections, e.g., on the bottom side of the photovoltaic device 346 and the top side of the photovoltaic device 344, thereby connecting a plurality of CPV cells in series (and/or forming a series circuit).
The structural layer 334 can comprise material that is patterned to form one or more of the standoffs 354, 356 using techniques often used to form one or more types of semiconductor copper pillars that form interconnects on semiconductor and semi-conductor based chips. Examples of the standoffs 354, 358 can fasten to the cooling mechanism 308, e.g., to the upper member 362, using a bonding agent (e.g., adhesive) and/or other fastening scheme (e.g., mechanical fasteners). Material for use as the standoffs 354, 356 may be conductive (e.g., metal) and/or non-conductive (e.g., di-electric). In one embodiment, the cooling mechanism 308 secures using solder that can be pre-tinned upon the standoffs 354, 356 and/or to other regions of the substrate component 306. This process can occur on the back side (e.g., the second side 236 of
Construction of the cooling component 306 can utilize various materials to form the cavity 370. This construction may form a monolithic unit, e.g., the lower member 360, the upper member 362, and any side walls or members (not shown) are formed as a single, contiguous unit. On the other hand, this disclosure contemplates construction of the fluid distribution unit 358 in multiple pieces, which are assembled and fastened together (using known techniques).
In one embodiment, the base substrate may incorporate one or more cavities (e.g., a first substrate cavity 374 and a second substrate cavity 376). The cavities 374, 376 can permit the cooling fluid 370 to penetrate into the substrate component 306. This configuration can dissipate more thermal energy from the substrate component 306. Examples of the cavities 374, 376 can be constructed to also permit the cooling fluid 370 to flow in closer proximity to the photoelectric devices 344, 346. This feature can more directly regulate the temperature to maintain operating efficiencies of the photoelectric devices 344, 346.
In
As used herein, an element or function recited in the singular and proceeded with the word “a” or “an” should be understood as not excluding plural said elements or functions, unless such exclusion is explicitly recited. Furthermore, references to “one embodiment” of the claimed invention should not be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.
This written description uses examples to disclose embodiments of the invention, including the best mode, and also to enable any person skilled in the art to practice the invention, including making and using any devices or systems and performing any incorporated methods. The patentable scope of the invention is defined by the claims, and may include other examples that occur to those skilled in the art. Such other examples are intended to be within the scope of the claims if they have structural elements that do not differ from the literal language of the claims, or if they include equivalent structural elements with insubstantial differences from the literal language of the claims.
This application claims the benefit of priority to U.S. Provisional Patent Application Ser. No. 61/585,394, filed on Jan. 11, 2012 and entitled “Dense Receiver Array Substrate with Integrated Bypass Diode.” The content of this application is incorporated herein by reference in its entirety.
Number | Date | Country | |
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61585394 | Jan 2012 | US |