BRIEF DESCRIPTION OF THE DRAWINGS
The subject matter which is regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other objects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic top perspective view of a metal fill region of a semiconductor chip;
FIG. 2 is a schematic cross-section view of a metal fill region of a semiconductor chip;
FIG. 3 is a schematic cross-section view of a metal fill region of a semiconductor chip, showing layer sets that include multiple insulation layers; and
FIG. 4 is a flow diagram of an exemplary design process used in semiconductor design, manufacturing, and/or test.
DETAILED DESCRIPTION OF THE INVENTION
Metal fill regions of circuits are areas of the circuit that contain little or no metal for wiring or power distribution. These regions must come close to matching the density of actively wired regions of the circuit to limit dishing during CMP, and thus metal fill is disposed within these regions. A strategy for disposing metal fill in these regions is discussed hereinbelow.
Referring to FIGS. 1 and 2, a metal fill region 10 of a semiconductor chip is illustrated. The region 10 includes a plurality of metal fill layers 12 and insulation layers 14 disposed in planes 15 parallel to each other. The insulation layers 14 are disposed between the metal fill layers 12. Any insulation layer 14 may be grouped with any two metal fill layers 12 it is disposed between, with this group comprising a layer set 16. There may be a plurality of layer sets 16 and 16a included in the region 10.
As is illustrated in FIG. 2, the layer set 16 includes a first metal fill layer 18 and a second metal fill layer 20 (both of which being metal fill layers 12), with one of the insulation layers 14 of the region 10 being disposed between the first and second metal fill layers 18 and 20. Along with the layer set 16, FIG. 2 also illustrates the second layer set 16a. It should be appreciated that the second metal fill layer 20 of layer set 16, also functions as a first metal fill layer 18a of second layer set 16a. Thus layer sets 16 and 16a can “share” the metal fill layer 20/18a, as can any other non-illustrated layer sets that overlap in this manner.
For simplicity purposes, the metal fill layers 12 and insulation layer 14 will now be discussed in relation to the layer set 16 only (not 16a). Referring back to FIGS. 1 and 2, each metal fill layer 12 includes a plurality of metal fill pieces 22. Each metal fill piece 22 of both the first metal fill layer 18 and second metal fill layer 20 includes a metal fill piece axis 24 (the axis 24 of the figures is not a tangible element, but a representation of axis position). Each axis 24 perpendicularly intersects the planes 15 of the first metal fill layer 18, second metal fill layer 20, and insulation layer 14 from any point of reference. The metal fill pieces 22 are positioned so that the axis 24 of each piece 22 in the first metal fill layer 18 is linearly displaced of the axis 24 of each piece 22 in the second metal fill layer 20. The linear displacement occurs in at least one direction orthogonal to the axes 24, such as directions 30 and 32. This displacement creates a metal fill pattern 33 in the metal fill layers 12 that off-sets the metal fill pieces 22 of the metal fill layers nearest to each other, with this off-setting occurring throughout all the metal fill layers 12 of the region 10. Offsetting the pieces 22 in this manner reduces capacitance within the metal fill region 10, while allowing the region 10 to still contain enough metal fill pieces 22 to provide the density requirements of the semiconductor chip.
As is shown best in FIG. 3, the insulation layers 14 also include metal fill in the form of plurality of metal interconnector fill pieces 40. These interconnector pieces 40, which are also known as via, traverse the insulation layers 14 of the circuit, and connect (in active circuits) routing wire and I/O wire in the metal wire containing layers (again of an active circuit). In the metal fill region 10 of the circuit, there is no need to connect the metal fill of one metal fill layer 12 with the metal fill of another metal fill layer 12, as there is no active electrical transmission running through the metal region 10. However, there may be a desire to match density of the insulation layers 14 of the metal fill region 10 of the circuit with the density of insulation layers in active regions of the circuit, and thus, the metal interconnector fill pieces 40 may be added to the insulation layer 14 of the metal fill region 10. By matching insulation layer density along with metal wire/fill layer density, dishing can be further diminished. Like the metal fill layers 20 though, it is also desirable to offset the interconnector pieces 40 of the insulation layers 14 nearest to each other, so as to maintain a reduced capacitance.
Referring to FIG. 3, the interconnector pieces 40 are offset similarly to the metal fill pieces 22 of FIGS. 1 and 2. In FIG. 3, a layer set 42 includes a first metal fill layer 44, a second metal fill layer 46 (both of which being metal fill layers 12), a first insulation layer 48 and a second insulation layer 50, wherein the two metal fill layers 44 and 46 are alternatingly disposed with the two insulation layers 48 and 50 to preclude adjacency between the first metal fill layer and the second metal fill layer, and to preclude adjacency between the first insulation layer and the second insulation layer. Along with the layer set 42, FIG. 3 also illustrates a second layer set 42a. It should be appreciated that the second metal fill layer 46 and second insulation layer 50 of layer set 42, also function as a first metal fill layer 44a and first insulation layer 48a of the second layer set 42a. Thus layer sets 42 and 42a can “share” the metal fill layer 46/44a and insulation layer 50/48a, as can any other non-illustrated layer sets that overlap in this manner.
For simplicity purposes, the metal fill layers 12 and insulation layers 14 will now be discussed in relation to the layer set 42 only (not 42a), and since off-setting of the metal fill pieces 22 has already been discussed above, only the interconnector pieces 40 will be discussed hereinbelow. Referring back to FIG. 3, each interconnector piece 40 of both the first insulation layer 48 and second insulation layer 50 includes a metal interconnector axis 52. Each axis 52 perpendicularly intersects the parallel planes 15 of the first metal fill layer 44, second metal fill layer 46, first insulation layer 48, and second insulation layer 50. The interconnector pieces 40 are positioned so that the axis 52 of each interconnector piece 40 in the first insulation layer 48 is linearly displaced of the axis 52 of each interconnector piece 40 in the second insulation layer 50. The linear displacement occurs in at least one direction orthogonal to the axes 52, such as directions 30 and 32 (as shown in FIG. 1). This displacement creates a metal interconnector pattern 56 in the insulation layers 14 that offsets the interconnector pieces 40 of the insulation layers 14 nearest to each other, with this offsetting occurring throughout all the insulation layers 14 of the region 10. Off-setting the interconnector pieces 40 in this manner reduces capacitance within the metal fill region 10, while allowing the region 10 to still contain enough metal fill pieces 22 and interconnector pieces 40 to provide the density requirements of the semiconductor chip.
FIG. 4 is a block diagram illustrating an example of a design flow 400. Design flow 400 may vary depending on the type of IC being designed. For example, a design flow 400 for building an application specific IC (ASIC) will differ from a design flow 400 for designing a standard component. Design structure 410 is preferably an input to a design process 420 and may come from an IP provider, a core developer, or other design company or may be generated by the operator of the design flow, or from other sources. Design structure 410 comprises circuit embodiments 10 in the form of schematics or HDL, a hardware-description language, (e.g., Verilog, VHDL, C, etc.). Design structure 410 may be contained on one or more machine readable medium(s). For example, design structure 410 may be a text file or a graphical representation of circuit embodiments 10. Design process 420 synthesizes (or translates) circuit embodiments 10 into a netlist 430, where netlist 430 is, for example, a list of wires, transistors, logic gates, control circuits, I/O, models, etc., and describes the connections to other elements and circuits in an integrated circuit design and recorded on at least one of machine readable medium 415. This may be an iterative process in which netlist 430 is resynthesized one or more times depending on design specifications and parameters for the circuit.
Design process 420 includes using a variety of inputs; for example, inputs from library elements 435 which may house a set of commonly used elements, circuits, and devices, including models, layouts, and symbolic representations, for a given manufacturing technology (e.g., different technology nodes, 32 nm, 45 nm, 90 nm, etc.), design specifications 440, characterization data 450, verification data 460, design rules 470, and test data files 480, which may include test patterns and other testing information. Design process 420 further includes, for example, standard circuit design processes such as timing analysis, verification tools, design rule checkers, place and route tools, etc. One of ordinary skill in the art of integrated circuit design can appreciate the extent of possible electronic design automation tools and applications used in design process 420 without deviating from the scope and spirit of the invention. The design structure of the invention embodiments is not limited to any specific design flow.
Design process 410 preferably translates an embodiment of the invention as shown in FIGS. 1-3, along with any additional integrated circuit design or data (if applicable), into a second design structure 490. Second design structure 490 resides on a storage medium in a data format used for the exchange of layout data of integrated circuits (e.g., information stored in a GDSII (GDS2), GL1, OASIS, or any other suitable format for storing such design structures). Second design structure 490 may comprise information such as, for example, test data files, design content files, manufacturing data, layout parameters, wires, levels of metal, vias, shapes, data for routing through the manufacturing line, and any other data required by a semiconductor manufacturer to produce an embodiment of the invention as shown in FIGS. 1-3. Second design structure 490 may then proceed to a stage 495 where, for example, second design structure 490: proceeds to tape-out, is released to manufacturing, is released to a mask house, is sent to another design house, is sent back to the customer, etc.
While the invention has been described with reference to an exemplary embodiment, it should be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the invention. In addition, many modifications may be made to adapt a particular situation or substance to the teachings of the invention without departing from the scope thereof. Therefore, it is important that the invention not be limited to the particular embodiment disclosed as the best mode contemplated for carrying out this invention, but that the invention will include all embodiments falling within the scope of the apportioned claims. Moreover, unless specifically stated any use of the terms first, second, etc. do not denote any order or importance, but rather the terms first, second, etc. are used to distinguish one element from another.
Patent Application
20080082300
