Designing and operating of semiconductor integrated circuit by taking into account process variation

Information

  • Patent Application
  • 20070226660
  • Publication Number
    20070226660
  • Date Filed
    September 25, 2006
    18 years ago
  • Date Published
    September 27, 2007
    17 years ago
Abstract
A method of designing a semiconductor integrated circuit includes defining a tolerable range in which an operating temperature and an operating power supply voltage of a semiconductor integrated circuit are allowed to vary, computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused by process variation of the semiconductor integrated circuit, separately for each circuit characteristic responsive to the process variation, and designing the semiconductor integrated circuit such that the semiconductor integrated circuit properly operates with any temperature and power supply voltage within the tolerable range based on an assumption that the semiconductor integrated circuit is to operate within the tolerable range centered substantially at the target temperature and target power supply voltage.
Description

BRIEF DESCRIPTION OF THE DRAWINGS

Other objects and further features of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings, in which:



FIG. 1 is a flowchart showing a procedure from the designing of a semiconductor integrated circuit to the operating of the semiconductor integrated circuit after implementation;



FIGS. 2A and 2B are drawings for explaining the method of designing a semiconductor integrated circuit according to the present invention as compared with a related-art method of designing a semiconductor integrated circuit;



FIG. 3 is a flowchart showing a procedure from the designing of a semiconductor integrated circuit to the operating of the semiconductor integrated circuit after implementation according to the present invention;



FIG. 4A is a drawing showing an example of a variation table;



FIG. 4B is a drawing showing an example of a variation table;



FIG. 4C is a drawing showing an example of a variation table;



FIG. 4D is a drawing showing an example of a variation table;



FIG. 4E is a drawing showing an example of a variation table;



FIG. 4F is a drawing showing an example of a variation table;



FIG. 5 is a flowchart for explaining the detail of the library generating step shown at step S5 of FIG. 3;



FIG. 6 is a drawing for explaining information that is passed to the system designer;



FIGS. 7A and 7B are drawings illustrating correspondence tables that show correspondences between ranks, power supply voltages, and temperatures. Such a correspondence table is passed to the systems side together with the rank information;



FIG. 8 is a drawing showing an example of a configuration for controlling temperature on the system side; and



FIG. 9 is a drawing showing the configuration of an apparatus for performing the method of designing a semiconductor integrated circuit according to the present invention.


Claims
  • 1. A method of designing a semiconductor integrated circuit, comprising: defining a tolerable range in which an operating temperature and an operating power supply voltage of a semiconductor integrated circuit are allowed to vary;computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused by process variation of the semiconductor integrated circuit, separately for each circuit characteristic responsive to the process variation; anddesigning the semiconductor integrated circuit such that the semiconductor integrated circuit properly operates with any temperature and power supply voltage within the tolerable range based on an assumption that the semiconductor integrated circuit is to operate within the tolerable range centered substantially at the target temperature and target power supply voltage.
  • 2. An apparatus for designing a semiconductor integrated circuit, comprising: a memory unit configured to store data and a program; anda processing unit configured to process the data stored in the memory by executing the program stored in the memory,wherein the processing unit performs:defining a tolerable range in which an operating temperature and an operating power supply voltage of a semiconductor integrated circuit are allowed to vary;computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused by process variation of the semiconductor integrated circuit, separately for each circuit characteristic responsive to the process variation; anddesigning the semiconductor integrated circuit such that the semiconductor integrated circuit properly operates with any temperature and power supply voltage within the tolerable range based on an assumption that the semiconductor integrated circuit is to operate within the tolerable range centered substantially at the target temperature and target power supply voltage.
  • 3. A method of controlling an operation of a semiconductor integrated circuit, comprising: acquiring a semiconductor integrated circuit;acquiring information indicative of a circuit characteristic responsive to process variation of the semiconductor integrated circuit; andoperating the semiconductor integrated circuit with a temperature and power supply voltage responsive to the information.
  • 4. The method as claimed in claim 3, wherein the information is acquired by measuring a process monitor of the semiconductor integrated circuit.
  • 5. The method as claimed in claim 3, wherein the semiconductor integrated circuit is designed by defining a tolerable range in which an operating temperature and an operating power supply voltage of the semiconductor integrated circuit are allowed to vary, computing a target temperature and a target power supply voltage that cancel variation in circuit characteristics caused by process variation of the semiconductor integrated circuit, separately for each circuit characteristic responsive to the process variation, and designing the semiconductor integrated circuit such that the semiconductor integrated circuit properly operates with any temperature and power supply voltage within the tolerable range based on an assumption that the semiconductor integrated circuit is to operate within the tolerable range centered substantially at the target temperature and target power supply voltage.
  • 6. A semiconductor integrated circuit characterized to contain electronic data regarding a circuit characteristic responsive to process variation such that the electronic data is readable from an exterior of the semiconductor integrated circuit.
  • 7. A system for controlling a semiconductor integrated circuit, comprising: a temperature measuring unit configured to measure a temperature of a semiconductor integrated circuit;a temperature controlling unit configured to control the temperature of the semiconductor integrated circuit in response to a temperature measurement by the temperature measuring unit; anda voltage controlling unit configured to control a power supply voltage supplied to the semiconductor integrated circuit,wherein the semiconductor integrated circuit is operated with a temperature and power supply voltage responsive to information indicative of a circuit characteristic responsive to process variation of the semiconductor integrated circuit.
  • 8. The system as claimed in claim 7, wherein the information is embedded in the semiconductor integrated circuit, and the temperature controlling unit and the voltage controlling unit controls the temperature and power supply voltage of the semiconductor integrated circuit in response to the information read from the semiconductor integrated circuit.
  • 9. The system as claimed in claim 7, wherein the temperature controlling unit includes a Peltier device.
  • 10. The system as claimed in claim 7, wherein the information is represented by a cut/intact state of fuses provided in the semiconductor integrated circuit.
Priority Claims (1)
Number Date Country Kind
2006-083336 Mar 2006 JP national