Patent Application
20200274538
This disclosure relates generally to power control for circuits and more particularly to performing a corrective action in response to certain detected supply voltage conditions.
Computing devices (especially mobile devices) sometimes operate with high current loads, e.g., when multiple components are working at the same time. When a large current demand occurs, a significant drop in supply voltage may occur, potentially causing a supply voltage undershoot and ringing in the supply voltage. When one or more components are no longer used, a load release event may occur, resulting in a transient voltage spike before the power supply can adjust. This rapid voltage increase may then cause a subsequent ringing and undershoot in supply voltage, e.g., due to the inductive and capacitive characteristics of an integrated circuit. Either the voltage during the initial undershoot or the undershoot caused by a load release may correspond to the worst-case supply voltage in the system, since load releases occur in a high-load scenario where the supply voltage has already drooped.
Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply. In some embodiments, the sensor circuitry is configured to detect a load step or load release event that includes a decrease or an increase in the supply voltage that meets one or more pre-determined threshold parameters.
One of more of various sensors disclosed herein and/or other types of sensors may be used to detect the load step or load release event. In some embodiments, a sensor includes multiple comparators configured to compare supply voltage to different reference voltage and is configured to detect supply voltage events by tracking comparator outputs over multiple clock cycles. In some embodiments, a programmable sensor complex includes one or more high-pass filters, one or more low-pass filters, and one or more programmable level-sense elements. In some embodiments, a sensor includes a replica of voltage-controlled oscillator (VCO) delay stages (e.g., where the VCO has a separate power supply and the replica is powered by the supply voltage being measured) and is configured to measure phase differences between the VCO and the replica to detect changes in the supply voltage.
In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. The corrective action itself may also control the ringing of the supply voltage by affecting the frequency of the clock. In some embodiments, the corrective action avoids logic timing failures corresponding to the worst case supply voltage droop.
In some embodiments, a power supply mode with a low load line, in some embodiments less than 5mOhms, is used to control relatively lower-frequency voltage events while adjustments in clock frequency are used to control relatively higher-frequency voltage events. The lower values of load line mode may increase average supply voltage (relative to a high load line) during high current loads while the adjustments in clock frequency may control the impact of increased transients from the low load line mode.
In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and critical path failures or computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).
This specification includes references to various embodiments, to indicate that the present disclosure is not intended to refer to one particular implementation, but rather a range of embodiments that fall within the spirit of the present disclosure, including the appended claims. Particular features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.
Within this disclosure, different entities (which may variously be referred to as “units,” “circuits,” other components, etc.) may be described or claimed as “configured” to perform one or more tasks or operations. This formulation—[entity] configured to [perform one or more tasks]—is used herein to refer to structure (i.e., something physical, such as an electronic circuit). More specifically, this formulation is used to indicate that this structure is arranged to perform the one or more tasks during operation. A structure can be said to be “configured to” perform some task even if the structure is not currently being operated. A “clock circuit configured to generate an output clock signal” is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in question is not currently being used (e.g., power is not connected to it). Thus, an entity described or recited as “configured to” perform some task refers to something physical, such as a device, circuit, memory storing program instructions executable to implement the task, etc. This phrase is not used herein to refer to something intangible.
The term “configured to” is not intended to mean “configurable to.” An unprogrammed FPGA, for example, would not be considered to be “configured to” perform some specific function, although it may be “configurable to” perform that function. After appropriate programming, the FPGA may then be configured to perform that function.
Reciting in the appended claims that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. § 112(f) for that claim element. Accordingly, none of the claims in this application as filed are intended to be interpreted as having means-plus-function elements. Should Applicant wish to invoke Section 112(f) during prosecution, it will recite claim elements using the “means for” [performing a function] construct.
As used herein, the term “based on” is used to describe one or more factors that affect a determination. This term does not foreclose the possibility that additional factors may affect the determination. That is, a determination may be solely based on specified factors or based on the specified factors as well as other, unspecified factors. Consider the phrase “determine A based on B.” This phrase specifies that B is a factor is used to determine A or that affects the determination of A. This phrase does not foreclose that the determination of A may also be based on some other factor, such as C. This phrase is also intended to cover an embodiment in which A is determined based solely on B. As used herein, the phrase “based on” is synonymous with the phrase “based at least in part on.”
This disclosure initially describes, with reference to
PMU 120 may be configured to initiate any of various appropriate corrective actions in response to detecting voltage situations via sensor(s) 130. Adjusting the frequency of adjustable clock circuitry 110 is discussed herein to facilitate explanation of some embodiments, but is not intended to limit the scope of the present disclosure. Other corrective actions include clock gating or powering down portions of processing element(s) 140, adjusting one or more parameters of a voltage supply, etc.
Sensor(s) 130 may include one or more filters to detect particular types of voltage fluctuations (e.g., high-pass filters to detect transients and low-pass filters to detect longer-term voltage droops under high current loads). More detailed exemplary sensor embodiments are discussed below with reference to
Processing element(s) 140, in some embodiments, are configured to perform various operations, e.g., based on execution of program instructions. Processing element(s) 140 may include central processing units (CPUs), graphics processors, wireless communication elements (e.g., cellular radios or WLAN radios), display elements, etc. Unused circuitry for a given workload or task may be clock gated or powered down during operation of other circuitry. Therefore, the current load imposed on the power supply of device 100 may vary significantly based on the set of processing element(s) 140 that is currently operating and the frequencies at which it these processing elements are clocked.
Adjustable clock circuitry 110, in some embodiments, is configured to perform rapid, open-loop downshifting to decrease its output frequency in response to control signaling from PMU 120. U.S. patent application Ser. No. 15/146,374, filed May 4, 2016, which is incorporated by reference herein in its entirety, discusses various implementations of asynchronous shift circuitry configured to adjust the output frequency of an oscillator in response to control signals. Any of these techniques may be implemented by circuitry disclosed herein, among others.
The PMU 120 may or may not be located on the same integrated circuit as the other elements of device 100. Further, sensor(s) 130 may be located in one or more of various locations, including other elements of device 100 (not shown). In some cases, other integrated circuit paths may be configured to translate sensor events into clock frequency downshifts without using PMU 120. PMU 120 is shown as one example of control circuitry but is not intended to limit the scope of the present disclosure.
As used herein, the term “load release event” is intended to be construed according to well-understood meaning in the art, which includes a rapid decrease on a current load on a power supply relative to the power supply's ability to adjust its output power, causing a sudden increase in supply voltage. Load release events may be caused by clock gating, a memory stall, or powering down a component, for example, which quickly reduces the current load, or due to other short-term variations in active current consumption. This is a high-frequency event, in various embodiments, e.g., when a high-frequency clock is suddenly gated on a particular clock edge. In the illustrated embodiment, the current load may return shortly after the load release event, such as when a memory stall has been cleared causing the voltage to return to a substantially low DC value after the event.
In the illustrated example, the positive increase in supply voltage caused by the load release is followed by a high-frequency ringing 340 in supply voltage that leads to a decrease in supply voltage (that undershoots below the level prior to the increase) that is a result of the load release. As used herein, the term “ringing” is intended to be construed according to its well-understood meaning in the art, which includes the high-frequency response of a signal that results from a high-frequency increase in the signal in the other direction. This may be caused by resonance in capacitance and inductance in the power delivery network, such that a high-frequency positive perturbation results in an opposite negative perturbation. Because the device is under high current load prior to the load release event and the voltage has drooped, the undershoot corresponding to ringing 340 may correspond to the worst-case supply voltage of the device. Therefore, reducing or eliminating the ringing subsequent to a load release may prevent damage to the device and/or may allow for reductions in voltage margins.
Therefore, in some embodiments, device 100 is configured to detect load release event 330 and initiate a corrective action to increase cycle time for circuitry powered by the supply voltage and/or control the resulting ringing and undershoot in supply voltage. In some embodiments, the corrective action is reduction in frequency of adjustable clock circuitry 110, which is performed quickly enough that the circuitry clock by adjustable clock circuitry 110 begins drawing less current (relative to operation at the previous frequency) prior to the ringing. This may reduce the downward transient in the supply voltage, in some embodiments. In some situations or embodiments, the reduction in frequency of adjustable clock circuitry 110 simply gives more time to critical paths contained within processing elements 140, allowing for improved operating margins while in other situations the magnitude of the downward transient may also be reduced.
In some embodiments, a high-pass analog voltage sensor or a slope detector is used to detect one or more of the supply voltage events of
Although a load release event is discussed herein for purposes of explanation, similar techniques may be used for other types of events. For example, high dV/dt voltage transients in either the positive or negative direction that are not caused by a load release may be similarly detected and handled. In the illustrated embodiment, a second step up in current demand 370 subsequent to the load release event keeps the supply voltage in
In some embodiments, high-pass filter 420 is configured to pass relatively high-frequency changes in supply voltage, e.g., for droop events 310 and 320 of
Level-sense modules 440 may be implemented using any of various appropriate circuitry. In the illustrated embodiment, the threshold level sensed by a given module 440 is programmable using one of level control signals 450A-450N. By programming the reference levels, sensor complex 400 may be programmed to detect various different supply voltage events or combinations of events.
In some embodiments, high-pass filter 425 and level-sense module 440C are configured to detect load release event 330 and trigger 460C indicates that a potential load-release 430 has been detected. The cutoff frequency for high-pass filters 420 and 425 may be the same or may be different, depending on the types of events that these filters are configured to pass (and may be programmable).
In some embodiments, low-pass filter 430 is configured to remove high-frequency excursions of the supply voltage and trigger 460N indicates whether a longer-term voltage droop (e.g., the droop leading up to load release 330) is detected.
In some embodiments, control circuitry is configured to determine whether to initiate a corrective action based on detecting an appropriate combination of trigger assertions over time. For example, control circuitry may initiate a corrective action in response to a trigger corresponding to event 310, followed by a trigger corresponding to event 320, a trigger indicating a low voltage over a longer time interval, and a trigger corresponding to load release event 330. In other situations, any of various combinations of events or states may be detected. In these embodiments, the combination of multiple different sensors and/or triggers may reduce false positives so that corrective actions are not taken unnecessarily when a worst-case load release event is not actually a possibility, while ensuring that corrective action is taken when voltage margins are in fact reduced.
In various embodiments, detecting the load release and initiating a corrective action prior to the end of the voltage spike caused by the load release may eliminate or reduce the amount of ringing subsequent to the load release. Note that device 100 may also initiate other corrective actions prior to the load release event. For example, PMU 120 and/or adjustable clock circuitry 110 may reduce clock frequency in response to initial droop event 310 to reduce the magnitude of the second droop event 320. In some embodiments, the corrective action for the load release event may correspond to an even further reduction in frequency. In these embodiments, adjustable clock circuitry 110 is configured to generate output clock signals at multiple different frequency levels, e.g., based on control signaling from PMU 120. In other embodiments, control signaling for adjustable clock circuitry 110 may be generated by one or more other circuit elements in addition to or in place of PMU 120, including sensor(s) 130, sensor 134, or sensor block 400, for example.
Control unit 530, in some embodiments, is configured to initiate corrective actions in response to detection of supply voltage events. For example, control unit 530 may reduce the frequency of adjustable clock circuitry 110 in response to a reduction in supply voltage. In some embodiments, control unit 530 is configured to control adjustable clock circuitry 110 at multiple different frequencies in response to different supply voltage characteristics (e.g., based on detecting different supply voltage levels).
In some embodiments, control unit 530 is configured to detect change in supply voltage based on comparator outputs over multiple cycles.
In the illustrated embodiment, detector 600 also includes a noisy VDD detector portion 670. In some embodiments, detector portion 670 includes replicas of the delay elements in VCO 610, which are also controlled by common control voltage 630. The delay elements in detector portion 670, however, are powered by the noisy VDD supply 640. In the illustrated embodiment, detector portion 670 includes phase comparison circuitry 650 and feedback control circuitry 660 that are configured to determine difference in phase between the outputs of the two sets of delay elements.
In the illustrated embodiment, detector 600 is configured to detect certain conditions in the noisy VDD supply 640 based on phase difference detected by phase comparison circuitry 650. In the illustrated embodiment, MUX 695 is configured to provide either (1) the PLL output 675 to the delay elements of portion 670 or (2) detector output 685 to the input of these delay elements.
When the delay elements in portion 670 are receiving the PLL output signal 675, the phases between PLL output 675 and detector output 685 should be similar if the supply voltages 620 and 640 are similar and control voltage 630 is common, in embodiments in which the delay elements in 620 and 640 are matched. Therefore, phase comparison circuitry 650, in some embodiments, is configured to detect supply voltage perturbations in noisy VDD supply 640 relative to the quiet supply voltage 620 based on difference between the phases of these two signals. Comparison circuitry 650 may compare the difference in phase divided by N, where N is the number of delay elements. The phase difference may correspond to the magnitude and/or rate of changes in noisy VDD supply 640 and may be used to detect various supply voltage events such as load release event 330, for example. Feedback control circuitry 660 may allow for long term differences between the two loops to be compensated for such that detector 670 may be running at the same frequency and constant phase with respect to PLL VCO 610 when the supply is quiet, and only when there are significant noise events will phase comparison 650 show a difference between the phase position. In some embodiments the frequency response of detector 670 is tuned through feedback control 660 in order to achieve the balance of tracking between the two loops and sensitivity to noise signals.
In some embodiments, periodically, after MUX 695 has provided an edge from detector output 685, feedback control circuitry 660 is reconfigured to control MUX 695 to provide signals from PLL output signal 675 for multiple passes through the VCO cycle. This may be used to improve resolution of the detector by integrating any differences over the multiple passes to determine the difference in delay between PLL output 675 and detector output 685. For an iteration through “i” VCO cycles, the resolution may become the phase divided by (i times N). In these embodiments, after an event is detected, the detector may be reset by injecting a new edge from PLL output 675. This injection may help to maintain tracking between the two loops. The injection may occur every cycle, every other cycle, some other number of cycles, or a programmable number of cycles in various embodiments. In other embodiments, feedback control circuitry 660, MUX 695, and the feedback loop for detector output 685 may be omitted.
Sensors 400, 500, and 600 are included for purposes of illustration but are not intended to limit the scope of the present disclosure. In other embodiments, any of various appropriate sensors may be used in conjunction with and/or in place of disclosed sensors. In some embodiments, using different types of sensors for different supply voltage events may improve overall detection accuracy.
In some embodiments, the transients in mode B can be greatly reduced by detecting steep slopes in the supply voltage (e.g., using one or more of the various sensors discussed above) and through migration by rapidly adjusting the frequency of adjustable clock circuitry 110, e.g., using the techniques discussed above and in U.S. patent application Ser. No. 15/146,374. In some embodiments, the combination of the adjustable clock circuitry 110 for high-frequency and mid-frequency transients and the low load line mode of power supply 730 for low frequency voltage changes may increase average supply voltage while reducing transients. In particular, in embodiments in which the ringing 340 subsequent to load release event 330 is detected and reduced, the combination of the low load line mode and the adjustable clock circuitry 110 may significantly improve the worst-case supply voltage of the device which may allow reduced voltage margins in a circuit design. In some embodiments the entire voltage setting may be reduced because of the reduced impact from high current droop (due to reduced load line) without affecting the minimum voltage the critical paths will experience. As discussed above, in some embodiments adjustable clock circuitry 110 mitigates the effect of high frequency noise (e.g., by providing more cycle time on the critical path) without actually reducing high-frequency noise. In these embodiments, the combination of low load line mode and adjustable clock circuitry 110 may also allow reduced voltage margins, e.g., because the low load line mode reduces the magnitude of long-term voltage droops while the adjustable clock circuitry 110 mitigates the effects of high-frequency transients.
In some embodiments, PMU 120 or another processing element is configured to adjust the frequency of adjustable clock circuitry 110 based on tracking the supply voltage. This may be particularly useful in cost-reduced or space constrained systems with low bypass capacitance or a PMU which is not sized for peak current behavior. In such systems, the supply voltage waveform may have a triangle or sine-wave behavior. By tracking the supply voltage over time, control circuitry may be configured to upshift or downshift the frequency of adjustable clock circuitry 110 in order to reduce the magnitude of the droop in the power supply. In these embodiments it may be important to detect the case where the supply voltage begins dropping and to ensure that the clock frequency is reduced in time. In some embodiments, the wave behavior of the supply voltage may be reduced using these techniques.
In other embodiments, the techniques of
At 910, in the illustrated embodiment, one or more sensors monitor a supply voltage from a power supply. The supply voltage may be directly supplied by the power supply or may be a derivation based on the power supply output. The monitoring may occur using multiple sensors which may be placed at multiple locations across a semiconductor device. The monitoring may be performed using multiple different types of sensors, which may include one or more types disclosed herein. Note that although various sensors herein are configured to measure voltage characteristics, other types of sensors may be used to determine voltage characteristics indirectly (e.g., using current sensors, etc.).
At 920, in the illustrated embodiment, control circuitry (e.g., PMU 120) detects a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In other embodiments, similar techniques may be used to detect a droop event that includes a decrease in supply voltage that meets one or more pre-determined threshold parameters. In various embodiments, the parameters may include one or more threshold rates of change of the supply voltage. The parameters may include a magnitude of the decrease/increase, a value of the supply voltage prior to the increase, and/or a value of the supply voltage subsequent to the decrease/increase. The parameters may include one or more previous events (e.g., events 310 and/or 320) that should be detected before PMU 120 will determine that a load release event has occurred.
At 930, in the illustrated embodiment, control circuitry initiates a corrective action to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval. In the illustrated embodiment, the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. Said another way, the ringing of the supply voltage occurs during the time interval in which clock cycle time is increased, although the time interval during which the clock cycle is adjusted may extend beyond the ringing. This may avoid logic errors on one or more critical paths, for example, by providing circuitry with extra time in each clock cycle to perform operations when the circuitry is receiving a lower supply voltage.
In some embodiments, the corrective action may also reduce or control the ringing. For example, circuitry may have lower switching power consumption when the clock cycle time is increased. Controlling the ringing may include reducing the amount of the undershoot (relative to amount of the undershoot that would have occurred without the corrective action) or even eliminating the ringing. This may improve the worst-case supply voltage of device 100 which may allow for reduced voltage margins and lower overall power consumption, for example.
In some embodiments, the corrective action is a rapid decrease in clock frequency by adjustable clock circuitry 110. In other embodiments, any of various corrective actions may be implemented in conjunction with or in place of reduction in clock frequency.
Referring now to
Fabric 1010 may include various interconnects, buses, MUX's, controllers, etc., and may be configured to facilitate communication between various elements of device 1000. In some embodiments, portions of fabric 1010 may be configured to implement various different communication protocols. In other embodiments, fabric 1010 may implement a single communication protocol and elements coupled to fabric 1010 may convert from the single communication protocol to other communication protocols internally.
In the illustrated embodiment, compute complex 1020 includes bus interface unit (BIU) 1025, cache 1030, and cores 1035 and 1040. In various embodiments, compute complex 1020 may include various numbers of processors, processor cores and/or caches. For example, compute complex 1020 may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache 1030 is a set associative L2 cache. In some embodiments, cores 1035 and/or 1040 may include internal instruction and/or data caches. In some embodiments, a coherency unit (not shown) in fabric 1010, cache 1030, or elsewhere in device 1000 may be configured to maintain coherency between various caches of device 1000. BIU 1025 may be configured to manage communication between compute complex 1020 and other elements of device 1000. Processor cores such as cores 1035 and 1040 may be configured to execute instructions of a particular instruction set architecture (ISA) which may include operating system instructions and user application instructions.
Cache/memory controller 1045 may be configured to manage transfer of data between fabric 1010 and one or more caches and/or memories. For example, cache/memory controller 1045 may be coupled to an L3 cache, which may in turn be coupled to a system memory. In other embodiments, cache/memory controller 1045 may be directly coupled to a memory. In some embodiments, cache/memory controller 1045 may include one or more internal caches.
As used herein, the term “coupled to” may indicate one or more connections between elements, and a coupling may include intervening elements. For example, in
Graphics unit 1050 may include one or more processors and/or one or more graphics processing units (GPU's). Graphics unit 1050 may receive graphics-oriented instructions, such as OPENGL®, Metal, or DIRECT3D® instructions, for example. Graphics unit 1050 may execute specialized GPU instructions or perform other operations based on the received graphics-oriented instructions. Graphics unit 1050 may generally be configured to process large blocks of data in parallel and may build images in a frame buffer for output to a display. Graphics unit 1050 may include transform, lighting, triangle, and/or rendering engines in one or more graphics processing pipelines. Graphics unit 1050 may output pixel information for display images. In the some embodiments, graphics unit 1050 includes a programmable shader core.
Display unit 1065 may be configured to read data from a frame buffer and provide a stream of pixel values for display. Display unit 1065 may be configured as a display pipeline in some embodiments. Additionally, display unit 1065 may be configured to blend multiple frames to produce an output frame. Further, display unit 1065 may include one or more interfaces (e.g., MIPI® or embedded display port (eDP)) for coupling to a user display (e.g., a touchscreen or an external display).
I/O bridge 1080 may include various elements configured to implement: universal serial bus (USB) communications, security, audio, and/or low-power always-on functionality, for example. I/O bridge 1080 may also include interfaces such as pulse-width modulation (PWM), general-purpose input/output (GPIO), serial peripheral interface (SPI), and/or inter-integrated circuit (I2C), for example. Various types of peripherals and devices may be coupled to device 1000 via I/O bridge 1080.
In some embodiments, various elements of device 1000 are powered by power supply 710 and/or clocked by adjustable clock circuitry 110. The disclosed techniques may reduce switching power consumption in device 1000, prevent damage to components of device 1000, etc.
The present disclosure has described various exemplary circuits in detail above. It is intended that the present disclosure cover not only embodiments that include such circuitry, but also a computer-readable storage medium that includes design information that specifies such circuitry. Accordingly, the present disclosure is intended to support claims that cover not only an apparatus that includes the disclosed circuitry, but also a storage medium that specifies the circuitry in a format that is recognized by a fabrication system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuitry. Claims to such a storage medium are intended to cover, for example, an entity that produces a circuit design, but does not itself fabricate the design.
Non-transitory computer-readable medium 1110, may comprise any of various appropriate types of memory devices or storage devices. Medium 1110 may be an installation medium, e.g., a CD-ROM, floppy disks, or tape device; a computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory such as a Flash, magnetic media, e.g., a hard drive, or optical storage; registers, or other similar types of memory elements, etc. Medium 1110 may include other types of non-transitory memory as well or combinations thereof. Medium 1110 may include two or more memory mediums which may reside in different locations, e.g., in different computer systems that are connected over a network.
Design information 1115 may be specified using any of various appropriate computer languages, including hardware description languages such as, without limitation: VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1115 may be usable by semiconductor fabrication system 1120 to fabrication at least a portion of integrated circuit 1130. The format of design information 1115 may be recognized by at least one semiconductor fabrication system 1120. In some embodiments, design information 1115 may also include one or more cell libraries which specify the synthesis and/or layout of integrated circuit 1130. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies cell library elements and their connectivity.
Semiconductor fabrication system 1120 may include any of various appropriate elements configured to fabricate integrated circuits. This may include, for example, elements for depositing semiconductor materials (e.g., on a wafer, which may include masking), removing materials, altering the shape of deposited materials, modifying materials (e.g., by doping materials or modifying dielectric constants using ultraviolet processing), etc. Semiconductor fabrication system 1120 may also be configured to perform various testing of fabricated circuits for correct operation.
In various embodiments, integrated circuit 1130 is configured to operate according to a circuit design specified by design information 1115, which may include performing any of the functionality described herein. For example, integrated circuit 1130 may include any of various elements shown in
As used herein, a phrase of the form “design information that specifies a design of a circuit configured to . . . ” does not imply that the circuit in question must be fabricated in order for the element to be met. Rather, this phrase indicates that the design information describes a circuit that, upon being fabricated, will be configured to perform the indicated actions or will include the specified components.
Although specific embodiments have been described above, these embodiments are not intended to limit the scope of the present disclosure, even where only a single embodiment is described with respect to a particular feature. Examples of features provided in the disclosure are intended to be illustrative rather than restrictive unless stated otherwise. The above description is intended to cover such alternatives, modifications, and equivalents as would be apparent to a person skilled in the art having the benefit of this disclosure.
The scope of the present disclosure includes any feature or combination of features disclosed herein (either explicitly or implicitly), or any generalization thereof, whether or not it mitigates any or all of the problems addressed herein. Accordingly, new claims may be formulated during prosecution of this application (or an application claiming priority thereto) to any such combination of features. In particular, with reference to the appended claims, features from dependent claims may be combined with those of the independent claims and features from respective independent claims may be combined in any appropriate manner and not merely in the specific combinations enumerated in the appended claims.
This application is a continuation of U.S. application Ser. No. 15/419,218, filed Jan. 30, 2017 (now U.S. Pat. No. 10,581,440), which claims priority to U.S. Provisional Appl. No. 62/395,801, filed Sep. 16, 2016; the disclosures of each of the above-referenced applications are incorporated by reference herein in their entireties.
| Number | Date | Country | |
|---|---|---|---|
| 62395801 | Sep 2016 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 15419218 | Jan 2017 | US |
| Child | 16803861 | US |
