Patent Grant
11210979
This application claims the benefit of and priority to Chinese Patent Application No. 2019/11331000.9, filed on Dec. 20, 2019, the contents of which being incorporated by reference in their entirety herein.
The present disclosure relates to the field of display technology and, in particular, to a detection circuit, an array substrate and detection method, electronic paper, and a detection tool using the same.
Electronic paper is an electronic display similar to paper. Electronic paper can not only bring the same comfortable visual display as paper, but also realize a display function of a common display. Electronic paper has an array substrate like a common display, and signal lines, such as gate lines, data lines and the like, are integrated on the array substrate. When compared to electronic paper having a rigid array substrate, signal lines on the electronic paper having a flexible array substrate are prone to breakage, and have other defects due to thermal shrinkage of substrate material, etc., resulting in a decrease in the yield of the electronic paper.
It should be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to those of ordinary skill in the art.
According to a first aspect of the present disclosure, there is provided a detection circuit for detecting a plurality of first signal lines of an array substrate, wherein the detection circuit includes:
a first input circuit having a plurality of first switch units, each of the plurality of first switch units being disposed in a one-to-one correspondence with a corresponding one of the plurality of first signal lines, a first terminal of each of the plurality of first switch units being connected to a first power signal terminal, a second terminal of each of the plurality of first switch units being connected to a first terminal of a corresponding first signal line, and a control terminal of each of the plurality of first switch units being connected to a first control signal terminal; and
a first output circuit having a plurality of second switch units connected in cascade, each of the plurality of second switch units being disposed in a one-to-one correspondence with a corresponding one of the plurality of first signal lines, a second terminal of the second switch unit in a previous stage being connected to a first terminal of the second switch unit in the next adjacent stage, a control terminal of each of the plurality of second switch units being connected to a second terminal of a corresponding first signal lines, and the first terminal of the second switch unit of a first stage being connected to the second terminal of the corresponding first signal lines, the second terminal of the second switch unit of a last stage being connected to a first detection terminal.
According to a second aspect of the present disclosure, there is provided an array substrate, said array substrate includes the detection circuit mentioned above.
According to a third aspect of the present disclosure, there is provided an array substrate detection method for detecting the array substrate mentioned above, wherein the method includes:
inputting a valid level signal into the first control signal terminal, so as to turn on each of the plurality of first switch units;
inputting the valid level signal into the first power signal terminal; and
detecting a level state of the first detecting terminal, and determining whether any one of the plurality of first signal lines is broken according to the level state of the first detection terminal,
wherein in the case of the detected level state of the first detecting terminal is a signal with a valid level, it is determined that none of the plurality of first signal lines is broken, and in the case of the detected level state of the first detecting terminal is a signal with an invalid level, it is determined that at least some of the first signal lines are broken.
According to a fourth aspect of the present disclosure, there is provided an electronic paper comprising the array substrate mentioned above.
According to a fifth aspect of the present disclosure, there is provided a detection tool, which includes:
a first NAND gate having a first input terminal being connected to a high-level signal terminal and the second input terminal being connected to a first detection terminal; and
a first light-emitting unit configured being connected between an output terminal of the first NAND gate and a ground terminal,
wherein the first detection terminal is connected to a second terminal of a second switch unit of a last stage of cascaded multiple second switch units of a detection circuit, and the detection circuit comprising:
According to a sixth aspect of the present disclosure, there is provided a detection tool, which includes:
a first NOR gate having a first input terminal being connected to a low-level signal terminal and the second input terminal being connected to a first detection terminal; and
a third light-emitting unit configured being connected between a output terminal of the first NOR gate and a high-level signal terminal,
wherein the first detection terminal is connected to a second terminal of a second switch unit of a last stage of cascaded multiple second switch units of a detection circuit, and the detection circuit comprising:
It is to be understood that the above general description and the detailed description below are merely exemplary and explanatory, and do not limit the present disclosure.
The accompanying drawings herein are incorporated in and constitute a part of this specification, illustrate embodiments conforming to the present disclosure and, together with the description, serve to explain the principles of the present disclosure. Understandably, the accompanying drawings in the following description show merely some embodiments of the present disclosure, and persons of ordinary skill in the art may still derive other drawings from these accompanying drawings without creative efforts.
Example embodiments will now be described more fully with reference to the accompanying drawings. However, the embodiments can be implemented in a variety of forms and should not be construed as being limited to the examples set forth herein. Rather, these embodiments are provided so that this disclosure will be more complete so as to convey the idea of the exemplary embodiments to those skilled in this art. The same reference numerals in the drawings denote the same or similar parts, and the detailed description thereof will be omitted.
Although relative terms such as “upper” and “lower” are used in the specification of the present disclosure to describe the relationships of one component relative to another component, these terms are used in this specification to be illustrative of the present disclosure, for example, the direction of the example described the accompanying drawings. It will be understood that if the device is upside down, an “upper” component described above will become a “lower” component. When a structure is “on” another structure, it is possible that the structure is integrally formed on another structure, or that the structure is “directly” disposed on another structure, or the structure is “indirectly” disposed on another structure through other structure.
In the present specification, terms “a,” “an,” “the,” “said,” and “at least one of” are used to denote the presence of one or more elements, constituent parts, etc. Terms “comprising,” “including,” and “having” represent open including and refer to additional elements, constituent parts, etc. in addition to the listed elements, constituent parts, etc.
An embodiment of the present disclosure first provides a detection circuit. A schematic structural diagram of an exemplary embodiment of the detection circuit of the present disclosure is shown in
In the detection circuit provided by this exemplary embodiment, each of the first switch units T1 can be turned on via a valid level inputted to the first control signal terminal CN1, and at the same time, the valid level can be inputted to the first power signal terminal V1. When all of the first signal lines L1 do not break, i.e. are connected, all of the second switch units T2 are turned on, so a valid level is detected at the first detection terminal TS1. When any one of the first signal lines breaks, the second switch unit corresponding to the broken first signal line is turned off, so an invalid level is detected at the first detection terminal TS1. Therefore, the present exemplary embodiment can determine whether any one of the first signal lines L1 is broken by detecting the level of the first detection terminal TS1.
In this exemplary embodiment, a schematic structural diagram of another exemplary embodiment of the detection circuit of the present disclosure is shown in
The second output circuit 22 includes a plurality of fourth switch units T4 connected in cascade. Each of the fourth switch units T4 is disposed in a one-to-one correspondence with a corresponding one of the plurality of second signal lines L2, a second terminal of the fourth switch unit T4 in a previous stage is connected to a first terminal of the fourth switch unit T4 in the next adjacent stage, and a control terminal of each of the plurality of fourth switch units T4 is connected to a second terminal of a corresponding one of the plurality of second signal lines L2. Furthermore, the first terminal of the fourth switch unit T4 of the first stage is connected to the second terminal of the corresponding one of the plurality of second signal lines L2, and the second terminal of the fourth switch unit T4 of the last stage is connected to a second detection terminal TS2.
In the detection circuit provided by this exemplary embodiment, each of the third switch units T3 can be turned on via a valid level inputted to the second control signal terminal CN2, and at the same time, the valid level can be inputted to the second power signal terminal V2. When all of the second signal lines L2 do not break, i.e. in a connect state, all of the fourth switch units T4 are turned on, so a valid level is detected at the second detection terminal TS2. When any one of the first signal lines breaks, the fourth switch unit corresponding to the broken second signal line is turned off, so an invalid level is detected at the second detection terminal TS2. Therefore, the present exemplary embodiment can determine whether any one of the second signal line L2 is broken by detecting the level of the second detection terminal TS2.
In this exemplary embodiment, the first signal line may be a gate line, and the second signal line may be a data line. It should be understood that, in other exemplary embodiments, the first signal line may be a data line, and the second signal line may be a gate line. The gate line may include a signal line extending laterally along the array substrate, for example, the gate line may be a signal line configured for providing a gate driving signal to a pixel driving circuit. The data line may include a signal line extending in a column direction of the array substrate, for example, the data line may be a signal line configured for providing a data signal to the pixel driving circuit.
In this exemplary embodiment, as shown in
In this exemplary embodiment, both of the first switch units T1 and the second switch units T2 may be N-type transistors or P-type transistors. When both of first switch units T1 and the second switch units T2 are N-type transistors or P-type transistors, the first control signal terminal CN1 may be shared with the first power signal terminal V1, since the logic levels configured for turning on the first switch units T1 and the second switch units T2 are the same. Similarly, both of the third switch units T3 and the fourth switch units T4 may be N-type transistors or P-type transistors, and the second control signal terminal CN2 may be shared with the second power signal terminal V2, since the logic levels configured for turning on the third switch unit T3 and the fourth switch unit T4 are the same.
The present exemplary embodiment also provides an array substrate, and the array substrate includes the above-mentioned detection circuit.
In this exemplary embodiment, a schematic structural diagram of an exemplary embodiment of an array substrate of the present disclosure is shown in
In this exemplary embodiment, as shown in
In this exemplary embodiment, a circuit structure diagram of a display area in an exemplary embodiment of an array substrate of the present disclosure is shown in
In this exemplary embodiment, as shown in
In this exemplary embodiment, as shown in 3, the array substrate may further include a third probe pad 33 and a fourth probe pad 34. The third probe pad 33 is disposed on the surface of the array substrate and connected to the second power signal terminal V2 and the second control signal terminal CN2. The fourth probe pad 34 is disposed on the surface of the array substrate and connected to the second detection terminal TS2. When the second signal lines L2 need to be detected, a valid level signal can be input to the second power signal terminal V2 and the second control signal terminal CN2 of the detection circuit via the third probe pad 33, so that whether any one of the second signal lines is broken can be determined by a level detection at the fourth probe pad 34. The specific detection method has been described in detail above, and will not be repeated here.
In this exemplary embodiment, the first probe pad 31 may be shared with the third probe pad 33. The first signal lines and the second signal lines can be detected simultaneously. It should be understood that in other exemplary embodiments, the first signal lines L1 and the second signal lines L2 may also be detected separately. In this case, both of the first power signal terminal V1 and the first control signal terminal CN1 may be connected to a probe pad, and both of the second power signal terminal V2 and the second control signal terminal CN2 may be connected to other probe pad. All of these belong to the protection scope of the present disclosure.
A flow diagram of an array substrate detection method for detecting an array substrate is shown in
At step 701, a valid level signal is inputted into a first control signal terminal CN1, so as to turn on each of a plurality of first switch units T1.
At step 702, the valid level signal is inputted into a first power signal terminal V1.
At step 703, a level state of a first detecting terminal TS1 is detected, and a broken state of the plurality of first signal lines L1 is determined according to the level state of the first detection terminal TS1.
In this array substrate detection method, in the case of the detected level state of the first detecting terminal TS1 is a signal having a valid level, it is determined that none of the plurality of first signal lines L1 is broken, and in the case of the detected level state of the first detecting terminal is a signal having an invalid level, it is determined that at least some of the plurality of first signal lines L1 are broken.
A flow diagram of another array substrate detection method for detecting an array substrate is shown in
At step 804, another valid level signal is inputted into a second control signal terminal CN2, so as to turn on each of a plurality of third switch units T3.
At step 805, another valid level signal is inputted into a second power signal terminal V2.
At step 806, a level state of a second detecting terminal TS2 is detected, and a broken state of the plurality of second signal lines L2 is determined according to the level state of the second detection terminal TS2.
In this array substrate detection method, in the case of the detected level state of the second detecting terminal TS2 is a signal having a valid level, it is determined that none of the plurality of second signal lines L2 is broken, and in the case of the detected level state of the second detecting terminal TS2 is a signal having an invalid level, it is determined that at least some of the plurality of second signal lines L2 are broken. The valid level signal may be the same as the other valid level signal or may be different from the other valid level signal.
The above content of the detection method has been described in detail, and will not be repeated here.
The present exemplary embodiment also provides an electronic paper including the above array substrate.
The electronic paper has the same technical characteristics and working principles as the above-mentioned array substrate. The above content has been described in detail and will not be repeated here.
The present exemplary embodiment also provides a detection tool. A schematic structural diagram of an exemplary embodiment of the detection tool of the present disclosure is shown in
In this exemplary embodiment, as shown in
A schematic structural diagram of an exemplary embodiment of another detection tool of the present disclosure is shown in
In this exemplary embodiment, as shown in
The purpose of the present disclosure is to provide a detection circuit, an array substrate and detection method, electronic paper and a detection tool using the same. The detection circuit can detect a broken state of signal lines in the electronic paper, thereby solving the technical problem of low degree of yield rate (i.e. accept rate of good products) of the electronic paper in the related art.
The present disclosure provides a detection circuit, an array substrate and detection method, electronic paper, and a detection tool using the same. The detection circuit is configured to detect a plurality of first signal lines of an array substrate, wherein the detection circuit includes a first input circuit and a second input circuit. The first input circuit have a plurality of first switch units, each of the plurality of first switch units are disposed in a one-to-one correspondence with a corresponding one of the plurality of first signal lines, a first terminal of each of the plurality of first switch units is connected to a first power signal terminal, a second terminal of each of the plurality of first switch units is connected to a first terminal of a corresponding first signal line, and a control terminal of each of the plurality of first switch units is connected to a first control signal terminal. The first output circuit have a plurality of second switch units connected in cascade, each of the plurality of second switch units is disposed in a one-to-one correspondence with a corresponding one of the plurality of first signal lines, a second terminal of the second switch unit in a previous stage is connected to a first terminal of the second switch unit in the next adjacent stage, a control terminal of each of the plurality of second switch units is connected to a second terminal of a corresponding first signal lines, and the first terminal of the second switch unit of a first stage is connected to the second terminal of the corresponding first signal lines, the second terminal of the second switch unit of a last stage is connected to a first detection terminal.
In the detection circuit provided by this exemplary embodiment, each of the first switch units can be turned on via a valid level inputted to the first control signal terminal, and at the same time, the valid level can be inputted to the first power signal terminal. When all of the first signal lines do not break, i.e. are connected, all of the second switch units are turned on, so a valid level is detected at the first detection terminal. When any one of the first signal lines breaks, the second switch unit corresponding to the broken first signal line is turned off, so an invalid level is detected at the first detection terminal. Therefore, the present exemplary embodiment can determine whether any one of the first signal lines is broken by detecting the level of the first detection terminal.
Those skilled in the art will readily contemplate other embodiments of the present disclosure after considering the specification and practicing the disclosure. The present disclosure is intended to cover any variations, uses, or adaptive changes of the present disclosure. These variations, uses, or adaptive changes follow the general principles of the present disclosure and include the common general knowledge or conventional technical means in this art which is not described herein. The specification and examples should be considered as exemplary only, and the true scope and spirit of the disclosure should be defined by the appended claims.
It should be understood that the present disclosure is not limited to the precise structure that has been described above and shown in the drawings, and various modifications and changes can be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 201911331000.9 | Dec 2019 | CN | national |
| Number | Name | Date | Kind |
|---|---|---|---|
| 20020075419 | Kwon | Jun 2002 | A1 |
| 20150077753 | Ji | Mar 2015 | A1 |
| 20180350285 | Goto | Dec 2018 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20210192997 A1 | Jun 2021 | US |
