Claims
- 1. A cache comprising:
an associative memory having a plurality of entries, each of said plurality of entries configured to store a cache line of data, said plurality of entries arranged in a plurality of ways; and a replacement circuit configured to select an entry of said associative memory for eviction responsive to a cache miss by a memory transaction, and wherein said replacement circuit is configured, responsive to a first transaction specifying an explicit update of said replacement circuit to select a first way of said plurality of ways, to establish a first state corresponding to a selection of said first way.
- 2. The cache as recited in claim 1 wherein said replacement circuit employs a pseudo-random replacement policy.
- 3. The cache as recited in claim 2 wherein said replacement circuit comprises:
a control circuit coupled to receive a signal indicative of said first transaction; and a register coupled to said control circuit and configured to store a state of said replacement circuit; wherein said control circuit is configured to cause said register to store a predetermined value representing said first state responsive to said signal.
- 4. The cache as recited in claim 3 wherein said register comprises a linear feedback shift register.
- 5. The cache as recited in claim 4 wherein said control circuit is coupled to receive a second signal indicative of a memory transaction, and wherein said control circuit is configured to cause said register to shift and establish a new state responsive to said second signal.
- 6. The cache as recited in claim 3 wherein said control circuit is coupled to receive an indication of said first way, and wherein said control circuit is configured to select said predetermined value from a plurality of predetermined values responsive to said indication.
- 7. The cache as recited in claim 3 wherein said control circuit is coupled to receive a second signal indicative of a memory transaction, and wherein said control circuit is configured to change said state in said register responsive to said second signal.
- 8-26. (Canceled)
PRIORITY INFORMATION
[0001] This application is a continuation of and claims priority to U.S. patent application having an application Ser. No. 09/633,690, filed 08/07/2000, which application is hereby incorporated by reference.
Continuations (1)
|
Number |
Date |
Country |
Parent |
09633690 |
Aug 2000 |
US |
Child |
10861638 |
Jun 2004 |
US |