with special data handling

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G06F12/126

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/126with special data handling

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Scoreboard for register data cache
- Patent number 12,360,899
- Issue date Jul 15, 2025
- Apple Inc.
- Winnie W. Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and memory system
- Patent number 12,346,260
- Issue date Jul 1, 2025
- Kioxia Corporation
- Tomoya Suzuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache management using groups partitioning
- Patent number 12,339,784
- Issue date Jun 24, 2025
- Mellanox Technologies, Ltd.
- Gal Yefet
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-based system for allocating cache lines to a higher-level...
- Patent number 12,259,820
- Issue date Mar 25, 2025
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Criticality-informed caching policies with multiple criticality levels
- Patent number 12,235,769
- Issue date Feb 25, 2025
- Apple Inc.
- Tyler J. Huberty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parking threads in barrel processor for managing cache eviction req...
- Patent number 12,235,774
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intermediate cache management for non-uniform memory architecture
- Patent number 12,216,590
- Issue date Feb 4, 2025
- Advanced Micro Devices, Inc.
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage device and method for dynamic logical page write ordering
- Patent number 12,210,452
- Issue date Jan 28, 2025
- SanDisk Technologies, Inc.
- Noor Mohamed Aa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for enhancing flash channel utilization
- Patent number 12,197,320
- Issue date Jan 14, 2025
- Microchip Technology Incorporated
- Nima Nikuie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Providing content-aware cache replacement and insertion policies in...
- Patent number 12,182,036
- Issue date Dec 31, 2024
- QUALCOMM Incorporated
- George Patsilaras
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache control to preserve register data
- Patent number 12,182,037
- Issue date Dec 31, 2024
- Apple Inc.
- Jonathan M. Redshaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for transferring data within hierarchical cac...
- Patent number 12,174,753
- Issue date Dec 24, 2024
- ARM Limited
- Joseph Michael Pusdesris
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware architecture of packet cache eviction engine
- Patent number 12,164,439
- Issue date Dec 10, 2024
- Google LLC
- Chandan Muddamsetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
In-memory distributed cache
- Patent number 12,164,432
- Issue date Dec 10, 2024
- Google LLC
- Asa Briggs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-based system for allocating cache lines to a higher-level...
- Patent number 12,093,184
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQ...
- Publication number 20250231887
- Publication date Jul 17, 2025
- Micron Technology, Inc.
- Christopher Baronne
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20250225083
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ERROR INJECTION ARCHITECTURE IN A PROCESSING ENVIRONMENT
- Publication number 20250209003
- Publication date Jun 26, 2025
- Intel Corporation
- Soumya S. Sonnenahalli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE CENTRALIZED ERROR QUEUES IN A PROCESSING ARCHITECTURE
- Publication number 20250209010
- Publication date Jun 26, 2025
- Intel Corporation
- David Puffer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NEW METHOD TO IMPLEMENT SET-ASSOCIATIVE CACHE CONTROLLER
- Publication number 20250209004
- Publication date Jun 26, 2025
- ADVANCED MICRO DEVICES, INC.
- QiuPing Qiu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE CONTROLLER, STORAGE DEVICE, AND STORAGE SYSTEM
- Publication number 20250173275
- Publication date May 29, 2025
- Samsung Electronics Co., Ltd.
- Donggil KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE DEVICE AND A METHOD OF ERROR PROCESSING THEREOF
- Publication number 20250138943
- Publication date May 1, 2025
- Hitachi, Ltd
- Masanori TAKADA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSORS WITH TOGGLEABLE MEMORY TAGGING EXTENSIONS AND RELATED ME...
- Publication number 20250103506
- Publication date Mar 27, 2025
- Ampere Computing LLC
- Bret Leslie Toll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Cache Control to Preserve Register Data
- Publication number 20250094357
- Publication date Mar 20, 2025
- Apple Inc.
- Jonathan M. Redshaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO EVICT TOKENS FROM A KEY VALUE CACHE
- Publication number 20250036876
- Publication date Jan 30, 2025
- Intel Corporation
- Alexander Kozlov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERMEDIATE CACHE MANAGEMENT FOR NON-UNIFORM MEMORY ARCHITECTURE
- Publication number 20240411706
- Publication date Dec 12, 2024
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE REPLACEMENT POLICY STATE STRUCTURE WITH EXTRA STATES FOR PREF...
- Publication number 20240411705
- Publication date Dec 12, 2024
- SiFive, Inc.
- Bradley Gene Burgess
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Hardware Architecture of Packet Cache Eviction Engine
- Publication number 20240403228
- Publication date Dec 5, 2024
- Google LLC
- Chandan Muddamsetty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Data Storage Device and Method for Dynamic Logical Page Write Ordering
- Publication number 20240394182
- Publication date Nov 28, 2024
- Western Digital Technologies, Inc.
- Noor Mohamed AA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address Range Based Memory Hints for Prefetcher, Cache and Memory C...
- Publication number 20240385966
- Publication date Nov 21, 2024
- Google LLC
- Xinliang David Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF...
- Publication number 20240385969
- Publication date Nov 21, 2024
- SK HYNIX INC.
- Sung Woo HYUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-BASED SYSTEM-LEVEL CACHE MANAGEMENT METHOD AND ASSOCIATED EL...
- Publication number 20240370379
- Publication date Nov 7, 2024
- MEDIATEK INC.
- Chun-Ming Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MANAGEMENT USING EVICTION PRIORITY BASED ON MEMORY REUSE
- Publication number 20240303203
- Publication date Sep 12, 2024
- NVIDIA Corporation
- Noam Dor Korem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING

with special data handling

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Scoreboard for register data cache

Memory device and memory system

Cache management using groups partitioning

Methods and apparatus to facilitate atomic operations in victim cache

Victim cache with write miss merging

Write merging on stores with different privilege levels

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Processor-based system for allocating cache lines to a higher-level...

Criticality-informed caching policies with multiple criticality levels

Parking threads in barrel processor for managing cache eviction req...

Intermediate cache management for non-uniform memory architecture

Atomic compare and swap in a coherent cache system

Aggressive write flush scheme for a victim cache

Data storage device and method for dynamic logical page write ordering

Methods and apparatus to reduce bank pressure using aggressive writ...

System and method for enhancing flash channel utilization

Fully pipelined read-modify-write support

Providing content-aware cache replacement and insertion policies in...

Cache control to preserve register data

Methods and apparatus for allocation in a victim cache system

Methods and apparatus for transferring data within hierarchical cac...

Hardware architecture of packet cache eviction engine

In-memory distributed cache

Methods and apparatus for read-modify-write support in multi-banked...

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Methods and apparatus for eviction in dual datapath victim cache sy...

Processor-based system for allocating cache lines to a higher-level...

Methods and apparatus to facilitate read-modify-write support in a...

Patents Applicationslast 30 patents

PARKING THREADS IN BARREL PROCESSOR FOR MANAGING CACHE EVICTION REQ...

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

ERROR INJECTION ARCHITECTURE IN A PROCESSING ENVIRONMENT

SCALABLE CENTRALIZED ERROR QUEUES IN A PROCESSING ARCHITECTURE

NEW METHOD TO IMPLEMENT SET-ASSOCIATIVE CACHE CONTROLLER

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

STORAGE CONTROLLER, STORAGE DEVICE, AND STORAGE SYSTEM

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

STORAGE DEVICE AND A METHOD OF ERROR PROCESSING THEREOF

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

PROCESSORS WITH TOGGLEABLE MEMORY TAGGING EXTENSIONS AND RELATED ME...

Cache Control to Preserve Register Data

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

METHODS AND APPARATUS TO EVICT TOKENS FROM A KEY VALUE CACHE

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

INTERMEDIATE CACHE MANAGEMENT FOR NON-UNIFORM MEMORY ARCHITECTURE

CACHE REPLACEMENT POLICY STATE STRUCTURE WITH EXTRA STATES FOR PREF...

Hardware Architecture of Packet Cache Eviction Engine

Data Storage Device and Method for Dynamic Logical Page Write Ordering

Address Range Based Memory Hints for Prefetcher, Cache and Memory C...

MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF...

MEMORY-BASED SYSTEM-LEVEL CACHE MANAGEMENT METHOD AND ASSOCIATED EL...

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

CACHE MANAGEMENT USING EVICTION PRIORITY BASED ON MEMORY REUSE

VICTIM CACHE WITH WRITE MISS MERGING