Device and a method and mask for forming a device

Abstract

A method of forming a semiconductor device includes patterning a layer stack to form single conductive lines and single landing pads. Patterning of the layer stack includes two lithographic exposures using a set of two different photomasks. The landing pads are arranged at on side of an array region defined by a plurality of conductive lines. A set of photomasks used in the method of forming a semiconductor device includes a first photomask including patterns corresponding to the conductive lines and a second photomask including patterns corresponding to the landing pads. A semiconductor device includes conductive lines and landing pads connected with corresponding ones of said conductive lines wherein the landing pads are arranged in a staggered fashion at one side of an array region defined by a plurality of conductive lines.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate the embodiments of the present invention and together with the description serve to explain the principles of the invention. Other embodiments of the present invention and many of the intended advantages of the present invention will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.

FIGS. 1A and 1B illustrate plan views on conventional devices.

FIG. 2A illustrates a plan view on a memory device with symmetrical landing pads.

FIG. 2B illustrates a plan view on a memory device with asymmetrical landing pads.

FIGS. 3A to 3C illustrate plan views on a plurality of subsets of landing pads according to embodiments of the invention.

FIGS. 4A to 4F illustrate cross-sectional views of the substrate at different processing steps and plan views on the substrate after those processing steps according to an embodiment of the invention.

FIGS. 5A to 5G illustrate cross-sectional views of the substrate at different processing steps and plan views on the substrate after those processing steps according to another embodiment of the invention.

FIG. 6 illustrates a cross-sectional view of the new hard mask.

FIGS. 7A to 7D illustrate cross-sectional views of the substrate at different processing steps using the new hard mask.

FIGS. 8A and B illustrate plan views on the first photomask according to embodiments of the invention.

FIG. 9 illustrates a plan view on the second photomask according to the first photomask of FIGS. 8A and 8B.

FIGS. 10A and 10B illustrate plan views on the first photomask according to other embodiments of the invention.

FIG. 11 illustrates a plan view on the second photomask according to the first photomask of FIGS. 10A and 10B.

FIGS. 12A to 12D illustrate plan views on the first photomask according to yet another embodiment of the invention.

FIG. 13 illustrates a plan view on the second photomask according to the first photomask of FIG. 12D.

FIG. 14 illustrates a plan view on assist structures in the second photomask according to the detail of FIG. 11.

Claims

1. A method of forming a semiconductor device comprising: providing a semiconductor substrate having a surface;providing a layer stack comprising at least one conductive layer on the surface of the substrate; andpatterning the layer stack so as to form single conductive lines and single landing pads, each of the landing pads being connected with a corresponding one of the conductive lines;wherein patterning the layer stack further comprises two lithographic exposures using a set of two different photomasks; andwherein the landing pads are arranged at one side of an array region defined by the plurality of conductive lines.

2. The method of claim 1, wherein patterning the layer stack further comprises: providing a hard mask layer stack on top of the layer stack;patterning the hard mask layer stack so as to form hard mask lines and hard mask pads being arranged at one side of the array region defined by the plurality of lines; andremoving the uncovered portions of the layer stack thereby simultaneously forming single conductive lines and single landing pads.

3. The method of claim 2, wherein patterning the hard mask layer stack further comprises: providing a photoresist layer on top of the hard mask;imaging the conductive lines in a first exposure using a first photomask into the photoresist layer;imaging the landing pads in a second exposure using a second photomask into the same photoresist layer;developing the photoresist layer; andremoving the uncovered portions of the hard mask layer stack thereby forming hard mask lines and hard mask pads.

4. The method of claim 2, wherein patterning the hard mask layer stack further comprises: providing a first photoresist layer on top of the hard mask layer stack;imaging the conductive lines in a first exposure using a first photomask into the first photoresist layer;developing the first photoresist layer;removing the uncovered portions of the hard mask layer stack thereby forming hard mask lines;removing the first photoresist layer from the hard mask layer stack leaving a surface of the substrate with regions covered by the hard mask layer stack and regions with uncovered layer stack;providing a second photoresist layer on top of the surface;imaging the landing pads in a second exposure using a second photomask into the second photoresist layer;developing the second photoresist layer; andremoving the uncovered portions of the hard mask layer stack thereby forming hard mask pads.

5. The method of claim 2, wherein during the patterning the hard mask layer stack hard mask lines corresponding to defined conductive lines are removed.

6. A set of photomasks comprising: a first and a second photomask used in a first and a second lithographic process, respectively;wherein the second lithographic process is performed after the first lithographic process;wherein the first photomask comprises a region with a line/space pattern including interrupting portions so that a pattern transferred into a photoresist material using the first photomask comprises space structures;wherein each of the space structures comprise a first segment of space, a segment of line and a second segment of space, and continuous lines; wherein two adjacent lines are spaced apart from each other by a corresponding space structure, the segment of line of the corresponding space structure connecting the two adjacent lines; andwherein the second photomask comprises a pattern so that a photoresist pattern obtained by the second lithographic process using the second photomask covers a predetermined number of the first segments of spaces and the adjacent portions of the lines entirely and the segments of lines at least partially while leaving the second segments of spaces and the adjacent portions of the lines uncovered.

7. The set of photomasks of claim 6, wherein at least one of the photomasks comprises non-printing assist features.

8. The set of photomasks of claim 6, wherein the interrupting portions in the line/space pattern of the first photomask are arranged in a staggered fashion with respect to the direction of the lines.

9. The set of photomasks of claim 8, wherein the interrupting portions in the line/space pattern are arranged with an increasing distance with respect to a reference position of the line/space pattern, the distance being measured along the direction of the lines.

10. The set of photomasks of claim 8, wherein the line/space pattern of the first photomask is divided in a plurality of subsets of line/space pattern and wherein the interrupting portions in the line/space pattern in each subset are arranged with an increasing distance with respect to a reference position of the line/space pattern, the distance being measured along the direction of the lines.

11. The set of photomasks of claim 10, wherein the interrupting portions in the line/space pattern are arranged symmetrically with respect to a middle line or space of the line/space pattern.

12. The set of photomasks of claim 10, wherein the interrupting portions in the line/space pattern are arranged asymmetrically with respect to a middle line or space of the line/space pattern.

13. The set of photomasks of claim 6, wherein the second photomask comprises a pattern according to the pattern in the first photomask in that way that a photoresist exposed with the second photomask and developed does not cover selected ones of lines obtained by the first lithographic process using the first photomask.

14. A set of photomasks comprising: a first and a second photomask used in a first and a second lithographic process, respectively;wherein the second lithographic process is performed after the first lithographic process;wherein the first photomask comprises a region with a line/space pattern so that a pattern transferred into a photoresist material using the first photomask comprises spaces surrounded by photoresist material separated from each other by lines of photoresist material and extending to different distances with respect to a reference position of the pattern; wherein the distance is measured along the direction of the lines and increases in a direction perpendicular to the direction of the lines; andwherein the second photomask comprises a pattern so that a photoresist pattern obtained by the second lithographic process using the second photomask covers a predetermined number of the lines and spaces and adjacent portions of the surrounding material thus defining pad structures, each of the pad structures being connected with a corresponding one of said lines.

15. The set of photomasks of claim 14, wherein at least one of the photomasks comprises non-printing assist features.

16. The set of photomasks of claim 14, wherein the line/space pattern of the first photomask is divided in a plurality of subsets of line/space patterns so that a pattern transferred into a photoresist material using the first photomask comprises a plurality of subsets comprising spaces surrounded by photoresist material separated from each other by lines of photoresist material and extending to different distances with respect to a reference position of the pattern, the distance being measured along the direction of the lines and increasing in a direction perpendicular to the direction of the lines, in each subset.

17. The set of photomasks of claim 16, wherein the lines and spaces of a subset in the pattern of the first photomask are arranged symmetrically with respect to a middle line or space of said subset.

18. The set of photomasks of claim 16, wherein the lines and spaces of a subset in the pattern of the first photomask are arranged asymmetrically with respect to a middle line or space of said subset.

19. The set of photomasks of claim 14, wherein the second photomask comprises a pattern according to the pattern in the first photomask in that way that a photoresist exposed with the second photomask and developed does not cover selected ones of lines obtained by the first lithographic process using the first photomask.

20. A semiconductor device comprising: a semiconductor substrate having a surface;a plurality of conductive lines running along a first direction, wherein the conductive lines are formed on the surface of the semiconductor substrate; anda plurality of landing pads made of a conductive material, the landing pads being arranged in a staggered fashion with respect to the first direction at one side of an array region defined by the plurality of conductive lines, each of the landing pads being connected with a corresponding one of said conductive lines;wherein the device is obtained by performing a method comprising: providing the semiconductor substrate;providing a layer stack comprising at least one conductive layer on the surface of the substrate;patterning the layer stack so as to form single conductive lines and single landing pads, each of the landing pads being connected with a corresponding one of the conductive lines;wherein patterning the layer stack comprises two lithographic exposures using a set of two different photomasks; andwherein the landing pads are arranged at one side of an array region defined by the plurality of conductive lines in a staggered fashion.

21. The device of claim 20, further comprising: a plurality of second conductive lines running along a second direction, the second direction intersecting the first direction; anda plurality of memory cells, each memory cell being accessable by addressing corresponding ones of said conductive lines and second conductive lines.

22. The device of claim 21, wherein the conductive lines correspond to word or bit lines of the device.

23. The device of claim 20, wherein the landing pads are arranged with an increasing distance with respect to a reference position of the device, the distance being measured along the first direction.

24. The device of claim 20, wherein the landing pads are arranged in a plurality of subsets of landing pads and wherein the landing pads of each subset are arranged with an increasing distance with respect to a reference position of the device, the distance being measured along the first direction.

25. The device of claim 24, wherein the landing pads of each subset are arranged symmetrically with respect to a space between the two conductive lines in the middle of the subset.

26. The device of claim 24, wherein the landing pads of each subset are arranged asymmetrically with respect to a space between the two conductive lines in the middle of the subset.

27. The device of claim 24, wherein the plurality of landing pads comprises first and second subsets of landing pads, the first and second subsets being adjacent to each other and having a first landing pad at the boundary of one subset having the smallest distance with respect to a reference position of the device of the landing pads of one subset, wherein the first landing pad of the first subset of landing pads is arranged at the same distance with respect to a reference position of the device as the first landing pad of the second subset.

28. The device of claim 24, wherein the plurality of landing pads comprises first and second subsets of landing pads, first and second subsets being adjacent to each other and having a first landing pad at the boundary of one subset having the smallest distance with respect to a reference position of the device of the landing pads of one subset, wherein the first landing pad of the first subset of landing pads is arranged at a larger distance with respect to a reference position of the device than the first landing pad of the second subset.

29. The device of claim 28, wherein a space between the first and second landing pad of the second subset of landing pads is provided in that way, that the first landing pad of the first subset of landing pads will reach into this space without contacting or affecting the landing pads of the second subset.

30. A semiconductor device comprising: a semiconductor substrate having a surface;a plurality of conductive lines running along a first direction and formed on the surface of the seminconductor substrate, each of the conductive lines having a line width wl and two neighbouring ones of the conductive lines having a distance ws from each other, the line width and the distance being measured perpendicularly with respect to the first direction, respectively; anda plurality of landing pads made of a conductive material, the landing pads being arranged in a staggered fashion with respect to the first direction at one side of an array region defined by the plurality of conductive lines, each of the landing pads being connected with a corresponding one of said conductive lines, wherein each of said landing pads has a width wp and length lp, the width wp being measured perpendicularly with respect to the first direction, the length lp being measured along the first direction and wherein two landing pads connected to two different neighbouring conductive lines are separated by a space having a distance Is measured along the direction of the conductive lines, wherein the line width wl of each of the conductive lines is equal to the distance ws and wherein ls+lp<10×wl.

31. The device of claim 30, further comprising: a plurality of second conductive lines running along a second direction, the second direction intersecting the first direction, anda plurality of memory cells, each memory cell being accessable by addressing corresponding ones of said conductive lines and second conductive lines.

32. The device of claim 31, wherein the conductive lines correspond to word lines and the second conductive lines correspond to bit lines of the device.

33. The device of claim 30, wherein the landing pads are arranged with an increasing distance with respect to a reference position of the device, the distance being measured along the first direction.

34. The device og claim 30, wherein wl is smaller than 70 nm.

35. The device of claim 30, wherein wp is smaller than 350 nm and lp is smaller than 300 nm.

36. The device of claim 30, wherein the landing pads are arranged in a plurality of subsets of landing pads and wherein the landing pads of each subset are arranged with an increasing distance with respect to a reference position of the device, the distance being measured along the first direction.

37. The device of claim 36, wherein the landing pads of each subset are arranged symmetrically with respect to a space between the two conductive lines in the middle of the subset.

38. The device of claim 36, wherein the landing pads of each subset are arranged asymmetrically with respect to a space between the two conductive lines in the middle of the subset.

39. The device of claim 36, wherein the plurality of landing pads comprises first and second subsets of landing pads, the first and second subsets being adjacent to each other and having a first landing pad at the boundary of one subset having the smallest distance with respect to a reference position of the device of the landing pads of one subset, wherein the first landing pad of the first subset of landing pads is arranged at the same distance with respect to a reference position of the device as the first landing pad of the second subset.

40. The device of claim 36, wherein the plurality of landing pads comprises first and second subsets of landing pads, first and second subsets being adjacent to each other and having a first landing pad at the boundary of one subset having the smallest distance with respect to a reference position of the device of the landing pads of one subset, wherein the first landing pad of the first subset of landing pads is arranged at a larger distance with respect to a reference position of the device than the first landing pad of the second subset.

41. The device of claim 40, wherein a space between the first and second landing pad of the second subset of landing pads is provided in that way, that the first landing pad of the first subset of landing pads will reach into this space without contacting or affecting the landing pads of the second subset.