Patent Application
20050216704
This application claims priority from French Application for Patent No. 04 02929 filed Mar. 22, 2004, the disclosure of which is hereby incorporated by reference.
1. Technical Field of the Invention
The present invention relates in a general manner to the management of a microprocessor instruction set. The invention relates more particularly to a microprocessor, as well as to a method of control of such a microprocessor for modifying the nature of the operations coded by the instructions of this microprocessor's instruction set.
2. Description of Related Art
In RISC (“Reduced Instruction Set Computer”) microprocessors, the variety of instructions is limited by the hardware architecture on account of the fact that the instructions must have a fixed size in terms of number of bits. Because the variety of instructions is limited, the user may need to use several instructions to be able to perform a single operation such as, for example, the copying of a memory page into a register. Such an operation requires, for example, the implementation of a software loop where the microprocessor reads a value at a source address in the memory, copies it to a destination address in the register, then increments the source address and the destination address, and if it has not finished running through all the source addresses in the memory, repeats the execution of the corresponding instructions.
To optimize the speed of execution of this software loop, one could imagine supplementing the microprocessor instruction set with instructions, such as, for example, read and write instructions with post-incrementation or post-decrementation of the pointers which point respectively to the source address and the destination address. This is easily possible within the framework of a microprocessor exhibiting a CISC (“Complex Instruction Set Computer”) architecture but is very difficult to achieve within the framework of an RISC microprocessor on account of its reduced instruction set.
Such a software loop contains five instructions, this being expensive in terms of memory space required to store the program of an application implementing the software loop. Now, it is known that a microprocessor occupies the major part of the time to execute software loops in, generally, performing the same type of specific operation as that described above, for example, where only a few instructions are used.
Moreover, it is known that the higher the number of different instructions of the program, the higher the number of instruction cycles during which the microprocessor is monopolized in respect of processing these instructions. This slows down the time of execution of the program by the microprocessor which therefore often performs the same type of operation.
To alleviate the aforesaid drawbacks of the prior art, the present invention proposes that the variety of instructions of the microprocessor instruction set be increased by configuring (or modifying) the nature of said instructions, in particular by modifying the operations coded by said instructions.
In a general manner, there is provided a register of N mode bits in such a way as to indicate to the microprocessor several modes of execution of the instructions.
The invention thus relates to a microprocessor having a set of determined instructions which are coded on a determined number P of bits in an instruction coding space. The microprocessor comprises a mode register having a determined number N of mode bits. The microprocessor further comprises a decoding unit and an execution unit, which are arranged so as to decode and execute a given instruction according to at least one first or one second mode of execution as a function of the values of a determined number Qi of mode bits associated with the instruction, the said instruction corresponding to distinct respective operations in the said first mode of execution and in the said second mode of execution, where Qi is a strictly positive integer.
The variety of operations coded by the instructions is thus increased without modifying the size in terms of number of bits of the instructions hence the number of distinct instructions of the instruction set. Everything occurs as if the instruction set comprised additional instructions whereas the instruction coding space remains unchanged.
Moreover, by virtue of the invention, the size of the program in terms of memory space required to store it is reduced and the performance of the microprocessor in terms of speed of execution is improved.
Preferably, each mode bit is associated with at most one instruction. Thus, incompatibilities between modes of execution of distinct instructions are avoided.
Advantageously, at least one configuration instruction of the set of instructions makes it possible to write to the mode register by giving the mode bits values corresponding to the mode of execution of the instruction.
In one embodiment, such a configuration instruction is an initialization instruction, that is to say an instruction for setting to the logic value “1”, having as parameter the value of the address of the mode bit to be programmed. Such an instruction having just a single parameter may be coded on a relatively large number of bits in an RISC architecture, allowing a more varied set of instructions.
In this case, another configuration instruction is provided for in the form of a reinitialization instruction, that is to say an instruction for setting to the logic value “0”, having as parameter the value of the address of the mode bit to be programmed.
In another embodiment, the configuration instruction is a load instruction having as parameters the value of the address of the mode bit to be configured and the value (0 or 1) to be given to the said mode bit. A single instruction is therefore sufficient to program a mode bit. Moreover, it is coded on a relatively small number P of bits in an RISC architecture, thereby limiting the number of instructions of the instruction set.
In an embodiment where the invention is particularly advantageous, the microprocessor exhibits an RISC architecture.
Advantageously, the mode register may be internal to the microprocessor. The access times are reduced, thereby speeding up the execution of the programs.
The invention also relates to a method of managing a microprocessor of the type described above, the method comprising a step according to which the execution unit executes a given instruction according to at least one first or one second mode of execution as a function of the values of a determined number Qi of mode bits associated with the instruction, said instruction corresponding to distinct respective operations in said first mode of execution and in said second mode of execution, where Qi is a strictly positive integer.
In accordance with an embodiment of the invention, an apparatus comprises a computation unit for a microprocessor and a register storing at least one mode bit associated with a certain program instruction. A decoding unit is operable to interpret program instructions and control operation of the computation unit according to those instructions, the certain program instruction corresponding to at least two different operations to be performed by the computation unit based on the value of the at least one mode bit.
In accordance with another embodiment, an apparatus comprises a computation unit for a microprocessor having a set of program instructions and a register storing at least one mode bit associated with a certain one of those program instructions. A decoding unit is operable to control the computation unit to execute that certain program instruction in a first mode of execution if the mode bit has a first value and operable to execute that certain program instruction in a second, distinct, mode of execution if the mode bit has a second value.
In accordance with another embodiment, a method for use with a microprocessor having a set of program instructions comprises storing at least one mode bit associated with a certain one of those program instructions. Execution of that certain program instruction is controlled in a first mode of execution if the mode bit has a first value. Execution of that certain program instruction is controlled in a second, distinct, mode of execution if the mode bit has a second value.
Other characteristics and advantages of the invention will become further apparent on reading the description which follows. The latter is purely illustrative and should be read in conjunction with the appended drawings, in which:
With reference to
The execution unit 12 further comprises a data memory 18, such as, for example, registers or/and memories, for storing data specific to the various elementary operations performed such as for example the result of an elementary operation.
The microprocessor 10 comprises a control unit 14 for interpreting the instructions of a program being executed and for controlling the arithmetic and logic unit 16 accordingly.
The control unit 14 comprises for example:
The microprocessor 10 further comprises a mode register 30 of N bits, called mode bits, the mode register 30 being internal or external to the microprocessor 10 and N being a strictly positive integer.
The microprocessor 10 also comprises a bus 32 for reading the values of the mode bits of the mode register 30 and for transmitting the values read to the decoding unit 28.
Each instruction “Ii” is associated with Qi mode bits such as is illustrated in
Thus, the state of the Qi mode bits indicates to the microprocessor 10, in particular to the decoding unit 28, the mode of execution of the instruction “Ii” to be implemented.
For example, as illustrated in
Likewise, the instruction “Ii+1” is associated with the Qi+1 mode bit, that is to say the bit D. The instruction “Ii+1” can thus be executed according to at most 2{circumflex over ( )}1 modes of execution.
Every-thing occurs therefore as if there were additional instructions in the microprocessor instruction set, whereas in reality the number of instructions of the instruction set remains fixed.
Specifically, for a given instruction “Ii” coded on a determined number P of bits in an instruction coding space of size 2{circumflex over ( )}P and associated with a number Qi of mode bits, the instruction set is akin to an instruction set to which 2{circumflex over ( )}Qi−1 instructions have been added. Of course, the maximum number of distinct instructions of the instruction set is in reality still equal to 2{circumflex over ( )}P.
Stated otherwise, the variety of operations coded by each instruction can be increased without thereby increasing the size in terms of number of bits of the said instruction, which must remain fixed within the framework of RISC microprocessors.
To modify the mode of execution of instruction “Ii”, a configuration instruction makes it possible to modify the values of the Qi mode bits associated with the said instruction.
In one embodiment, the programming of the mode bits may be performed via an initialization instruction “SET” and/or a reinitialization instruction “RESET” having the address of the mode bit as value specified as parameter. For example, the initialization instruction sets the state of a mode bit to the logic value “1” and the reinitialization instruction sets the state of the mode bit to the logic value “0”.
In another embodiment, the configuration instruction is a load instruction having as input parameters the address of the mode bit whose state one wishes to modify and the value of the state that one wishes to give it.
Thus, to ascertain the mode of execution of the instruction “11”, the decoding unit 28 is configured in mode register read mode. By way of the bus 32 it reads the values of the Qi mode bits associated with the instruction “Ii” currently being decoded and intended to be executed.
As a function of the values of the Qi mode bits, the decoding unit 28 and the execution unit 12 implement the appropriate mode of execution of the instruction “Ii”. The determined mode of execution is implemented so long as the values of the Qi mode bits remain unchanged.
The selection of the mode bits to be read by the decoding unit 28, that is to say the Qi mode bits associated with the instruction “Ii” currently being decoded is carried out by the decoding of the code of the said instruction. In particular, the decoding of the code of the instruction “Ii” indicates to the decoding unit 28 the values of the Qi mode bits to be read.
The object of this portion of program is to store the content of a memory in a FIFO register referenced “reg_fifo” in the program by way of a software loop comprising a load instruction referenced “LD” in the program and for which one wishes to modify the nature of the operation that it codes and whose associated mode bit is referenced “LD_conf” in the program.
The start address and the end address of the memory are respectively referenced “adr_beg” and “adr_end” in the program. The address of the memory is pointed at by the pointer referenced “p_memory” in the program.
To store the data of the memory, all the addresses of the said portion of the memory are run through, incrementing the address pointed at by the pointer “p13 memory”.
By comparison, an incrementation instruction INC can also be used to increment the address pointed at by the pointer as is illustrated in
Through the present invention, the aforesaid constraints are circumvented by modifying the nature of the operation coded in the load instruction. More precisely, the load instruction is indicated to the microprocessor 10, in particular the decoding unit 28, as being a post-incremented load instruction, that is to say that for each iteration of the software loop, the address of the memory pointed at by the pointer “p_memory” is incremented automatically.
The program thus comprises an initialization instruction “SET” for initializing the mode bit referenced “LD_conf” associated with the load instruction. For example, the initialization instruction sets the value of the mode bit to the logic value “1”.
Thus, during the decoding of the load instruction for each iteration of the software loop, the decoding unit reads the state of the associated mode bit in the mode register to determine according to which mode of execution the load instruction is to be executed.
The nature of the operation coded by the load instruction is modified and comprises in addition to its initial function, namely to load a data item into a memory space (here a register), the function of post-incrementation of the address of the memory pointed at by the pointer “p_memory”.
When all the data are copied from the memory into the register, a reinitialization instruction “RESET” is executed to reinitialize the mode bit of the load instruction and to indicate to the microprocessor that it can again execute the load instruction according to the normal mode of execution. For example, the reinitialization instruction sets the value of the mode bit to the logic value “0”.
More precisely, in the subsequent execution of the program, the operation coded by the load instruction has as function to load data into a specific location but no longer carries out the post-incrementation function.
An advantage of the invention is understood here, according to which the program is of reduced size and of reduced execution time as compared with the procedure of
For example, to store 1000 values in the register on the basis of 1000 values stored in the memory according to the procedure of the state of the art with the aid of a software loop, the microprocessor executes 4002 operations, whereas according to the embodiment of the present invention, the microprocessor executes 3004 operations (i.e., a reduction of 25% of the operations to be executed by the microprocessor and consequently an increase in the performance of the said microprocessor in terms of speed of execution of the program). This advantage is all the more beneficial as microprocessors execute a very large number of software loops of this type.
Of course, the embodiment given above by way of example is not limiting. It is possible to modify the nature of the operations of each instruction of the set of instructions of the microprocessor, each instruction being executable according to several modes of execution. For example, in the example described above, it is possible to also assign the function of loading with post-decrementation to the load instruction.
Moreover, the size in terms of number of bits of the instructions of the microprocessor is nonlimiting and can take any value whatsoever, for example 8 bits, 16 bits, 32 bits or more.
Although preferred embodiments of the method and apparatus of the present invention have been illustrated in the accompanying Drawings and described in the foregoing Detailed Description, it will be understood that the invention is not limited to the embodiments disclosed, but is capable of numerous rearrangements, modifications and substitutions without departing from the spirit of the invention as set forth and defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 0402929 | Mar 2004 | FR | national |
