Patent Application
20060291548
This application claims priority to German Application No. DE 102005024649.4, filed on May 25, 2005, and titled “Device and Method for Measuring Jitter,” the entire contents of which are hereby incorporated by reference.
Data transmission systems such as, e.g., SONET/SDH, require that the system clock be complied with very precisely. Fluctuations in the system clock, if they exceed a permissible tolerance threshold, may lead to incorrect assessments of the received sinusal and thus initiate a bit error.
Real clock generators are always subjected to such fluctuations. In this case, fluctuations may affect not only the clock frequency but also the phases of the rising edges or of the falling edges. In this case, by way of example, the edge of the clock sinusal sometimes occurs somewhat earlier and sometimes occurs somewhat later. This behavior is referred to as jitter. The following definition for jitter is used hereinafter.
Jitter denotes the periodic and stochastic deviations of the core instants of a digital sinusal relative to their ideal, equidistant core instants. The core instant of a digital sinusal may be any customary, easily identifiable point of the sinusal, such as, e.g., the rising or falling edge or the sampling instant. Consideration is given for example to a square-wave clock sinusal
This square-wave clock sinusal is then acted upon by a periodic jitter sinusal where
j(t)=β*sin(2πfjt+Φ)
This produces a sinusal subjected to jitter where
u(t)=square(f1t+β sin(2πfjt+Φ)).
In this case, β emits the jitter amplitude, fj indicates the jitter frequency and Φ indicates the jitter phase offset. Electrical components, e.g., transmitters or transceivers in data transmission systems, have to satisfy specified requirements with regard to their jitter parameters. One requirement is, e.g., the jitter tolerance. This defines what jitter can be applied to a semiconductor component without the data transmission error rate increasing.
The characteristic value of the jitter transfer coefficient indicates the magnitude of the ratio between the jitter amplitude at the output of the component and the jitter amplitude at the input of the component.
When testing the components with regard to their jitter behavior it is necessary to use very complicated test devices, because the jitter measurements have to be effected with high precision.
In application note 1267 “Frequency Agile Jitter Measurement System” from Agilent Technologies, the section “Jitter transfer measurement setup” describes a test device for measuring the jitter transfer coefficient, in which test device a digital sinusal generator feeds a predefined or a random data sequence to a semiconductor component to be tested. The clock is likewise generated in the sinusal generator and a deterministic or statistical jitter sinusal is modulated onto the clock.
The input clock beset with jitter is fed to a first input of a jitter measuring instrument, on the one hand, and is connected to the clock input of the semiconductor component to be tested, on the other hand. A clock is recovered from the output data stream of the component. This recovered clock is fed into a second input of a jitter measuring instrument.
The jitter measuring instrument compares the input clock with the recovered output clock and from this determines the extent to which the recovered clock still contains the input jitter. Extremely high demands are made of the measurement technology particularly in the jitter measuring instrument and in the sinusal generator. High-precision testers and measuring instruments are used particularly at high frequencies. These high-precision testers and measuring instruments are very sensitive and expensive. Moreover, the labor for setting and calibrating these testers and measuring instruments is high.
The invention provides a test device and a method with which jitter in sinusals is measured in a less complicated manner and thus less expensively. The test device includes a data pattern generator that generates a data stream at its output by modulating a low-frequency analog basic sinusal via a sampling frequency fs. The basic sinusal has a frequency fc or is a combination of sinusals with different basic frequencies fci, where i is a running variable. The sampling frequency fs is greater than the basic frequency fc or the basic frequencies fci. In this case, the modulation has the “noise-shaping” property. The latter means that the error sinusal caused by the modulation is shifted toward very high frequencies. The power density spectrum of the modulating sinusal, by contrast, remains in baseband. In this case, the baseband is situated at the frequency of the basic sinusal.
The test device furthermore includes a jitter generator. According to one option, the jitter generator is connected between the output of the data pattern generator and a terminal which serves for connection to a data input of a component to be tested. With the construction described, the output sinusal of the data pattern generator is subjected to jitter and fed to the data input of the component to be tested. In the case of this first option, a clock sinusal may additionally be connected to a second terminal for connection to a clock input. It is also possible for the semiconductor component to be tested not to be connected to a clock, but rather to obtain the clock from the sinusal at the data input.
According to a second option, the jitter generator is connected to the output of a clock generator. The output of the jitter generator is connected to a second input terminal for connection to a clock input of the electrical component to be tested. The clock generator generates a clock having the test frequency ft, which is equal to or an integer multiple of the sampling frequency fs.
An output terminal serves for connection to the data output of the semiconductor component to be tested. The output terminal is connected to an input of an evaluation circuit. The evaluation circuit determines the jitter parameters of the input sinusal present at its input. The jitter parameters are determined from the low-frequency components of the input sinusal. Low-frequency components of the input sinusal are those frequency components of the input sinusal whose frequency is less than half the sampling frequency fs/2.
The jitter parameters include the jitter frequency and the jitter amplitudes of a sinusal and also the jitter transfer coefficient of a semiconductor component. By virtue of the fact that the frequency of the analog basic sinusal is known, the jitter amplitude, the jitter frequency and the jitter transfer coefficient can be determined from the input sinusal of the evaluation device.
According to the present invention, the data sinusal, which heretofore was not used for determining the jitter parameters and could even be random, is used as an information carrier. Purely pseudorandom bit patterns have generally been used heretofore. An analog basic sinusal chosen such that the jitter can be measured is modulated onto the data sinusal.
The fact that the jitter parameters are determined at low frequencies means that the complexity for the measurement technology is considerably reduced, because the complexity for the measurement decreases with the frequency. Rather than special measuring instruments, standard measuring instruments which are also used for other measurements are used for the jitter measurement. The standard measuring instruments are less sensitive, require less labor for calibration and are additionally less expensive.
In one embodiment of the invention, the data pattern generator generates a delta-sigma-modulated data stream, which is also referred to as a pulse-width-modulated data stream, at its output. A delta-sigma-modulated data stream is a digital data stream generated by the sampling with a sampling frequency fs of an analog basic sinusal.
Delta-sigma modulator architectures are sensitive to jitter. The zero crossings of the binary digital pulses are readily shifted by the jitter in the clock sinusal, as a result of which the binary zeros and ones turn out to be sometimes shorter and sometimes longer, depending on the jitter. The consequence of this is that additional frequency components occur in the frequency spectrum both in baseband and at the high frequencies.
This leads to significant sinusal interference during the demodulation, i.e., the recovery of the analog sinusal. The sensitivity to jitter is extremely undesirable in audio applications, because this sensitivity leads to significant sinusal interference during the demodulation, i.e., the recovery of analog sinusal. Therefore, the modulators used therein are designed for maximum jitter robustness. According to the invention, by contrast, this property is utilized as a measurement principle. In this case, the modulators to be used are optimized for maximum jitter sensitivity. The jitter amplitude can be determined from the baseband sinusal spectrum altered by jitter.
Delta-sigma-modulated data streams generally have the “noise-shaping” property. The extent to which the error sinusal is shifted to high frequencies depends on the circuits used. In addition, the extent to which the modulated sinusal is influenced by jitter also depends on the circuits. Consequently, there are many possible options for finding an optimum of small error sinusal in baseband and high sensitivity to jitter by the choice of the circuits used. When defining which frequencies belong to the low-frequency component, on the one hand it must be taken into consideration that the error sinusal caused by the delta-sigma modulation does not belong to the low-frequency component. On the other hand, the frequencies of the analog harmonic sinusal and also the sidebands generated by the jitter frequency must belong to the low-frequency range as completely as possible.
For most applications, therefore, all frequencies which belong to the range resulting from the basic frequency fc and the largest of all the jitter frequencies fj according to the formula fc±kfj, where k is a natural number, belong to the low-frequency range. As a result, only the first k sidebands are considered, because the amplitudes of the higher sidebands are so small that they can be disregarded. In one embodiment, k is equal to 10. A broad frequency range is thus covered. In order to reduce the test costs further, k is set to be equal to eight or preferably six or preferably equal to three.
Another definition for the boundary between the low-frequency component and the other components is afforded by the criterion that the error sinusal of the delta-sigma modulation must be substantially suppressed in the low-frequency component.
In this case, “substantially” means that the error sinusal is suppressed to ten percent. It is preferable to choose three percent, preferably one percent and preferably two thousandths. In the most preferred case, the error sinusal is not measurable.
The evaluation unit considers only low-frequency components of the input sinusal of the evaluation device. Errors caused by the modulation are thereby masked out. Frequency components of the clock frequency ft are not taken into account either. Consequently, all that remain are the frequency components generated by the basic sinusal and by the jitter, in the low-frequency range. The information about the jitter parameters can be obtained therefrom.
If the basic sinusal constitutes a sinusoidal sinusal, the frequency components can readily be determined from the frequency spectrum at the data output of the electrical component to be tested since it only contains sidebands that effect little interference. In this context, sinusoidal denotes those sinusals which have the form of a sine function or a cosine function or a linear combination of sine and cosine functions.
In one embodiment of the invention, the basic sinusal constitutes a linear combination of sinusoidal functions having different frequencies fci. In this case, measurement is effected in one step simultaneously with a plurality of basic frequencies fci. Frequency spectra around these basic frequencies fci arise at the data output. By means of this “multi-tone test”, the measurement method is parallelized, which shortens the time for measuring the jitter parameters.
In order to generate the delta-sigma-modulated data stream, the data pattern generator may have a delta-sigma modulator. Such a modulator is an electrical circuit which samples an analog sinusal having a basic frequency fc. The sampling is effected with the higher sampling frequency fs. Such a delta-sigma-modulator, which is present at a dedicated electrical circuit, can be adapted particularly well to different requirements for the desired sinusal profile. This applies primarily to higher frequencies at which particular demands are made of screening and reflection behavior of the circuits used.
In a further embodiment, the data pattern generator has a memory for a digital sinusal sequence. The values stored in the memory are generated by the simulation of a delta-sigma modulation. The latter involves simulating how an analog harmonic sinusal having the basic frequency fc is sampled with the sampling frequency fs. Registers that are available in any standard tester may be used as the memory for the digital sinusal sequence. Therefore, for the test device there is no need for a dedicated delta-sigma modulator to be realized as an electrical circuit, rather a simulation by software suffices. In this case, the simulation may be effected in a digital computer, e.g., a PC.
This saves space in the tester and obviates the need to specifically adapt the tester to the jitter test. During the simulation, the model of the delta-sigma modulator may be chosen as desired without having to give consideration to restrictions governed by circuit technology.
The model of the delta-sigma modulator is expediently chosen so as to produce a maximum sensitivity to the input jitter and so to optimize the sinusal/noise ratio within the sinusal band defined by the basic frequency fc.
The jitter generator preferably contains a phase modulator having a first input and a second input. The phase modulator is connected to a clock generator at its first input. The clock generator generates a sinusal of the form
u(t)=g1(t).
In this case, g1 is usually a function which generates a periodic clock.
A generator for generating a sinusoidal sinusal with the jitter frequency fj is connected to the second input of the phase modulator. The pulse generator generates a test clock with the aid of the two input sinusals, the test clock having the form
u(t)=A1g1(t+βsin(2πf, t+Φ)).
A deterministic jitter sinusal is thus applied to the test clock. This has the advantage that only the known jitter frequency has to be taken into account in the evaluation of the frequency components of the output sinusal. As a result, the spectral lines in the output sinusal can be unambiguously assigned their causes.
In this case, g1 is preferably a digital function. In the case of digital functions, the instants for a sinusal change are precisely defined, so that during the evaluation of the sinusals it is readily possible to ascertain which sinusal parts belong to the jitter and which belong to the sinusal with the function g1.
In a further embodiment, the jitter generator subjects a sinusal to jitter with the aid of a stochastic noise sinusal. The component to be tested can thus be tested simultaneously with a multiplicity of input jitter parameters.
In order to separate the low-frequency component of the input sinusal from the high-frequency components of the input sinusal, use may be made of a low-pass filter. The latter is part of the evaluation device and filters the input sinusal at the input of the evaluation device. The low-pass filter does not have to be directly connected to the first input, but rather may also be connected downstream of processing units, such as, e.g., amplifiers. The limiting frequency of the low-pass filter lies below the frequencies of the clock sinusal ft and half the sampling frequency fs.
The low-pass-filtered output sinusal contains frequency components of the modulated basic sinusal and also frequency components directly in the vicinity thereof which were caused by the jitter.
The requirement made of the low-pass filter is for it to be as linear as possible and for the limiting frequency to lie somewhat above the baseband bandwidth. Therefore, a passive filter is used in order to meet the first condition, while the second condition is ensured by the setting of the limiting frequency of the low-pass filter.
In order to filter the sinusal at the input of the evaluation device, it is also possible to use a bandpass filter. The bandpass filter also filters out components of low frequencies, for example interference due to the external voltage supply at 50 Hz or 60 Hz.
Digital sinusal processing is particularly suitable for determining the frequency components generated by the jitter. Digital sinusal processing generally has the advantage that it exhibits long-term and thermal stability and that it is reliable and insensitive to interference. In order to make the output sinusal of the low-pass filter accessible to digital sinusal processing an analog-to-converter is connected to the output of the low-pass filter or of the bandpass filter.
The analog-to-digital converter converts the analog sinusal at the output of the low-pass filter into an n-value digital sinusal. This sinusal is fed to a computing unit, in which it is processed further. The sinusal may be transformed, e.g., by means of an FFT (Fast Fourier Transformation) in the frequency ranges where the different frequency components generated by the jitter can be read. The computing unit in which the digital output sinusal of the analog-to-digital converter is processed may be provided by the tester. However, it may also be mounted on the load board, e.g., in the form of an FPGA (Field Programmable Array).
It is also possible for the computing unit to be made available in the semiconductor component to be tested, provided that the latter has a processor unit. This reduces the terminals required for the test and avoids corruption of the measurement result by long lines on the load board.
In a further embodiment, the output sinusal of the low-pass filter is fed directly to a spectrum analyzer, which carries out the separation of the frequency ranges. This obviates the additional circuitry outlay for the analog-to-digital converter and reduces the risk of additional interference being generated by the analog-to-digital conversion.
The data pattern generator and the clock generator are preferably accommodated in a tester, while parts of the evaluation circuit and the terminals for connection to a component to be tested are formed on a load board. As a result, those parts of the test device which are specifically required for the test of the jitter parameters are realized on the load board, whereas those devices which are required for a multiplicity of tests are provided in the tester. During the jitter test, the already existing testers can thus be used without modification and only the load boards are specifically adapted to the jitter test.
The components of the test device, the data pattern generator, the jitter generator, the clock generator and the evaluation device may be integrated as BIST (Built-in Self-Test) individually or in combination in the semiconductor component to be tested. This advantageously reduces the sinusal lines between the components and the costs for the test device.
The invention also relates to a method for measuring jitter parameters. Such a method comprises the provision of a semiconductor component to be tested, having at least one data input and a data output. A further step involves generating a data stream by modulation of a basic sinusal, which has the basic frequency fc or a plurality of basic frequencies fci, by a sampling frequency fs. The modulation has the “noise-shaping” property according to which the error sinusal of the modulation is shifted into high frequencies.
The semiconductor component is subsequently operated, in which case, in a first option, the digital data stream generated by the modulation is present at the data input and a clock sinusal subjected to jitter and having the clock frequency ft is present at a clock sinusal. In this case, the clock frequency ft is equal to or an integer multiple of the sampling frequency fs. In a second option, the data stream obtained by the modulation is subjected to jitter and the data stream that has been subjected to jitter is applied to the data input.
The subsequent determination of the jitter parameters of the semiconductor component is effected by the assessment of the sinusal sequence at the data output of the semiconductor component. Only the low-frequency components of the sinusal sequence at the data output are assessed in this case.
The assessment of the low-frequency components of the sinusal sequence is significantly less complicated than a calculation of the entire sinusal spectrum. Low frequency is deemed to include the frequencies which are less than half the sampling frequency fs/2 and are at a sufficient distance from half the sampling frequency fs/2 without the error sinusal produced by the modulation being influenced.
Since the error sinusal is shifted into the high frequency range, the jitter in the low frequency range becomes visible in an uncorrupted manner. The circuitry outlay for measuring the jitter parameters is thus also significantly reduced. Standard test devices may be used instead of the special jitter test devices. This also simplifies the test process, because for the jitter measurement the semiconductor components to be tested thus no longer need be brought to special tester stations for the jitter measurement, but rather can be tested by the standard testers with a specific load board.
If the modulation used is a delta-sigma modulation, a desired optimum with regard to a high sensitivity to jitter and a small error sinusal in baseband can advantageously be chosen by means of a suitable choice of the circuits used.
If the low-frequency range is additionally restricted, the influence of the error sinusal is reduced. One embodiment of the invention provides the definition that all frequencies which are within the range fc±3fj belong to the low-frequency range. In the case where there are a plurality of basic frequencies fci, the largest of the basic frequencies fci is used in the calculation. As a result, only the first k sidebands are considered, because the amplitudes of the higher sidebands are so small that they can be disregarded. k is chosen to be equal to 10, preferably eight or preferably six or preferably three.
Another definition for the boundary between the low-frequency component and the other components is afforded by the criterion that the error sinusal of the delta-sigma modulation must be substantially suppressed in the low-frequency component.
In this case, “substantially” means that the error sinusal is suppressed to ten percent. It is preferable to choose three percent, preferably one percent and preferably two thousandths. In the most preferred case, the error sinusal is not measurable.
The distribution of the error sinusal can be estimated by a simulation in which the limiting frequency is shifted.
The basic sinusal is advantageously sinusoidal. As a result, there are only few interfering sidebands which have to be taken into account in the evaluation.
If the basic sinusal comprises a linear combination of a plurality of sinusoidal functions with different frequencies, then a plurality of basic frequencies can be tested simultaneously.
If the step of determining the jitter parameter contains a step of low-pass filtering the sinusal sequence at the data output, the high-frequency components of the data output sinusal are filtered away and need no longer be taken into account in the subsequent processing steps. As a result, less complicated measuring devices can be used because they only have to evaluate low-frequency sinusals.
A bandpass filter may also be used instead of a low-pass filter. In the case of a bandpass filter, additional interference occurring at very low frequencies, for example at 50 Hz, is removed.
In one embodiment, the low-pass filtering or bandpass filtering of the sinusal sequence at the data output is followed by analog-to-digital conversion. As a result, the low-pass-filtered data output sinusal is available in digital form and can be processed further by digital sinusal processing. Digital sinusal processing has advantages with regard to thermal stability, reliability and low sensitivity to interference. Moreover, the results obtained by digital sinusal processing are readily reproducible, and measuring instruments having the same structural component types generally have the same properties and can readily be interchanged among one another.
If the delta-sigma-modulated data stream is generated by cyclically reading out from a data register, the pattern of the data stream need only be generated once. This may be effected for example by calculating a softer model of a delta-sigma-modulator. A register that is already present in a standard tester may be used as the register, so that there is no need to provide additional circuits for the delta-sigma-modulator.
During the generation of the delta-sigma-modulated sinusal, preferably a harmonic analog basic sinusal having a basic frequency fc is sampled with a sampling frequency of fs. The fact that a harmonic analog sinusal is used means that there are only few frequency characteristic curves which have to be taken into account in the evaluation of the data output sinusal, which facilitates the calculation of the jitter parameters.
If the clock sinusal subjected to jitter is generated by phase modulation of the clock sinusal or of the delta-sigma-modulated data stream with a harmonic sinusal having the jitter frequency fj, a deterministic jitter is applied to the test sinusal. The phase and amplitude thereof are known, so that the characteristic figures for the jitter transfer coefficient and the jitter tolerance are calculated from the comparison of the data output sinusal with the known values for the input jitter. In the evaluation of the jitter parameters, the jitter amplitude of the sinusal sequence at the data output is determined from the jitter amplitudes of the low-frequency components at the data output.
On account of the clock sinusal being subjected to jitter in a targeted manner with the sinusoidal sinusal having the frequency fj, a phase-modulated sinusoidal sinusal having the basic frequency fc and the modulation frequency fj appears in the output spectrum of the analog output sinusal. The frequency spectrum of a harmonic sinusal which is phase-modulated with a second harmonic sinusal is described by the Bessel functions. The amplitude of the modulating sinusal can be calculated from the ratio of the amplitudes of the Bessel lines. This value corresponds to the maximum excursion of the jitter, which is also called “peak-to-peak” jitter. The comparison of the amplitudes with the Bessel functions has the advantage that the values can be read from existing tables and complicated calculation of the modulation is not required.
In the case where the jitter amplitude is very much less than 1, for example 0.1, the square of the jitter amplitude can be calculated from the ratio of double the power of the side lines through the power of the basic frequency. This method step affords a further simplification for comparison with respect to other embodiments.
The jitter frequency can be determined by the spacing of the low-frequency spectral lines by considering the spacing of the spectral line at the basic frequency fc with respect to the remaining spectral lines.
Particularly if the electrical component to be tested has a device for jitter attenuation, the jitter transfer coefficient has to be measured. Such a device is a “clean-up PLL”, for example, which reduces jitter present within a predetermined frequency range by a specific magnitude. The output sinusal contains the same data sequence as the input sinusal but the jitter component is attenuated by a specific amount. In order to measure this, the jitter amplitude of the input sinusal of the semiconductor component is divided by the jitter amplitude of the output sinusal, which produces the jitter transfer coefficient.
The invention will now be explained in more detail with reference to the accompanying figures.
The jitter amplitude is represented in the UI unit. UI is the abbreviation for Unit Interval. It specifies the fraction of the length of the data interval. In the equation
u(t)=square(ftt+β sin(2πfjt+Φ))
the quantity β has the Unit Interval unit. The clock frequency ft shall be (2 T1)−1. If β is equal to 0.1 UI, for example, then the amplitude of the jitter is equal to 0.1 times Tt. In this case, Tt corresponds to the time for which u(t) remains a constant value. The phase of the clock edge thus fluctuates temporally forward and backward by 0.05 Tt in each case about a middle position. The jitter frequency ft has the hertz unit. The range shown extends from 10 Hz to 10 MHz.
The jitter transfer characteristic curve, which is designated as SONET mask in
A test device according to the invention is illustrated schematically in
The clock generator 4 in the tester 1 generates a clock sinusal Clk_a having the frequency ft, which supplies the phase modulator 6. The sine wave generator 5 generates a sinusoidal sinusal MOD_IN having the frequency fj, which is connected to the second input of the phase modulator. The output of the phase modulator 6 supplies the sinusal Clk_b, which operates the clock input of the semiconductor component 7 to be tested on the load board 2.
A sinusoidal sinusal DATA_ANA of the form sin(2πfct) is generated in the basic sinusal generator 11.
The data pattern generator 3 generates from this the sinusal DATA_IN having the frequency fs, which is connected to the data input of the semiconductor component 7 to be tested. The electrical component 7 to be tested outputs the sinusal DATA_OUT which is connected to the input of the analog-to-digital converter 9 via the low-pass filter 8. The analog-to-digital converter 9 generates the digital sinusal ADC_OUT having a width of N bits.
The clock generator 4 generates a high-frequency, frequency-stable system clock Clk_a having the clock frequency ft of 139.264 MHz. This frequency corresponds to the DS4N interface specification for SONET. The clock sinusal is a regular sequence of, considered digitally, ones and zeros.
By contrast, the sine wave generator 5 generates a sine wave MOD_IN having the frequency fj, which is 500 Hz in the example under consideration. The sinusal generator 5 should likewise be as frequency-stable as possible in order that the measurement result is not corrupted.
In the phase modulator 6, a clock sinusal is generated which has the same frequency has the input clock Clk_a but is additionally phase-modulated. This means that, e.g., the zero-one transitions are not effected in each case at the beginning of a new clock cycle, rather they are in each case shifted forward or backward. A clock sinusal artificially subjected to jitter has consequently been generated. The amplitude of the jitter shall be β. This can be set in a targeted manner either by the sine wave generator or in the phase modulator.
A data pattern DATA_IN having the sampling frequency fs is generated in the data pattern generator 3. The data pattern is also referred to hereinafter as a data stream. It is generated from the basic sinusal DATA_ANA by the sinusal being subjected to delta-sigma modulation.
A delta-sigma-modulator converts an analog basic sinusal into a binary data sequence. Delta-sigma modulations are known for example from the book “Delta-Sigma-Data Converters” by Norsworthy, Schreier and Temes, IEEE Press.
Correspondingly converted data streams are also referred to as pulse-width-modulated data streams. In this case, the bandwidth of the analog sinusal is very much smaller than that of the digital sinusal.
The electrical component 7 to be tested receives the pulse-width-modulated data sinusal DATA_IN by means of the clock Clk_b subjected to jitter. Delta-sigma architectures are described as sensitive to jitter. The zero crossings of the binary digital pulses are shifted slightly by jitter in the clock sinusal. As a result, the binary zeros and ones turn out to be sometimes shorter and sometimes longer depending on the jitter. In the frequency spectrum, both the baseband and the high frequencies additionally have frequency components.
The electrical component 7 to be tested has a device which reduces the jitter at its clock input. At the output DATA_OUT a measurement is made of how much jitter has been filtered by the output sinusal DATA_OUT firstly being connected via a low-pass filter 8. The output sinusal of the low-pass filter 8 is an analog phase-modulated sinusoidal sinusal having the basic frequency fc and a modulation frequency fj.
The calculation is effected in the computing unit 10. In this case, the sinusal ANA_OUT is converted into a digital sinusal ADC_OUT by an analog-to-digital converter 9. The digital sinusal ADC_OUT is used by the computing unit 10. This performs, for example, a transformation into the frequency domain and calculates the jitter parameters from the frequency spectrum by comparison with the Bessel lines.
The frequency spectrum of this harmonic sinusal, which is phase-modulated with the second harmonic sinusal, is described by the Bessel function. The amplitude of the modulating sinusal can be calculated from the ratio of the amplitudes of the Bessel lines. This value corresponds to the “peak-to-peak” jitter of the digital data stream DATA_OUT.
The ratio between the jitter amplitude thus determined and the amplitude of the sinusal MOD_IN modulated in a targeted manner yields the jitter transfer coefficient sought.
In the case where the sampling frequency fs and the clock frequency Clk_a are identical, the clock generator 4 advantageously feeds the data pattern generator 3 as well. This ensures that no additional interference occurs as a result of the use of different clock generators.
In an embodiment of the invention that is not shown, the electrical component 7 to be tested does not have a separate clock input. Rather, it generates an internal clock from the data sinusal present at a data input. Consequently, the output of the clock generator 4 is connected only to a clock input of the data pattern generator 3, and not to a clock input of the electrical component 7 to be tested.
In
The clock Clk_b, by contrast, has been subjected to jitter in a targeted manner by means of the phase modulator 6.
The time between the second and third clock edges is no longer equal to the reciprocal of the clock frequency ft, but rather is calculated from the reciprocal of 0.9 times ft. The fourth rising edge of the clock sinusal Clk_b was not phase-shifted. The time between the first and fourth clock edges amounts overall to three times the reciprocal of the clock frequency ft. The spacing between the third and fourth edges is equal to the reciprocal of 1.1 times the clock frequency ft. For the illustration in
The electrical component to be tested receives the data stream DATA_IN at its data input and the test clock Clk_b as clock sinusal. It outputs the data sinusal DATA_OUT at its output.
The data sinusal DATA_OUT contains a power density spectrum whose positive sideband is reproduced in
In the high frequency range, further frequency lines are situated in the vicinity of half the sampling frequency fs.
Additional spectral lines are apparent compared with the power density spectrum of the data input sinusal DATA_IN as illustrated in
Higher-order spectral lines in baseband are not depicted in
After the data output stream DATA_OUT has been low-pass-filtered, the result is a frequency spectrum as illustrated in
The value for the jitter transfer can be subsequently be calculated from the value for the jitter amplitude by determining the ratio of the jitter amplitude at the output and the jitter amplitude β of the clock sinusal Clk_b.
A method according to an exemplary embodiment of the invention is shown in
The calculation of the data stream with the aid of the software model is preferably not effected in a tester, but rather during the test preparation once on a digital computer. A special sinusal generator is not required in this case. After the pattern has been generated, it is stored in a test program or in a register of the tester. The data pattern is read out cyclically and a data stream is thus generated. The latter feeds the data input of a semiconductor component to be tested.
A clock sinusal which has been phase-modulated by a low-frequency sinusoidal sinusal is generated at the same time. The edges of the clock sinusal are thereby shifted. The clock sinusal is thus artificially subjected to jitter. This clock sinusal artificially subjected to jitter is applied to the clock input of the semiconductor component to be tested. The electrical component to be tested is operated with the data stream and the phase-modulated clock sinusal.
The output sinusal of the semiconductor component is filtered by an analog low-pass filter. The low-pass filter removes frequency components resulting from the sampling and frequency components resulting from the error during the delta-sigma modulation. Frequency components resulting from the basic sinusal and the jitter sinusal remain.
The analog sinusal that has been filtered by the low-pass filter is converted into a digital sinusal, for example by means of an AD converter, from which the frequency components are determined.
The discretized data present in the time domain are transformed into the frequency domain in a subsequent step. This may be effected for example by an FFT (Fast Fourier Transformation). The sampling rate of the AD converter must be at least a factor of two higher than the sum of basic frequency and the highest Bessel line k*fj taken into account. It is thus possible to identify the spectral lines generated by the jitter in the vicinity of the basic frequency fc. The jitter parameters are determined by evaluation of the data present in the frequency domain. The power densities at the basic frequency fc and at the adjacent frequencies fc+fj, fc−fj, fc+2 fj, fj, fc−2 fj, . . . are considered in this case. These are compared with the function values of the Bessel function of the first kind. The jitter amplitude can be determined from this comparison. If the jitter amplitude determined in this way is compared with the jitter amplitude of the clock sinusal, it is possible to calculate how much jitter was masked out by the semiconductor component to be tested. This indicates the jitter transfer coefficient. If the method is carried out at a plurality of test frequencies, the jitter transfer characteristic curve is produced from this.
If the basic sinusal contains a plurality of different basic frequencies fci, jitter parameters for a plurality of basic frequencies are calculated simultaneously by the method shown in
Having described preferred embodiments of the invention, it is believed that other modifications, variations and changes will be suggested to those skilled in the art in view of the teachings set forth herein. It is therefore to be understood that all such variations, modifications and changes are believed to fall within the scope of the present invention as defined by the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
| Number | Date | Country | Kind |
|---|---|---|---|
| DE 102005024649.4 | May 2005 | DE | national |
