Patent Application
20080204056
This Utility patent application claims priority to German Patent Application No. DE 10 2007 009 878.4 filed on Feb. 28, 2007, which is incorporated herein by reference.
The invention relates to a device, a system, and a method for performing a test of semiconductor devices with an optical interface, in one embodiment of semiconductor memory devices.
Semiconductor devices, e.g., integrated (analog or digital) computing circuits, semiconductor memory devices such as, for instance, functional memory devices (PLAs, PALs, etc.) and table memory devices (e.g., ROMs or RAMs, in one embodiment SRAMs and DRAMs), etc. are subject to comprehensive tests during and after their manufacturing processes.
For the common manufacturing of a plurality of (in general identical) semiconductor devices, a wafer (i.e. a thin disc of monocrystalline silicon) is used. The wafer is processed appropriately (e.g., subject successively to a plurality of coating, exposure, etching, diffusion, and implantation processes, etc.), and subsequently e.g., sawn apart (or e.g., scratched, and broken), so that the individual devices are then available.
During the above-mentioned manufacturing process and after the finishing of the semiconductor devices (i.e. after the performing of all the above-mentioned wafer processes), the semiconductor devices are i.a. subject to a plurality of test methods—for instance, it is possible to test the finished devices that are still available on the wafer by using appropriate test devices (“wafer tests”).
In one embodiment, one or a plurality of further tests (at further test stations, and by using appropriate, further test devices) may, for instance, be performed after the incorporation of the semiconductor devices in the semiconductor device packages, and/or, for instance, after the incorporation of the semiconductor device packages (along with the respectively incorporated semiconductor devices) in electronic modules, e.g., memory modules (“module tests”).
For a cost-efficient manufacturing of semiconductor devices it is required that both the costs for the manufacturing of the semiconductor devices and the costs for the testing of the semiconductor devices are reduced. Due to the strongly increased complexity of the semiconductor devices, the costs for the testing of the devices are in many cases comparable to the costs for the manufacturing of the dies in the manufacturing facility. The test effort is i.a. dependent on the costs for the test equipment and on the test time in which the test equipment is used for the testing of the semiconductor devices. It is therefore desirable to minimize both the test time and the complexity of the test equipment so as to minimize the costs for the testing of the semiconductor devices.
For avoiding excessive costs with a simultaneous adequate provision against errors, the development has recently gone toward semiconductor devices or integrated circuits, respectively, with an integrated self test function (Built-in Self Test, BIST). With this proceeding, one or a plurality of circuits are implemented in the semiconductor device or in the integrated circuit itself, which enable a self test. The respective integrated test circuit generates test signals and may then compare, for instance, response signals that were generated in reaction to the test signals with predetermined correct response signals, so that a test result can be output to an assigned Automatic Test Equipment (ATE). Built-in Self Tests are increasingly simple to implement by automated design processes and consume relatively little space with the large number of circuit elements that is common nowadays, but they are adapted to substantially reduce the material and time effort during testing.
The above-described Built-in Self Test function is usually implemented in conventional semiconductor devices with an electrical interface, but it may also be used and implemented in semiconductor devices with an optical interface.
Semiconductor devices with an optical interface will gain increasing importance in the future since it is to be expected that the clock frequencies of future processors, etc. will continue to expand in the range of several Gigabits per second and more, and since sophisticated information processing systems will thus require total bandwidths of up to 1 Terabit per second and more for data communication. The previously common connecting medium, copper lines, will no longer be suited for such bandwidths.
It is therefore to be assumed that optical media will find a broad range of application in high performance systems, and that optical media will replace the previously common electrical media in many fields. Thus, optical connections for the data communication between individual devices, modules, but also between semiconductor devices on the same printed circuit board or in the same module are conceivable in the nearer future. The bandwidth of data communication between a GPU (Graphic Processor Unit) and an assigned memory is, for instance, continually increasing to such a degree that an (at least partial) optical interface between the GPU and the memory will replace the present electrical interface in the nearer future.
The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments and together with the description serve to explain principles of embodiments. Other embodiments and many of the intended advantages of embodiments will be readily appreciated as they become better understood by reference to the following detailed description. The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts.
In the following Detailed Description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. In this regard, directional terminology, such as “top,” “bottom,” “front,” “back,” “leading,” “trailing,” etc., is used with reference to the orientation of the Figure(s) being described. Because components of embodiments can be positioned in a number of different orientations, the directional terminology is used for purposes of illustration and is in no way limiting. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
It is to be understood that the features of the various exemplary embodiments described herein may be combined with each other, unless specifically noted otherwise.
The testing of such semiconductor devices with an optical interface by using an external, optical ATE is complex and cost-intensive since an expensive high speed test equipment has to be used. Additionally, a control for the automatic connection of the optical output of the semiconductor device to be tested with the ATE is required. Further, a parallel testing of a plurality of semiconductor devices is possible in a restricted scope only since an optical connection to the external optical ATE is required for every semiconductor device to be tested.
One or more embodiments provide a device and a method for performing a self test at a semiconductor device with an integrated self test function, in one embodiment a device and a method which require, with adequate provision against errors, less time and cost efforts for a testing of semiconductor devices with an optical interface.
In one embodiment, there is provided a device for performing a test at a semiconductor device with an integrated self test function and with an optical interface which includes an optical transmitter and an optical receiver, wherein the device includes a system or means for returning an optical emission of the semiconductor device from the optical transmitter to the optical receiver of the semiconductor device.
In one embodiment, there is provided a system for performing a test which includes a semiconductor device with an integrated self test function and with an optical interface, wherein the optical interface includes an optical input and an optical output, wherein the system further includes a system or means for returning an optical emission of the semiconductor device from the optical output of the semiconductor device to the optical input of the semiconductor device.
In one embodiment, there is provided a method for performing a test at a semiconductor device with an integrated self test function and with an optical interface which includes an optical input and an optical output, wherein an optical emission of the semiconductor device is returned from the optical output to the optical input of the semiconductor device.
The embodiments have in common that a semiconductor device with an optical interface and an integrated self test function, the Built-in Self Test (BIST) functionality, has to be tested in each case.
In the following embodiments, as will be explained in more detail in the following, a BIST logic provided on the respective device may, for instance, generate test signals or test patterns, i.e., for instance, a plurality of test input signals for partial circuits of the semiconductor device to be tested, and/or the optical interface, and output the test response signals generated by the respective partial circuits and/or the optical interface in response to the test input signals, and/or compare them with predetermined test response signals.
By using the optical interface, the semiconductor device is configured to communicate via an optical high speed line with, for instance, other semiconductor devices.
Therefore, conventional test method by using an external automatic test equipment, the Automatic Test Equipment (ATE), require a relatively expensive optical high speed ATE for a test of the semiconductor device which includes a testing of the optical interface.
In the present embodiments, the requirement of the expensive optical high speed ATE may be eliminated in that the above-mentioned test input signals or the test response signals generated in reaction thereto which are output by an optical transmitter of the semiconductor device as optical signals may be returned to an optical receiver of the semiconductor device via suitable means for returning these optical signals, be converted to electrical signals by the optical receiver, and be then compared, for instance, by the BIST logic with predetermined test response signals.
This proceeding can thus also have the further advantage that the optical transmitter and the optical receiver of the semiconductor device to be tested are tested simultaneously.
The system 20 illustrated in
The spherical reflector 24A, 24B is suited to reflect the electromagnetic beams or light beams, respectively, emitted by the optical transmitter 22. In the drawing, three exemplary optical paths 27A, 27B, 27C of the plurality of possible optical paths of the light radiation are illustrated. The drawing plane constitutes a two-dimensional cross-section through the three-dimensional radiation cone and the three-dimensional spherical reflector 24A, 24B. The two outer optical paths 27A and 27C quasi span the radiation cone emitted by the optical transmitter 22. As may be seen, the illustrated spherical reflector 24A, 24B is suited to reflect light radiation with a high divergence such that the broad radiation cone is bundled prior to hitting the optical receiver 23, or that the beams are oriented in parallel, respectively, and thus a large portion of the strongly divergent radiation emitted by the transmitter 22 is detected by the receiver 23.
An even more efficient returning of the radiation with high divergence emitted by the transmitter 22 can be achieved in that the principles of non-imaging optics are used when designing the spherical reflector 24A, 24B, i.e. all beams of the entire radiation cone are considered and taken into account during the designing of the spherical reflector 24A, 24B such that substantially all light beams, i.e. optical paths of the radiation cone emitted by the optical transmitter 22, are reflected on the optical receiver 23 in a bundled manner, and that it substantially detects all the beams emitted by the transmitter 22. The principles of non-imaging optics are described for three-dimensional problems, for instance, in H. Ries and J. Muschawek: “Tailored freeform optical surfaces”, Journal Optical Society of America A, volume 19, pages 590-595, March 2002, Optical Society of America.
The system 30 illustrated in
The rear reflector 34 is suited to reflect the radiation emitted by the transmitter 32. The rear reflector 34 consists of three essentially planar reflectors, for instance, mirrors which form a right angle together.
The radiation cone emitted by the optical transmitter 32, indicated by the three exemplary optical paths 37A, 37B, 37C, is reflected via the rear reflector 34 back to the receiver 33 of the semiconductor device 31. As is illustrated in
In one embodiment, the illustrated system 30 includes two optical lenses 35A and 35B, wherein the optical lens 35A collimates, i.e. orients in parallel, the beams emitted by the transmitter 32, and the optical lens 35B focuses the beam reflected back in the direction of the semiconductor device 31 on the optical receiver 33. For a radiation with low divergence emitted by the optical transmitter 32, the portion of the radiation emitted by the optical transmitter which is detected by the optical receiver 33 can be distinctly increased by using the two optical lenses 35A and 35B.
The illustrated system 40 includes a semiconductor device 41 with an optical transmitter 42 and an optical receiver 43, a fiber optic cable 44, and two optical lenses 45A and 45B.
The radiation emitted by the optical transmitter 42 is collimated by using the optical lens 45a, enters the fiber optic cable 44, and is guided along the fiber optic cable 44. The radiation emanating from the fiber optic cable 44 is focused on the optical receiver 43 by the optical lens 45B, so that the major portion of the radiation emitted by the transmitter 42 is detected at the receiver 43.
The illustrated system 50 includes a semiconductor device 51 with an optical transmitter 52, an optical receiver 53, a first connection 56A for fiber optic cables, and a second connection 56B for fiber optic cables, and a fiber optic cable 54.
The optical transmitter 52 is connected with the first connection 56A for fiber optic cables, and the optical receiver 53 is connected with the second connection 56B for fiber optic cables. The fiber optic cable 54 is connected with its ends with the first connection 56A for fiber optic cables and with the second connection 56B for fiber optic cables. Thus, the optical signal or the radiation, respectively, generated in the optical transmitter 52 is, via the first connection 56A for fiber optic cables, directly guided into the fiber optic cable 54 that guides the optical signal or the radiation, respectively, via the second connection 56B for fiber optic cables, directly to the optical receiver 53 that detects the optical signal.
The system 60 illustrated in
The embodiment illustrated in
In the embodiment illustrated in
Like the embodiment with a rear reflector illustrated in
One embodiment illustrated in
In the previous embodiments of the systems illustrated in
The system 80 illustrated in
The connection 86 for a bi-directional fiber optic cable is connected both with the optical transmitter 82 and with the optical receiver 83, and is suited, on the one hand, to guide optical signals from the transmitter 82 to its input/output and, on the other hand, to guide incoming optical signals from its input/output to the receiver 83.
The substantially planar reflector 84 is positioned close to the input/output of the connection 86 for a bi-directional fiber optic cable, so that an optical signal or radiation, respectively, emanating from the connection 86 is reflected directly back to the input/output of the connection 86 at the substantially planar reflector.
As results from
In the embodiment illustrated in
In one embodiment, a system includes an electrical Automatic Test Equipment (ATE) to perform, with a semiconductor device to be tested which includes, in addition to the above-mentioned optical interface, an electrical interface, a self test of the semiconductor device by using the electrical interface.
The electrical ATE then controls the above-mentioned test progression and collects the results of the test that is performed, as described further above, by using the BIST logic, the optical transmitter and receiver of the semiconductor device to be tested, and the system or means for returning the optical emission from the optical transmitter to the optical receiver.
The electrical ATE may, for instance, merely have the object of a flow control and error detection device (e.g., if the above-mentioned test response signals generated in reaction to the test input signals are compared with predetermined test response signals by the semiconductor device itself, in one embodiment the BIST logic), wherein the signals required for flow control or error detection may, for instance, be exchanged between the semiconductor device and the ATE via the above-mentioned electrical interface. In one embodiment, the test response signals generated during the performing of the above-mentioned tests—also including the optical interface—may be compared with predetermined test response signals also by the electrical ATE (wherein the above-mentioned test response signals generated in reaction to the above-mentioned test input signals may, for instance, be converted to electrical signals, be transmitted to the electrical ATE via the electrical interface, and be compared with the above-mentioned predetermined test response signals by the electrical ATE).
The above-mentioned semiconductor devices illustrated in
Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10 2007 009 878.4 | Feb 2007 | DE | national |
