Patent Application
20250218479
This application claims the benefit under 35 USC § 119 (a) of Korean Patent Application No. 10-2023-0197082, filed on Dec. 29, 2023 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference for all purposes.
The following description relates to a device and method with a multi-bit operation.
A neural network operation may include a multiply-accumulate (MAC) operation which repeats multiplication and addition. At a certain node of a neural network, an operation of employing a suitable active function after performing multiplication and addition on node values of a previous layer and weights that are mapped to the node values may be performed. To perform this operation, a memory access operation of loading a suitable input and weight at a desired time and a MAC operation of performing multiplication and addition on the loaded input and weight may be repeated. In addition, an operation on an input and a weight may be required in various fields other than a neural network. Instead of processing an operation for an input and a weight by using a generally known digital computer, a method may try to improve efficiency in performing the processing of the operation for an input and a weight by using a different hardware architecture.
This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.
In one or more general aspects, a multi-bit operation device includes a plurality of multi-bit cells, and a converter configured to convert second sum data into digital data, wherein the second sum data is generated by summing pieces of first sum data output from each of the plurality of multi-bit cells, and each of the plurality of multi-bit cells comprises a memory configured to store a weight resistance corresponding to a multi-bit weight, a current source configured to apply current to the memory such that a weight voltage is generated from the weight resistance, a plurality of multiplexers connected to one another in parallel and connected to the memory in series and each configured to output a signal of one of the weight voltage and a first fixed voltage, based on a multi-bit input, a plurality of capacitors connected respectively to the plurality of multiplexers and each configured to store a separate weight capacitance and generate charge data by performing an operation on the output signal and the weight capacitance, a bit line configured to output first sum data generated by summing pieces of charge data generated by each of the plurality of capacitors, and a switch of which an end is connected to the memory and an opposite end to the end is connected to the bit line.
The multi-bit operation device may include a weight calibration module configured to measure the weight voltage by controlling the switch.
The weight calibration module may be configured to control the switch to be in a first state, input the weight voltage, which is analog data, to the converter, convert the weight voltage into digital data, and measure the weight voltage converted into the digital data.
The weight calibration module may be configured to compare the measured weight voltage with a target voltage and determine whether there is an error.
The weight calibration module may be configured to, in response to determining that there is the error, calibrate the weight resistance to the target voltage.
The memory may include resistance elements of which the number corresponds to the number of bits of the multi-bit weight and that are connected to one another in series, and the multi-bit cell may be configured to control each of the resistance elements to be on/off and adjust the weight resistance.
The plurality of multiplexers may each receive an input of 1 or 0, and a multiplexer that receives 1 may be configured to output the weight voltage and a multiplexer that receives 0 may be configured to output the first fixed voltage among the plurality of multiplexers.
In response to the first fixed voltage being output from all the plurality of multiplexers, the multi-bit cell may be configured to control the current source to be off and reduce power consumption.
The size of a second fixed voltage that is relayed to an opposite end to an end of a capacitor to which the output signal is relayed may be the same as the size of the first fixed voltage, and a capacitor that receives the first fixed voltage among the plurality of capacitors and has the same potential at both ends of the capacitor may be configured to generate 0 C charge data in response to a 0 V voltage being applied to the capacitor.
The weight resistance may be set to linearly increase as the multi-bit weight increases, and the size of the second fixed voltage may be set such that a differential value from the weight voltage is proportional to the multi-bit weight.
The multi-bit cell may include the plurality of capacitors of which the number corresponds to the number of bits of the multi-bit input, and each of the plurality of capacitors may be configured to store a weight capacitance of a value corresponding to each digit of the multi-bit input.
A value of each digit of the multi-bit input may be input to a multiplexer connected to a capacitor corresponding to the digit.
The plurality of capacitors may be configured to receive the output signal at one end and receive a second fixed voltage at an opposite end to the end, perform a differential operation on the second fixed voltage with respect to the output signal, and generate the charge data by performing a multiplication operation on a value of the differential operation and the weight capacitance.
The memory may include a first memory and a second memory configured to store different weight resistances, the multi-bit cell further may include a sign multiplexer configured to determine, based on a sign input, one memory to which the current is to be applied between the first memory and the second memory, and a weight voltage may be generated from a weight resistance stored in the determined memory.
The memory may include a first memory configured to store a first weight resistance and a second memory configured to store a second weight resistance, the current source may include a first current source configured to apply current to the first memory to generate a first weight voltage and a second current source configured to apply current to the second memory to generate a second weight voltage, and each of the plurality of multiplexers may be configured to output one signal of the first weight voltage, the second weight voltage, and the first fixed voltage, based on the multi-bit input comprising a sign input.
In one or more general aspects, a multi-bit cell includes a memory configured to store a weight resistance corresponding to a multi-bit weight, a current source configured to apply current to the memory such that a weight voltage is generated from the weight resistance, a plurality of multiplexers connected to one another in parallel and connected to the memory in series and each configured to output a signal of one of the weight voltage and a first fixed voltage, based on a multi-bit input, a plurality of capacitors connected respectively to the plurality of multiplexers and each configured to store a separate weight capacitance and generate charge data by performing an operation on the output signal and the weight capacitance, a bit line configured to output first sum data generated by summing pieces of charge data generated by each of the plurality of capacitors, and a switch of which an end is connected to the memory and an opposite end to the end is connected to the bit line.
A multi-bit operation device may include a plurality of multi-bit cells comprising the multi-bit cell, and a converter configured to convert second sum data into digital data, wherein the second sum data is generated by summing pieces of first sum data output from each of the plurality of multi-bit cells.
In one or more general aspects, a multi-bit operation method includes generating a weight voltage from a weight resistance by applying current to a memory in which the weight resistance corresponding to a multi-bit weight is stored, receiving a multi-bit input for a plurality of capacitors each configured to store a separate weight capacitance, relaying one signal of the weight voltage and a first fixed voltage to each of the plurality of capacitors, based on the multi-bit input, generating charge data that is stored in each of the plurality of capacitors by performing an operation on the relayed signal and the weight capacitance, outputting first sum data generated by summing pieces of charge data generated by each of the plurality of capacitors through a bit line, and controlling a switch of which an end is connected to the memory and an opposite end to the end is connected to the bit line and measuring the weight voltage.
The measuring the weight voltage may include controlling the switch to be in a first state, inputting the weight voltage, which is analog data, to a converter, converting the weight voltage into digital data, and measuring the weight voltage converted into the digital data.
The multi-bit operation method may include comparing the measured weight voltage with a target voltage and determining whether there is an error.
The multi-bit operation method may include, in response to determining that there is the error, calibrating the weight resistance to the target voltage.
Other features and aspects will be apparent from the following detailed description, the drawings, and the claims.
Throughout the drawings and the detailed description, unless otherwise described or provided, the same drawing reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative size, proportions, and depiction of elements in the drawings may be exaggerated for clarity, illustration, and convenience.
The following detailed description is provided to assist the reader in gaining a comprehensive understanding of the methods, apparatuses, and/or systems described herein.
However, various changes, modifications, and equivalents of the methods, apparatuses, and/or systems described herein will be apparent after an understanding of the disclosure of this application. For example, the sequences within and/or of operations described herein are merely examples, and are not limited to those set forth herein, but may be changed as will be apparent after an understanding of the disclosure of this application, except for sequences within and/or of operations necessarily occurring in a certain order. As another example, the sequences of and/or within operations may be performed in parallel, except for at least a portion of sequences of and/or within operations necessarily occurring in an order, e.g., a certain order. Also, descriptions of features that are known after an understanding of the disclosure of this application may be omitted for increased clarity and conciseness.
Although terms such as “first,” “second,” and “third”, or A, B, (a), (b), and the like may be used herein to describe various members, components, regions, layers, or sections, these members, components, regions, layers, or sections are not to be limited by these terms. Each of these terminologies is not used to define an essence, order, or sequence of corresponding members, components, regions, layers, or sections, for example, but used merely to distinguish the corresponding members, components, regions, layers, or sections from other members, components, regions, layers, or sections. Thus, a first member, component, region, layer, or section referred to in the examples described herein may also be referred to as a second member, component, region, layer, or section without departing from the teachings of the examples.
Throughout the specification, when a component or element is described as “on,” “connected to,” “coupled to,” or “joined to” another component, element, or layer, it may be directly (e.g., in contact with the other component, element, or layer) “on,” “connected to,” “coupled to,” or “joined to” the other component element, or layer, or there may reasonably be one or more other components elements, or layers intervening therebetween. When a component or element is described as “directly on”, “directly connected to,” “directly coupled to,” or “directly joined to” another component element, or layer, there can be no other components, elements, or layers intervening therebetween. Likewise, expressions, for example, “between” and “immediately between” and “adjacent to” and “immediately adjacent to” may also be construed as described in the foregoing.
The terminology used herein is for describing various examples only and is not to be used to limit the disclosure. The articles “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As non-limiting examples, terms “comprise” or “comprises,” “include” or “includes,” and “have” or “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, but do not preclude the presence or addition of one or more other features, numbers, operations, members, elements, and/or combinations thereof, or the alternate presence of an alternative stated features, numbers, operations, members, elements, and/or combinations thereof. Additionally, while one embodiment may set forth such terms “comprise” or “comprises,” “include” or “includes,” and “have” or “has” specify the presence of stated features, numbers, operations, members, elements, and/or combinations thereof, other embodiments may exist where one or more of the stated.
Unless otherwise defined, all terms, including technical and scientific terms, used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains and based on an understanding of the disclosure of the present application. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the disclosure of the present application, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
As used herein, the term “and/or” includes any one and any combination of any two or more of the associated listed items. The phrases “at least one of A, B, and C”, “at least one of A, B, or C”, and the like are intended to have disjunctive meanings, and these phrases “at least one of A, B, and C”, “at least one of A, B, or C”, and the like also include examples where there may be one or more of each of A, B, and/or C (e.g., any combination of one or more of each of A, B, and C), unless the corresponding description and embodiment necessitates such listings (e.g., “at least one of A, B, and C”) to be interpreted to have a conjunctive meaning.
The features described herein may be embodied in different forms, and are not to be construed as being limited to the examples described herein. Rather, the examples described herein have been provided merely to illustrate some of the many possible ways of implementing the methods, apparatuses, and/or systems described herein that will be apparent after an understanding of the disclosure of this application. The use of the term “may” herein with respect to an example or embodiment (e.g., as to what an example or embodiment may include or implement) means that at least one example or embodiment exists where such a feature is included or implemented, while all examples are not limited thereto. The use of the terms “example” or “embodiment” herein have a same meaning (e.g., the phrasing “in one example” has a same meaning as “in one embodiment”, and “one or more examples” has a same meaning as “in one or more embodiments”).
The examples may be implemented as various types of products, such as, for example, a personal computer (PC), a laptop computer, a tablet computer, a smartphone, a television (TV), a smart home appliance, an intelligent vehicle, a kiosk, and a wearable device. Hereinafter, examples will be described in detail with reference to the accompanying drawings. In the drawings, like reference numerals are used for like elements.
Various attempts have continued to develop a computing device for efficiently processing a vast volume of information by simulating a biological neuron or a biological neural network that is formed of biological neurons connected to one another. The operation of a biological neuron may be simulated through a node model 11. The node model 11 may be an example of a neuromorphic operation that is executed by a hardware operation device or a hardware operation processor. The node model 11 may include a multiplication operation that multiplies a synaptic weight by information from multiple nodes, an addition operation Σ for values w0x0, w1x1, and w2x2 which a synaptic weight has been multiplied, and an operation of applying a characteristic function b and an activation function f to an addition operation result. The execution of a neuromorphic operation may provide a neuromorphic operation result. Here, values x0, x1, x2, . . . , etc. may correspond to axon values and values w0, w1, w2, . . . , etc. may correspond to synaptic weights.
In the neural network 20, nodes of layers except for an output layer may be connected to nodes of a subsequent layer via links for transmitting an output signal. An output of an activation function for weighted inputs of nodes included in a previous layer may be input to the nodes via the links. The weighted inputs may be obtained by multiplying weights by inputs (node values) of the nodes, the weights may be synaptic weights, and the inputs may be axon values. The weights may be referred to as parameters of the neural network 20. The activation function may include sigmoid, hyperbolic tangent (tan h), and rectified linear unit (ReLU) and may form a nonlinearity in the neural network 20.
An output of a node 22 included in this neural network 20 may be represented by Equation 1 below, for example.
Equation 1 may represent an output value yi of an ith node 22 for m input values in a layer. xj denotes an output value of a jth node of a previous layer. wj,i denotes a weight applied to the output value of the jth node of the previous layer and the ith node 22 of the current layer. f( ) denotes an activation function. As shown in Equation 1, a multiply-accumulate (MAC) result of the input value xj and the weight wj,i may be used for the activation function. In other words, an operation (MAC operation) of multiplying and adding the appropriate input value xj and weight wj,i at a desired time may be repeated. Besides the above, there are various application fields implementing MAC operations, and a multi-bit operation device for processing the MAC operations in an analog area may be used for those fields.
Here,
Referring to
The multi-bit cells included in the multi-bit operation device 30 are unit circuits that receive multi-bit inputs. The number of multi-bit cells connected in parallel is not particularly limited, and it may be a power of two, for example. However, the structure of three multi-bit cells connected in parallel is provided as an example herein for ease of description.
The multi-bit operation device 30 illustrated in
The resistance values of the multi-bit cells for the electric power source may be determined based on inputs X1, X2, X3 and weights W11, W21, W31, which are applied respectively to the multi-bit cells. The inputs and weights may be a multi-bit. Here, the input X1 may refer to the output value of the first node (e.g., the first layer) or a node value thereof, which is an input applied to the first multi-bit cell. Likewise, the inputs X2 and X3 may refer to inputs or node values of the second and third nodes, which are inputs applied to the second and third multi-bit cells, respectively. The left ‘1’ in the weight ‘W11’ may refer to the first node of the first layer and the right ‘1’ therein may refer to the first node of the second layer. The weight W11 may be a weight for a link between the first node of the first layer and the first node of the second layer, which is a weight applied to the first multi-bit cell. Likewise, the weights W21 and W31 may be weights applied to the second and third multi-bit cells, respectively.
Referring to
The memory 110 may store a multi-bit weight in a resistance form. The multi-bit weight stored in the memory 110 in a resistance form may be referred to as a weight resistance. When the multi-bit weight is 3 and a resistance corresponding to the multi-bit weight is 12 kΩ, the memory 110 may store the multi-bit weight that is 3 in the form of a 12 kΩ weight resistance. For example, the memory 110 may be a non-volatile memory, such as resistive random-access memory (ReRAM), phase-change memory (PCM), and/or magnetic RAM (MRAM). However, the types of the memory 110 described above are just examples, and the memory 110 may include any forms that may store resistance information without limit.
The current source 120 may apply a current to the memory 110. The current source 120 may apply a constant size of current to the memory 110 regardless of the size of voltage or resistance. For example, the current source 120 may apply a direct-current bias current, which sets an operating point of the multi-bit cell 100. Even when the size of the current applied to the memory 110 is the same, the voltage of the memory 110 may vary depending on the size of the resistance of the memory 110. As the current source 120 applies the current to the memory 110, a weight voltage may be generated from the weight resistance stored in the memory 110. The weight voltage may be generated with the current being multiplied by the weight resistance by Ohm's law. An example of the weight voltage is described in detail below with reference to
The multi-bit cell 100 may receive a multi-bit input. The multi-bit input may include a plurality of inputs, unlike a 1-bit input that is only expressed by 1 or 0. For example, the multi-bit input may be formed of values of respective digits expressing the multi-bit input. In the case of a 3-bit input, the multi-bit input may be expressed by 3′b101 and may be formed of ‘1’ of a 2-2 digit, ‘0’ of a 21 digit, and ‘1’ of a 20 digit. In this case, ‘1’, ‘0’ and ‘1’ may correspond respectively to values of the inputs included in the multi-bit input. The number of multi-bit weights may be the same as the number of bits of the multi-bit input.
A multiplexer 131 may receive the weight voltage by being connected to the memory 110 in series and may receive a fixed voltage through another line. The fixed voltage may be a constant size of voltage that is fixedly applied to the multiplexer 131. In addition, the multiplexer 131 may receive one of the plurality of inputs forming the multi-bit input. Based on the received input, the multiplexer 131 may output a signal of the weight voltage and the fixed voltage. For example, the multiplexer 131 may output the weight voltage when receiving 1 and may output the fixed voltage when receiving 0. An example of this is described in detail below with reference to
There may be the plurality of multiplexers 130 connected to one another in parallel. The plurality of multiplexers 130 may be connected to the memory 110 in series and may all receive the same signal (the weight voltage and the fixed voltage). The plurality of multiplexers 130 may receive the multi-bit input and may each output a signal of the weight voltage and the fixed voltage, based on the received multi-bit input. A signal that is output, of the weight voltage and the fixed voltage, from each multiplexer may be determined according to a value of a received input. For example, when the multi-bit input is 3′b101, a multiplexer having received ‘1’ of the 2-2 digit and a multiplexer having received ‘1’ of the 20 digit may output the same signal and a multiplexer having received ‘0’ of the 21 digit may output a different signal.
The capacitor 141 may be connected to the multiplexer 131 and may receive a signal output from the multiplexer 131. The capacitor 141 may store a weight capacitance. The capacitor 141 may generate charge data by performing an operation on the received signal and the weight capacitance. An example of the operation in the capacitor 141 is described in detail below with reference to
There may be a plurality of capacitors 141 connected to one another in parallel. The capacitors 140 may be connected respectively to the plurality of multiplexers 130 in series. Accordingly, one capacitor 141 may be connected to one multiplexer 131. The plurality of capacitors 140 may each store a separate weight capacitance. The weight capacitances may be different for capacitors, may be all the same, or may only be partially different.
As described below, process variation during a semiconductor process may cause an error in a weight resistance value. The multi-bit cell 100 according to one or more embodiments may include a switch 160 to detect and correct an error in a weight resistance value.
Referring to
Only the components related to the present embodiments are shown in the circuit diagram illustrated in
Referring to the circuit diagram of
The signal output from the multiplexer 131 may be relayed to the capacitor 141. The signal output from the multiplexer 131 may be relayed to the left end of the capacitor 141, and the second fixed voltage may be relayed to the right end of the capacitor 141. Accordingly, a voltage having a potential difference between the signal output from the multiplexer 131 and the second fixed voltage may be applied to the capacitor 141. Hereinafter, an example of the operation method of the multi-bit input 150 and a multi-bit weight is described in detail.
The memory 110 may store a weight resistance corresponding to the multi-bit weight. A value of the weight resistance corresponding to each value of the multi-bit weight may vary. The weight resistance may be set to linearly increase as the multi-bit weight increases. For example, the weight resistance may increase by a constant difference as the multi-bit weight increases by a constant difference, like an isometric sequence. An example of the weight resistance for a 3-bit weight may be represented by Table 1 below.
The multi-bit cell 100 may generate a weight voltage from the weight resistance by the current source 120 applying a current to the memory 110. When the current is applied to the weight resistance stored in the memory 110, the current and the weight resistance may be multiplied according to Ohm's law, and as a result, the weight voltage may be generated. Since the current source 120 may output a constant size of current, the weight voltage may be proportional to the weight resistance. An example of the weight voltage for the 3-bit weight may be represented by Table 2 below.
The multi-bit cell 100 may receive the multi-bit input 150 by using the plurality of capacitors 140 that receive a 1-bit input 151. The number of capacitors 140 and the weight capacitance may be set to receive the multi-bit input 150.
For example, the number of capacitors 140 of the multi-bit cell 100 may correspond to the number of bits of the multi-bit input 150, and each of the capacitors 140 may store a value of the weight capacitance corresponding to each digit of the multi-bit input 150. When the multi-bit input 150 is a 3-bit input, the multi-bit input 150 may be expressed by 3′b000 to 3′b111, and respective digits of the multi-bit input 150 may be 20, 21, and 22. In this case, the multi-bit cell 100 may include three capacitors 140 and the capacitors 140 may respectively store 20 times of a unit capacitance, 21 times of the unit capacitance, and 22 times of the unit capacitance. Referring to
The capacitors 140 may indirectly receive the multi-bit input 150 through the plurality of multiplexers 130. As described above, the multi-bit input 150 may include the plurality of inputs, and each of the inputs may be received by a multiplexer connected to a corresponding capacitor. A value of each digit of the multi-bit input 150 may be input to a multiplexer connected to a capacitor corresponding to the value of each digit. For example, when the multi-bit input 150 is a 3-bit input, a 20-digit value of the multi-bit input 150 may be input to a capacitor CAP0 that stores a capacitance weight of one time the unit capacitance, a 21-digit value of the multi-bit input 150 may be input to a capacitor CAP1 that stores a capacitance weight of 2 times the unit capacitance, and a 22-digit value of the multi-bit input 150 may be input to a capacitor CAP2 that stores a capacitance weight of 4 times the unit capacitance, indirectly. Since the value of each digit of the multi-bit input 150 may be input directly to the multiplexer, and a signal output from the multiplexer based on the input is relayed to the capacitor, the value of each digit may be input indirectly to the capacitor.
When the multi-bit input 150 is 3′b110 (or 6), 1 may be input to a multiplexer corresponding to the capacitor CAP2, 1 may be input to a multiplexer corresponding to the capacitor CAP1, and 0 may be input to a multiplexer corresponding to the capacitor CAP0. An example of a value input to a multiplexer according to a value of the 3-bit multi-bit input 150 is shown in Table 3 below.
As such, the plurality of multiplexers 130 may each receive an input of 1 or 0. A multiplexer that receives 1 among the plurality of multiplexers 130 may output the weight voltage and a multiplexer that receives 0 among the plurality of multiplexers 130 may output the first fixed voltage. However, this is just an example and may be performed vice versa or may be performed variously depending on the settings of the multiplexers. For example, the multiplexers may receive different types of an input or may determine a signal to be output based on a plurality of inputs. An example of the signal relayed to each capacitor from the plurality of multiplexers 130 according to the example of Table 3 is shown in Table 4 below.
The capacitor 141 may receive a signal output from the multiplexer 131 at one end and may receive a second fixed voltage at the opposite end to the end. The capacitor 141 may perform a differential operation on the second fixed voltage with respect to the signal output from the multiplexer 131. Accordingly, the capacitor 141 may perform a differential operation on the second fixed voltage with respect to the weight voltage or the first fixed voltage. A differential value may be a potential difference between both ends of the capacitor 141 and may be a voltage applied to the capacitor 141. For example, when the first fixed voltage is set to have the same value as the second fixed voltage, a differential value of the second fixed voltage for the first fixed voltage may be 0 V. However, the first fixed voltage and the second fixed voltage may be set to have different values depending on the structure and setting of the multi-bit cell 100. In this case, the differential value may be a value other than 0 V.
The size of the second fixed voltage may be set such that a differential value with the weight voltage is proportional to the multi-bit weight. In the example of Table 2, the second fixed voltage may be 525 mV, which is an average value of weight voltage values. A relationship between the weight voltage, the second fixed voltage, and a differential value of the second fixed voltage for the weight voltage may be summarized as shown in Table 5 below, for example.
As shown in Table 5, the size of the second fixed voltage may be set such that the differential value is proportional to the multi-bit weight. In the example of Table 5, the first fixed voltage may also be set equivalent to the second fixed voltage.
Table 6 above, for example, shows the multi-bit input 150 set for each of the plurality of multi-bit cells 100 according to the example of Table 2, the multi-bit weight, the weight voltage according to the multi-bit weight, and the differential value of the second fixed voltage for the weight voltage.
The values of the multi-bit input 150 and the multi-bit weight as shown in Table 6 are set randomly based on 3 bits and may vary. One row of Table 6 may correspond to one multi-bit cell 100. Accordingly, Table 6 shows the results of 16 multi-bit cells 100.
Since the first fixed voltage may be set equivalent to the second fixed voltage, a capacitor that receives the first fixed voltage among the capacitors 140 may have the same potential at both ends, and a potential difference may be 0 V. In this case, the capacitor may receive a 0 V voltage and may generate 0 C charge data.
Table 7 below, for example, shows a differential value operated in each capacitor of the multi-bit cells 100 according to the examples of the tables shown above, which is a potential difference at both ends of each capacitor.
The capacitor 141, by multiplying the differential value by the weight capacitance, may generate charge data. In other words, the capacitor 141, by multiplying the differential value (voltage) by the weight capacitance according to operation Q=C×V, may generate the charge data.
Table 8 below, for example, shows the charge data generated in each capacitor according to the example of Table 7.
) (mC)
indicates data missing or illegible when filed
The multi-bit cell 100 may output first sum data generated by summing the charge data generated by each of the capacitors 140. In the example of Table 8, the multi-bit cell 100 corresponding to row 1 may output the first sum data of −100 mC, and the multi-bit cell 100 corresponding to row 4 may output the first sum data of 1,225 mC. The first sum data of each row may all be summed up and converted into a digital signal. An example of this is described below with reference to
On the other hand, by comparing a multiplication result of the multi-bit input 150 and the multi-bit weight with the first sum data, an operation method of the multi-bit cell 100 may be verified. The multiplication of multi-bit input 150 of row 1 and the multi-bit weight is −4, and the multiplication of the multi-bit input 150 of row 4 and the multi-bit weight is 49. Referring to Table 5, it is confirmed that the differential value of the second fixed voltage for the weight voltage is 25 times the multi-bit input 150. Here, since the first sum data of row 1 is −4×25 mC and the first sum data of row 4 is 49×25 mC, it is confirmed that the first sum data corresponds to the multiplication results described above.
Without performing a multiplication operation on the multi-bit input 150 and the multi-bit weight directly, through the plurality of capacitors 140 that store individual capacitance weights, the multi-bit cell 100 may perform a multi-bit operation by converting the multi-bit weight into the voltage weight.
As described above, process variation during a semiconductor process may cause an error in a weight resistance value. Graph 510 shows a MAC calculation error that occurs when performing a MAC operation through a multi-bit operation device of a 64×64 array including a multi-bit cell where a weight resistance has not been calibrated. Graph 510 shows that a 0.8˜3.2 LSBrms-level of a MAC calculation error occurs.
When the multi-bit operation device has a structure where 8 columns (e.g., columns 1-8, columns 9-16, . . . columns 57-64) share an analog-to-digital converter (ADC) with one capacitor set and has programmed the same weight (e.g., the weight of columns 1-12 is the same as the weight of columns 13-24) in a 12-column unit, a different MAC calculation error by each column is only due to an error of a weight value. Accordingly, the multi-bit cell 100 according to one or more embodiments may accurately program weight values to improve the accuracy of calculations.
Referring to
Referring to
Referring to
The number of the resistance elements 111 of the memory 110 may correspond to the number of bits of a multi-bit weight. For example, when the multi-bit weight is an N-bit weight, the memory 110 may include 2N−1 resistance elements 111. The multi-bit weight in one or more embodiments of
The resistance elements 111 may be connected to one another in series. A resistance element 111a may store two resistance values, and the memory 110 may represent 2N resistance values by using 2N−1 resistance elements 111 connected in series. The multi-bit cell 100 may control each of the resistance elements 111 to be on/off and may adjust a weight resistance. The multi-bit cell 100 may determine turning on/off each resistance element through a WR_SEL signal and may apply a current or a voltage to each resistance element through a Sub Bit-line[7:0] signal line.
For example, when the multi-bit weight corresponds to the weight resistance as shown in the example of Table 1, one resistance element may store 7 kΩ and the remaining resistance elements may store 1 kΩ, or each of the resistance elements may store 1 kΩ or 2 kΩ. The multi-bit cell 100 may control the resistance elements 111 connected in series to be on/off to store one weight resistance among 7 kΩ, 8 kΩ, 9 kΩ, 10 kΩ, 11 kΩ, 12 kΩ, 13 kΩ, and 14 kΩ in the memory 110. Accordingly, the weight resistances from 7 kΩ to 14 kΩ in a 1 kΩ unit may be expressed from the memory 110.
The resistance element 111a may be a magnetic tunnel junction (MTJ) or MRAM. However, the foregoing examples are just examples, and elements that store a resistance and are controlled by a transistor may be a resistance element without limit.
Referring to
For example, when the multi-bit input 150 is 0, the weight voltage is not used in the multi-bit cell 100, and only the first fixed weight may be applied to the plurality of multiplexers 130. When all individual inputs 151 included in the multi-bit input 150 are 0, the multi-bit input 150 may be 0. When the multi-bit input 150 is a 3-bit input, the multi-bit input 150 that is 0 may be expressed by 3′b000. The plurality of multiplexers 130 may all receive an input of 0. The plurality of multiplexers 130 may output the first fixed voltage in response to the input of 0. Since the weight voltage is not relayed to the capacitors 140, the current source 120 may not need to operate to generate the weight voltage. Accordingly, the multi-bit cell 100 according to one or more embodiments, by controlling the current source 120 to be off, may reduce power consumption of the multi-bit cell 100. For example, the multi-bit cell 100 may control a current applied from the current source 120 to be 0 μA by using an I_EN signal, which is an enable signal that controls the current source 120.
However, all the plurality of multiplexers 130 may output the first fixed voltage in various cases other than the multi-bit input 150 being 0 depending on the structure and setting of the multi-bit cell 100. When the first fixed voltage is output from all the plurality of multiplexers 130, the weight voltage is not used in the multi-bit cell 100, and thus, the current source 120 may be controlled to be off and the multi-bit cell 100 according to one or more embodiments may reduce power consumption of the multi-bit cell 100.
Referring to
The number of capacitors 140 of the multi-bit cell 100 may correspond to the number of bits of the multi-bit input 150. For example, the multi-bit cell 100 may include 2N−1 capacitors 140 for an N-bit multi-bit input 150. In this case, the weight capacitance stored in the capacitors 140 may all be the unit capacitance. The 2N−1 capacitors 140 may receive the multi-bit input 150 having values of 0 to 2N−1.
In the structure of one or more embodiments of
Referring to
The weight resistances of the first memory 110a and the second memory 110b may have different signs of the same absolute value, different values of the same sign, or may be set variously. The sign multiplexer 132 may be connected to the first memory 110a and the second memory 110b. The multi-bit cell 100 may also receive the sign input 152 other than the multi-bit input 150 through the sign multiplexer 132. The sign multiplexer 132, based on the sign input 152, may determine one memory 110, of the first memory 110a and the second memory 110b, to which a current from the current source 120 is to be applied. The sign multiplexer 132 may connect the memory 110 that has been determined to receive the current to a line from the current source 120. The multi-bit cell 100, based on the sign input 152, may generate a weight voltage from the weight resistance stored in the determined memory 110.
The multi-bit cell 100, by including a plurality of memories 110 which store different weight resistances, may receive further various inputs and may perform operations on various weights. When the resistance weight of the first memory 110a is a positive number and the resistance weight of the second memory 110b is a negative number, the multi-bit cell 100 may receive a signed integer input and may perform an operation on the signed integer input.
Referring to
The first memory 110a may store a first weight resistance and the second memory 110b may store a second weight resistance. The first weight resistance and the second weight resistance may have different signs of the same absolute value, different values of the same sign, or may be set variously.
The first current source 120a and the second current source 120b may apply the same size of current. The first current source 120a may apply a current to the first memory 110a to generate the first weight voltage and the second current source 120b may apply a current to the second memory 110b to generate the second weight voltage.
Each of the plurality of multiplexers 130 may output one signal of the first weight voltage, the second weight voltage, and the first fixed voltage, based on the multi-bit input 150 including a sign input. For example, the multiplexer 131 may output the first fixed voltage when the absolute value of an input is 0 and may determine one signal of the first weight voltage and the second weight voltage, based on the sign input, when the absolute value of the input is 1.
The multi-bit cell 100, by including a plurality of memories 110 which store different weight resistances, may receive further various inputs and may perform operations on various weights. When the resistance weight of the first memory 110a is a positive number and the resistance weight of the second memory 110b is a negative number, the multi-bit cell 100 may receive a signed integer input and may perform an operation on the signed integer input.
Referring to
In operation 1110, the multi-bit cell may generate a weight voltage from a weight resistance by applying a current to a memory that stores the weight resistance corresponding to a multi-bit weight.
The number, corresponding to the number of bits of the multi-bit weight, of resistance elements of the memory may connected to one another in series. The multi-bit cell may control each of the resistance elements to be on/off and may adjust the weight resistance.
The weight resistance may be set to increase linearly as the multi-bit weight increases.
In operation 1120, the multi-bit cell may receive a multi-bit input for a plurality of capacitors that each store a separate weight capacitance.
A value of each digit of the multi-bit input may be input to a multiplexer connected to a capacitor corresponding to the digit.
In operation 1130, the multi-bit cell may relay one signal of the weight voltage and a first fixed voltage to each of the plurality of capacitors, based on the multi-bit input.
A plurality of multiplexers may each receive an input of 1 or 0, and a multiplexer that receives 1 may output the weight voltage and a multiplexer that receives 0 may output the first fixed voltage among the plurality of multiplexers.
When the multi-bit input is 0, the plurality of multiplexers may all output the first fixed voltage and the multi-bit cell may control a current source to be off to reduce power consumption.
The size of a second fixed voltage relayed to the opposite end to one end of a capacitor to which the output signal is relayed may be the same as the size of the first fixed voltage and may be set such that a differential value of the second fixed voltage with the weight voltage is proportional to the multi-bit weight.
The multi-bit cell may include the capacitors of which the number corresponds to the number of bits of the multi-bit input, and each of the capacitors may store a weight capacitance of a value corresponding to each digit of the multi-bit input.
In operation 1140, the multi-bit cell may generate charge data that is stored in each of the plurality of capacitors by performing an operation on the relayed signal and the weight capacitance.
A capacitor that receives the first fixed voltage among the plurality of capacitors may have the same potential at both ends of the capacitor and may thus generate 0 C charge data when a 0 V voltage is applied to the capacitor.
The plurality of capacitors may receive the output signal at one end and receive a second fixed voltage at the opposite end to the end, may perform a differential operation on the second fixed voltage with respect to the output signal, and may generate the charge data by performing a multiplication operation on a differential value and the weight capacitance.
In operation 1150, the multi-bit cell may output first sum data generated by summing the charge data generated by each of the plurality of capacitors.
In one or more embodiments, the memory may include a first memory and a second memory which store different weight resistances. The multi-bit cell may further include a sign multiplexer that determines one memory to which a current is applied of the first memory and the second memory, based on a sign input. The multi-bit cell may generate the weight voltage from the weight resistance stored in the determined memory.
In another embodiment, the memory may include the first memory that stores a first weight resistance and the second memory that stores a second weight resistance. The current source may include a first current source and a second current source which apply the same size of current. The first current source may apply a current to the first memory to generate a first weight voltage and the second current source may apply a current to the second memory to generate a second weight voltage. Each of the plurality of multiplexers may output one signal of the first weight voltage, the second weight voltage, and the first fixed voltage, based on the multi-bit input including a sign input.
In operation 1160, the multi-bit cell may measure the weight voltage by controlling a switch. The end of the switch may be connected to the memory and the opposite end of the end of the switch may be connected to a bit line.
Referring to
The multi-bit operation device 1200 may include the plurality of multi-bit cells 200. The multi-bit operation device 1200 may generate second sum data by summing pieces of first sum data output from each of the multi-bit cells 200. The multi-bit operation device 1200 may output the second sum data and may input the second sum data to the converter 300. The converter 300 may convert the second sum data, which is analog data, into digital data.
The weight calibration module 400 may measure a weight voltage by controlling a switch. The term “module” used herein may be a unit including one or a combination of two or more of hardware, software, and firmware. The term “module” may be used interchangeably with other terms, for example, “unit”, “logic”, “logical block”, “component”, or “circuit”. The “module” may be a minimum unit of an integrally formed component or part thereof. The “module” may be a minimum unit for performing one or more functions or part thereof. The “module” may be implemented mechanically or electronically. For example, the “module” may include at least one of an application-specific integrated circuit (ASIC) chip, a field-programmable gate array (FPGA), and/or a programmable-logic device for performing certain operations that are well known or to be developed in the future.
The weight calibration module 400 may control the switch to be in a first state (e.g., a on state), may input the weight voltage, which is analog data, to the converter, may convert the weight voltage into digital data, and may measure the weight voltage converted into the digital data. The weight calibration module 400 may compare the measured weight voltage with a target voltage and may determine whether there is an error. For example, when the difference between the measured weight voltage and the target voltage exceeds a predetermined threshold, the weight calibration module 400 may determine that the measured weight voltage has an error. The weight calibration module 400, when determining that there is an error, may calibrate the weight resistance to the target voltage.
Referring to
The multi-bit operation device 1200 may convert second sum data, which is analog data, into digital data. The multi-bit operation device 1200 may input the second sum data to the comparator 310 to convert the second sum data into digital data. The comparator 310 may store pieces of data into which ranges of a minimum value to a maximum value of the second sum data are divided by a certain number and may classify the second sum data based thereon. The comparator 310 may output data indicating a certain range to which a value of the second sum data among the ranges divided by the certain number belongs.
The SAR logic 330 may convert data that is relayed from the comparator 310 based on reference voltage data that is relayed from the reference voltage cells 320 into digital data. The SAR logic 330 may compare the size of the data relayed from the comparator 310 with the size of the reference voltage data and may perform digital conversion on the data. For example, the SAR logic 330 may perform the digital conversion on the data by repeating a method of maintaining a bit value when the data relayed from the comparator 310 is greater than the reference voltage data and deleting the bit value when the data relayed from the comparator 310 is less than the reference voltage data.
On the other hand, the circuit diagram of the multi-bit operation device illustrated in
As illustrated in
A sample voltage may be applied to a multi-bit cell and a multi-bit input may be received during the multi-bit operation time such that the multi-bit operation is performed in the multi-bit cell. When each of multi-bit cells outputs the first sum data, the multi-bit operation device may sum pieces of the first sum data and may generate the second sum data.
The sample voltage applied to the multi-bit cell is off during the digital conversion time and a converter including an SAR logic may operate. The converter may convert the second sum data, which is analog data, into digital data.
Referring to
In operation 1510, each of a plurality of multi-bit cells may output first sum data.
In operation 1520, the multi-bit operation device may output second sum data generated by summing pieces of the first sum data output from each of the plurality of multi-bit cells.
In operation 1530, the multi-bit operation device may convert the second sum data, which is analog data, into digital data.
The multi-bit operation device may include a converter that converts second sum data, which is analog data, into digital data. The converter may include a plurality of reference voltage cells and an SAR logic.
Referring to
Each of the multi-bit operation devices 1100a to 1100n may generate and output digital data by converting second sum data output from multi-bit cells. The multi-bit operation device array 1600 may output the final operation result of an input to the multi-bit operation device array 1600 by combining pieces of digital data 301a to 301n output respectively from the multi-bit operation devices 1100a to 1100n. The multi-bit operation device array 1600 may correspond to, for example, the neural network 20 of
Referring to
In addition to the multi-bit operation device 1730, the electronic system 1700 may include a central processing unit (CPU) 1710 (e.g., one or more processors), RAM 1720, an external memory 1740 (e.g., one or more memories), a sensor module 1750, and a communication module (or a Tx/Rx module) 1760. Additionally, the electronic system 1700 may further include an input/output module, a security module, a power control device, and the like. A portion of hardware components of the electronic system 1700 may be mounted to a semiconductor chip. The multi-bit operation device 1730 may be an implementation of the multi-bit operation device described above with reference to the drawings in an on-chip type or may be an apparatus including the multi-bit operation device described above with reference to the drawings as a part thereof.
The CPU 1710 controls the overall operation of the electronic system 1700. The CPU 1710 may include a single processor core (single core) or a plurality of processor cores (multi-core). The CPU 1710 processes or executes programs and/or data stored in the external memory 1740. For example, the external memory 1740 may include a non-transitory computer-readable storage medium storing instructions that, when executed by the CPU 1710, configure the CPU 1710 to perform any one, any combination, or all of the operations and/or methods described above with reference to
The RAM 1720 may store programs, data, or instructions temporarily. For example, the programs and/or the data stored in the memory 1740 may be temporarily stored in the RAM 1720 according to control by the CPU 1710 or booting code. The RAM 1720 may be implemented as a memory device, such as dynamic RAM (DRAM) or static RAM (SRAM).
The multi-bit operation device 1730 may perform a multi-bit operation based on received input data and may generate an information signal based on a performing result. The multi-bit operation device 1730 may be used as a neuromorphic device or a neural network device. A neural network may include a convolutional neural network (CNN), a recurrent neural network (RNN), a deep belief network (DBN), a restricted Boltzmann machine (RBM), and the like, but examples are not limited thereto. The multi-bit operation device 1730 may be a hardware accelerator dedicated for the neural network. On the other hand, the multi-bit operation device 1730 may be applied to various systems that implement an operation for a multi-bit input and a multi-bit weight, besides the neuromorphic or neural network.
The information signal may include one of various types of recognition signals, such as a voice recognition signal, an object recognition signal, a video recognition signal, and a biological information recognition signal. For example, the multi-bit operation device 1730 may receive, as input data, frame data included in a video stream and may generate a recognition signal about an object included in an image represented by the frame data. The multi-bit operation device 1730 may receive various types of input data depending on the type or function of the electronic device to which the electronic system 1700 is mounted and may generate a recognition signal according to the input data.
The external memory 1740 may be a storage configured to store data and may store an operating system (OS), various types of programs, and various types of data. The external memory 1740 may include a volatile memory and/or a non-volatile memory. The non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable ROM (EEPROM), flash memory, phase-change RAM (PRAM), MRAM, resistive RAM (RRAM), ferroelectric RAM (FeRAM), and the like. The volatile memory may include DRAM, SRAM, synchronous DRAM (SDRAM), PRAM, MRAM, RRAM, FeRAM, and/or the like. The external memory 1740 may include, for example, hard disk drives (HDDs), solid state drives (SSDs), compact flash (CF) memory, secure digital (SD) memory, micro-SD memory, mini-SD memory, extreme digital (xD) memory, and/or memory sticks.
The sensor module 1750 may collect information around the electronic device to which the electronic system 1700 is mounted. The sensor module 1750 may sense or receive a signal (e.g., an image signal, a voice signal, a magnetic signal, a biosignal, a touch signal, etc.) from the outside of the electronic device and may convert the sensed or received signal into data. In this case, the sensor module 1750 may be various types of sensing devices, such as a microphone, an imaging device, an image sensor, a light detection and ranging (LiDAR) sensor, an ultrasonic sensor, an infrared sensor, a biosensor, or a touch sensor.
The sensor module 1750 may provide the data to the multi-bit operation device 1730 as input data. For example, the sensor module 1750 may include an image sensor, may generate a video stream by capturing an external environment of the electronic device, and may sequentially provide consecutive data frames of the video stream as input data to the multi-bit operation device 1730. However, examples are not limited thereto, and the sensor module 1750 may provide various types of data to the multi-bit operation device 1730.
The communication module 1760 may include various types of wired or wireless interfaces configured to communicate with an external apparatus. For example, the communication module 1760 may include a wired local area network (LAN), a wireless local area network (WLAN), such as wireless fidelity (Wi-Fi), a wireless personal area network (WPAN), such as Bluetooth, a wireless universal serial bus (USB), ZigBee, near field communication (NFC), radio-frequency identification (RFID), power line communication (PLC), a communication interface accessible to a mobile cellular network, such as 3rd generation (3G), 4th generation (4G), long term evolution (LTE), or 5th generation (5G), and the like.
The electronic system 1700 may further include a user interface device, such as a touch panel, a key, or a button, other than a memory device that stores and executes program data, a permanent storage, such as a disk drive, and a communication port that communicates with an external apparatus. The methods implemented in a software module or an algorithm may be computer-readable code or program instructions that may be executed in a processor, which may be stored in a computer-readable storage medium.
On the other hand, the operating methods described with reference to
The multi-bit operation devices, multi-bit cells, memories, resistance elements, current sources, multiplexers, capacitors, switches, converters, weight calibration modules, comparators, reference voltage cells, SAR logics, multi-bit operation device arrays, electronic systems, CPUs, RAMs, external memories, sensor modules, Tx/Rx modules, multi-bit operation device 30, multi-bit cell 100, memory 110, first memory 110a, second memory 110b, resistance elements 111, resistance element 111a, current source 120, first current source 120a, second current source 120b, multiplexers 130, multiplexer 131, capacitors 140, capacitor 141, switch 160, multi-bit operation device 1200, multi-bit cells 200, converter 300, weight calibration module 400, comparator 310, reference voltage cells 320, SAR logic 330, multi-bit operation device array 1600, multi-bit operation devices 1100a to 1100n, converters 300a to 300n, electronic system 1700, CPU 1710, RAM 1720, multi-bit operation device 1730, external memory 1740, sensor module 1750, and Tx/Rx module 1760 described herein, including descriptions with respect to respect to
The methods illustrated in, and discussed with respect to,
Instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above may be written as computer programs, code segments, instructions or any combination thereof, for individually or collectively instructing or configuring the one or more processors or computers to operate as a machine or special-purpose computer to perform the operations that are performed by the hardware components and the methods as described above. In one example, the instructions or software include machine code that is directly executed by the one or more processors or computers, such as machine code produced by a compiler. In another example, the instructions or software includes higher-level code that is executed by the one or more processors or computer using an interpreter. The instructions or software may be written using any programming language based on the block diagrams and the flow charts illustrated in the drawings and the corresponding descriptions herein, which disclose algorithms for performing the operations that are performed by the hardware components and the methods as described above.
The instructions or software to control computing hardware, for example, one or more processors or computers, to implement the hardware components and perform the methods as described above, and any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media, and thus, not a signal per se. As described above, or in addition to the descriptions above, examples of a non-transitory computer-readable storage medium include one or more of any of read-only memory (ROM), random-access programmable read only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROMs, CD-Rs, CD+Rs, CD-RWs, CD+RWs, DVD-ROMs, DVD-Rs, DVD+Rs, DVD-RWs, DVD+RWs, DVD-RAMs, BD-ROMs, BD-Rs, BD-R LTHs, BD-REs, blue-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), flash memory, a card type memory such as multimedia card micro or a card (for example, secure digital (SD) or extreme digital (XD)), magnetic tapes, floppy disks, magneto-optical data storage devices, optical data storage devices, hard disks, solid-state disks, and/or any other device that is configured to store the instructions or software and any associated data, data files, and data structures in a non-transitory manner and provide the instructions or software and any associated data, data files, and data structures to one or more processors or computers so that the one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files, and data structures are distributed over network-coupled computer systems so that the instructions and software and any associated data, data files, and data structures are stored, accessed, and executed in a distributed fashion by the one or more processors or computers.
While this disclosure includes specific examples, it will be apparent after an understanding of the disclosure of this application that various changes in form and details may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein are to be considered in a descriptive sense only, and not for purposes of limitation. Descriptions of features or aspects in each example are to be considered as being applicable to similar features or aspects in other examples. Suitable results may be achieved if the described techniques are performed in a different order, and/or if components in a described system, architecture, device, or circuit are combined in a different manner, and/or replaced or supplemented by other components or their equivalents.
Therefore, in addition to the above and all drawing disclosures, the scope of the disclosure is also inclusive of the claims and their equivalents, i.e., all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0197082 | Dec 2023 | KR | national |
