Patent Application
20250140313
The present application claims the benefit of priority to Korean Patent Application No. 10-2023-0145820 filed on Oct. 27, 2023, in the Korean Intellectual Property Office. The aforementioned application is hereby incorporated by reference in its entirety.
The present disclosure relates to a technology of updating a cross point array for a specific device, and more specifically, a method for efficiently updating a cross point array in two cycles when a resistive processing unit where potentiation and depression are separated is implemented in the form of an array.
Matrix operations using analog arrays are the key computations for Al learning and inference processes, and may improve computational performance by over several hundred times compared to conventional digital hardware.
Among methods for updating analog arrays in parallel, a stochastic update scheme involves applying random pulses corresponding to values in rows and columns to perform matrix multiplication.
If all the values corresponding to the rows and columns are positive, the array may be updated in a single pulse cycle, whereas if a mixture of positive and negative values exists in the rows and columns, up to four pulse cycles may be required for updating.
Hence, rows (or columns) having positive values and rows (or columns) having negative values are grouped, for example, as (Row, Column)=(+,+), (+,−), (−,+), (−,−), so that all devices in the array can be updated in parallel without interfering with each other. That is, due to the necessity of executing four cycles, the update process may take longer, which is a drawback in terms of time consumption.
Korean Patent Application Publication No. 10-2021-0072391 (Published on Jun. 17, 2021)
The present disclosure provides a method for efficiently updating a cross point array in two cycles when a resistive processing unit where potentiation and depression are separated is implemented in the form of an array.
In one general aspect of the present disclosure, there is provided a method for updating a cross point array implemented as a device where a potentiation region and a depression region are separated, the method being performed by a control logic and including: in a first cycle, controlling lines where positive values are applied among first lines, in ON state, and applying a first voltage pulse at each of second lines intersecting with the first lines based on an applied value; and in a second cycle, controlling lines where negative values are applied among the first lines, in ON state, and applying a second voltage pulse at each of the second lines based on an applied value.
The controlling of the lines in ON state may include independently applying a voltage pulse based on a positive value or a negative value to each first line controlled in ON state.
The applying of the first voltage pulse may include applying the first voltage pulse at each second line based on a code and magnitude of an applied value.
The applying of the second voltage pulse may include applying the second voltage pulse at each second line based on a code and magnitude opposite to an applied value.
The device may be composed of three transistors and one capacitor.
The device may charge the capacitor through a first transistor, discharge the capacitor through a second transistor, and measure a charge of the capacitor through a third transistor.
The first cycle may be defined independently so as not to overlap with the second cycle.
All devices in the cross point array may be updated in parallel only within the first and second cycles.
In another aspect, there is provided a method for updating a cross point array implemented as a device where a potentiation region and a depression region are converted through a selector, the method being performed by a control logic and including: in a first cycle, controlling lines where positive values are applied among first lines, in ON state, and controlling a connection state of a selector and a first voltage pulse at each of second lines intersecting with the first lines based on an applied value; and in the second cycle, controlling lines where negative values are applied among the first lines, in ON state, and controlling the connection state of the selector and a second voltage pulse at each second line based on an applied value.
The controlling of the lines in ON state may include independently applying a voltage pulse based on a positive value or a negative value to each first line controlled in ON state.
The controlling of the first voltage pulse may include applying the first voltage pulse at each second line based on a code and magnitude of an applied value.
The controlling of the second voltage pulse may include applying the second voltage pulse at each second line based on a code and magnitude opposite to an applied value.
The device may be composed of three NMOS transistors and one capacitor.
The device may include: two transistors connected in series, wherein a voltage source is connected to one end and a capacitor is connected to the other end; a capacitor connected to the other end of the transistors and connected to a ground (GND) at one end; and a read transistor having a gate terminal connected to the capacitor, and measuring a charge of the capacitor.
All devices in the cross point array may be updated in parallel only within the first and second cycles.
In yet another aspect, there is provided a device-based cross point array implemented as a first device where potentiation and depression are separated or as a second device where the potentiation and the depression are converted through a selector, wherein the cross point array comprises a control logic configured to update values applied to all devices in parallel in two independent cycles.
The first device or the second device may be composed of three NMOS transistors and one capacitor.
The second device may include: two transistors connected in series, wherein a voltage source is connected to one end and a capacitor is connected to the other end; a capacitor connected to the other end of the transistors and connected to a ground (GND) at one end; and a read transistor having a gate terminal connected to the capacitor, and measuring a charge of the capacitor.
The control logic may be further configured to, in a first cycle, control lines where positive values are applied among first lines, in ON state, and apply a first voltage pulse at each of second lines intersecting with the first lines based on an applied value.
The control logic may be further configured to, in a second cycle, control lines where negative values are applied among first lines, in ON state, and apply a second voltage pulse at each of second lines based on an applied value.
The disclosed technology may have the following effects. However, since it does not imply that a specific embodiment must include all of the following effects or only the following effects, the scope of the disclosed technology should not be understood to be limited thereto.
In the device-based cross point array and a method for operation thereof according to an embodiment of the present disclosure, it is possible to efficiently perform a cross point array in two cycles when a resistive processing unit where potentiation and depression are separated is implemented in the form of an array.
A description of the present disclosure is merely an embodiment for a structural or functional description and the scope of the present disclosure should not be construed as being limited by an embodiment described in a text. That is, since the embodiment can be variously changed and have various forms, the scope of the present disclosure should be understood to include equivalents capable of realizing the technical spirit. Further, it should be understood that since a specific embodiment should include all objects or effects or include only the effect, the scope of the present disclosure is limited by the object or effect.
Meanwhile, meanings of terms described in the present application should be understood as follows.
The terms “first,” “second,” and the like are used to differentiate a certain component from other components, but the scope of should not be construed to be limited by the terms. For example, a first component may be referred to as a second component, and similarly, the second component may be referred to as the first component.
It should be understood that, when it is described that a component is “connected to” another component, the component may be directly connected to another component or a third component may be present therebetween. In contrast, it should be understood that, when it is described that an element is “directly connected to” another element, it is understood that no element is present between the element and another element. Meanwhile, other expressions describing the relationship of the components, that is, expressions such as “between” and “directly between” or “adjacent to” and “directly adjacent to” should be similarly interpreted.
It is to be understood that the singular expression encompasses a plurality of expressions unless the context clearly dictates otherwise and it should be understood that term “include” or “have” indicates that a feature, a number, a step, an operation, a component, a part or the combination thereof described in the specification is present, but does not exclude a possibility of presence or addition of one or more other features, numbers, steps, operations, components, parts or combinations thereof, in advance.
In each step, reference numerals (e.g., a, b, c, etc.) are used for convenience of description, the reference numerals are not used to describe the order of the steps and unless otherwise stated, it may occur differently from the order specified. That is, the respective steps may be performed similarly to the specified order, performed substantially simultaneously, and performed in an opposite order.
The present disclosure can be implemented as a computer-readable code on a computer-readable recording medium and the computer-readable recording medium includes all types of recording devices for storing data that can be read by a computer system. Examples of the computer readable recording medium may include a ROM, a RAM, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like. Further, the computer readable recording media may be stored and executed as codes which may be distributed in the computer system connected through a network and read by a computer in a distribution method.
If it is not contrarily defined, all terms used herein have the same meanings as those generally understood by those skilled in the art. Terms which are defined in a generally used dictionary should be interpreted to have the same meanings as the meanings in the context of the related art, and are not interpreted as ideal meanings or excessively formal meanings unless clearly defined in the present application.
Referring to
Referring to
In addition, the first device 100 may be updated only at a point where a column pulse and a row pulse overlap. In the upper image of
Referring to
If an array device of a larger size needs to be updated, in the first cycle, all columns having positive values may be controlled to be in ON state and a pulse corresponding to a code and value of each row may be applied to a corresponding row, while, in the second cycle, all columns having negative values may be controlled to be in ON state and a pulse corresponding to a value opposite to a code for each row may be applied to a corresponding row. This process enables updates to be performed within two cycles for arrays of various sizes.
Referring to
Specifically, the potentiation region may be composed of the PMOS transistors, while the depression region may be composed of the NMOS transistor. It is possible to write and read data of the device by charging the capacitor through the PMOS transistor, discharging the capacitor through the NMOS transistor, and reading the charge stored in the capacitor through the read transistor.
In addition, only when specific conditions for voltage applied to the gate and drain electrode are met, the PMOS and NMOS transistors may proceed charging and discharging. This may correspond to the same mechanism shown in
Meanwhile, the PMOS and NMOS transistors may be implemented as oxide semiconductor-based PMOS and NMOS devices, respectively. For example, the oxide semiconductor-based PMOS device may be implemented using copper oxide (Cu2O), tin oxide (SnO), or a combination thereof, while the oxide semiconductor-based NMOS device may be implemented using zinc oxide (ZnO) based materials, such as IGZO (In—Ga—Zn Oxide), GZO (Ga—Zn Oxide), IZTO (Indium-Zn-Tin Oxide), or ZnO in combination.
Referring to
First, the values applied to the row lines (or column lines) of the cross point array may be separated into positive and negative, and all devices on row lines corresponding to positive values may be updated in one cycle, while all devices on row lines corresponding to negative values may be updated in the other cycle.
Specifically, in operation S510, an update process may proceed in a manner where in a first cycle, columns having positive values may be controlled to be in ON state and then pulses corresponding to the code and magnitude of the applied values are applied to the respective rows. In operation S530, the update process may proceed in a manner where, in the second cycle, columns having negative values are controlled to be in ON state and then a pulse corresponding to the opposite code and magnitude of an applied value is applied at each row.
Referring to
Referring to
In addition, updates may occur only at points where pulses of column Col and row Row overlap in the second device 600. In the upper image of
Referring to
In the second cycle, since a value corresponding to Row2 830 is 0.3, a pulse of 2/10 may be applied, and as a value corresponding to Col1 850 is 0.3, the selector may be converted to GND and a pulse of 3/10 may be applied to Col1 850. In addition, since a value corresponding to Col2 is −0.4, the selector may be converted to VDD and a pulse of 4/10 may be applied to Col2. Therefore, in the second cycle, values of −0.06 and 0.08 may be updated in device_21 and device_22, respectively. This process enables updates to be performed within two cycles for arrays of various sizes.
Referring to
Specifically, with two NMOS transistors connected in series, a voltage source VDD, GND may be connected to one end and a capacitor may be connected to the other end. GND may be connected to the other end of the capacitor, which is not connected to the NMOS transistors. In addition, in order to read the charge stored in the capacitor, an end of the capacitor may be connected to a gate electrode of a read NMOS transistor.
Accordingly, for charging, the both NMOS transistors may be controlled in ON state (i.e., VG1=VG2>Vth), and the voltage source may be set to VDD. For discharging, the both NMOS transistors may be controlled in ON state, and the voltage source may be set to GND. Furthermore, to halt charging, at least one of the two NMOS transistors may be controlled to OFF state (i.e., VG1<Vth or VG2<Vth). To read the charge stored in the capacitor, the both NMOS transistors may be controlled to OFF state (i.e., VG1=VG2<Vth), and current may be measured through the read NMOS transistor.
Additionally, charging and discharging may be implemented only when the voltage applied to the gate electrodes of the two NMOS transistors meets specific conditions. This may be the same mechanism shown in
Referring to
Specifically, in operation S1010, an update process may proceed in a manner where, in the first cycle, rows having positive values are controlled in ON state and then converting the state of the selector and applying a pulse is performed at each column based on a code and magnitude of an applied value. In operation S1030, in the second cycle, the update process may proceed in a manner where, in the second cycle, rows having negative values are controlled in ON state, and then converting the state of the selector and applying a pulse may be performed at each column based on a code and magnitude of an applied value.
Referring to
The control logic 1130 may control read, write, and other operations on the memory cell array 1110. In addition, the control logic 1130 may provide address decoding and timing signals, which are necessary for reading from and writing to the memory cell array 1110. In particular, the control logic 1130 may control the operation of updating values applied to all devices of the memory cell array 1110 in parallel within two independent cycles.
Specifically, in a method for updating a cross point array implemented as the first device, the control logic 1130 may, in a first cycle, control lines where positive values are applied among first lines (i.e., column lines), in ON state, and apply a first voltage pulse at each of the second lines (i.e., low lines) intersecting with the first lines based on a code and magnitude corresponding to an applied value, and in a second cycle defined independently of the first cycle, may control lines where negative values are applied among the first lines, in ON state, and apply a second voltage pulse at each of the second lines based on a code and magnitude opposite to an applied value.
In addition, in a method for updating a cross point array implemented as a second device, the control logic 1130 may, in a first cycle, control lines where positive values are applied among the first lines (i.e., low lines), in ON state, and control a connection state of the selector and a first voltage pulse based on an applied value at each of the second lines (i.e., column lines) intersecting with the first lines, and, in a second cycle defined independently of the first cycle, may control lines where negative values are applied among the first lines, in ON state, and control a connection state of the selector and a second voltage pulse at each of the second lines based on an applied value.
In one embodiment, the cross point array 1100 may be implemented as a memory device in conjunction with a memory controller. In this case, the control logic 1130 of the cross point array 1100 may operate in conjunction with the memory controller. For example, the control logic 1130 may receive a command CMD, an address ADDR, and a control signal CTRL from the memory controller, and may output a control signal to access the memory cell array 1110 to write or read data.
Referring to
First, in the first cycle of the update method, a voltage pulse may be applied to both the potentiation region and the depression region for column lines 1230 having positive values. In addition, for each row line 1210, a voltage pulse may be applied to the potentiation region for the positive value line (+) and to the depression region for the negative value line (−). For example, in the first cycle, a voltage pulse having the code and magnitude corresponding to a value applied to each row may be applied.
Next, in the second cycle of the update method, a voltage pulse may be applied to both the potentiation region and the depression region for column lines 1230 having negative values. In addition, for each row line 1210, a voltage pulse may be applied to the depression region for the positive value line (+) and to the potentiation region for the negative value line (−). For example, in the second cycle, a voltage pulse having a code and magnitude opposite to the value applied to each row line may be applied.
Referring back to
First, in a first cycle of the update method, voltage pulses may be applied only to row lines 1310 having positive values. At this point, for column line 1330, voltage pulses may be applied to both lines having positive values (+) and lines having negative values (−), and through selector lines 1350, VDD may be selected for column lines 1330 having the positive values while GND may be selected for column lines 1330 having negative values.
Next, in a second cycle of the update method, voltage pulses may be applied only to row lines 1310 having negative values. At this point, for the column line 1330, voltage pulses may be applied to both lines having positive values (+) and lines having negative values (−), and through the selector lines 1350, GND may be selected for the column line 1330 having positive values while VDD may be selected for the column lines 1330 having negative values.
A device-based cross point array according to the present disclosure may be implemented with a resistive processing unit where potentiation and depression are separated, and a method for updating the cross point array in parallel with only two cycles rather than four cycles may be provided.
Specifically, in the update method according to the present disclosure, every device may be updated in a manner in which values corresponding to rows (or columns) of the array are divided into positive and negative, all devices corresponding to rows (columns) having positive values are updated in the first cycle, and then all devices corresponding to rows (columns) having negative values are updated in the second cycle. In doing this, the update method according to the present disclosure may perform the update process twice as fast as the existing method.
While the present disclosure has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various modifications and changes may be made therein through inclusion, alteration, removal or addition of elements without departing from the spirit and scope of the present disclosure as defined by the following claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0145820 | Oct 2023 | KR | national |
