Claims
- 1. A device for neutralizing an access to an integrated-circuit zone to be protected, said integrated circuit being formed on a semiconductor substrate of a first given conductivity type, of the type comprising a fuse section integrated in a circuit and placed in series between said access and the zone to be protected, wherein the end portion of the fuse section located nearest the zone to be protected is connected to said zone by being connected directly to a layer of a second given conductivity type forming with the substrate a junction which is reverse-biased at the time of normal utilization of said circuit and which is forward biased at the time of the melting of the fuse the fuse section being surmounted by a metallic portion which surrounds directly a hole of said fuse section and rests on said section, electrically independent from said fuse, by means of an insulating layer, so that any attempt to contact any remaining part of said fuse after melting with a probe will be prevented by contact of said probe with said metallic portion, short circuiting said probe and preventing access to said zone, said device further comprising means for passing the melting current of the fuse through said junction, said means for passing also connecting said substrate forwardly when melting.
- 2. A device according claim 1, wherein said metallic portion is connected to a constant potential of the circuit in opposition to a rest potential of the layer of the second conductivity type.
- 3. A device according to claim 2, wherein the fuse section is open to free air by a hole in order to achieve improved melting of said fuse section.
- 4. A device according to claim 2, wherein the metallic portion is also connected to another metallic portion which is located above the junction.
- 5. A device according claim 4, wherein the fuse section is formed of polycrystalline silicon.
- 6. A device according to claim 5, wherein the fuse section has a width of 2.5 microns and a thickness of 0.5 micron.
- 7. A device according to claim 6, wherein the fuse section rests on a thick oxide layer formed above the substrate.
- 8. A device according to claim 6, wherein the fuse section rests on a silicon nitride layer.
- 9. A device according to claim 8, wherein the integrated circuit is fabricated in accordance with the MOS technology.
- 10. A device according to claim 9, wherein the integrated circuit is fabricated in accordance with the NMOS technology.
- 11. A device according to claim 10, wherein the integrated circuit is covered with a dielectric layer outside the portions which are left exposed to free air.
- 12. A device according to claim 2, wherein said substrate acts as a terminal of said fuse when melted.
- 13. A device according to claim 2, wherein said layer of a second given conductivity type extends into said zone to be protected.
Priority Claims (1)
Number |
Date |
Country |
Kind |
84 12679 |
Aug 1984 |
FRX |
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Parent Case Info
This application is a continuation of application Ser. No. 004,223, filed on Jan. 5, 1987, now abandoned, which is a continuation of application Ser. No. 763,272, filed Aug. 7, 1985, abandoned.
US Referenced Citations (10)
Foreign Referenced Citations (3)
Number |
Date |
Country |
0076967 |
Apr 1983 |
EPX |
2503424 |
Oct 1982 |
FRX |
59-66144 |
Apr 1984 |
JPX |
Continuations (2)
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Number |
Date |
Country |
Parent |
4223 |
Jan 1987 |
|
Parent |
763272 |
Aug 1985 |
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