DEVICE HAVING AN ARRAY OF NON-VOLATILE MEMORY CELLS AND A METHOD FOR ALTERING A STATE OF A NON-VOLATILE MEMORY CELL

Abstract

An array of non-volatile memory cells and a method for altering a state of a non-volatile memory cell that comprises multiple terminals, a substrate, and a charge retainer surrounded by an insulator, the method includes: illuminating the substrate with light such as to create electron-hole pairs within a first portion of the substrate positioned deep within the substrate and to create electron-hole pairs within a second portion of the substrate located near an upper surface of the substrate; and applying at least one control voltage to at least one terminal of the non-volatile memory cell such as to cause charged particles created in the first portion and in the second portion to propagate towards the upper surface of the substrate and to be injected into the charge retainer.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will be understood and appreciated more fully from the following detailed description taken in conjunction with the drawings in which:

FIGS. 1A and 1B illustrates two cross sectional views of a portion of a device according to an embodiment of the invention;

FIG. 2 illustrates a cross section of a portion of a non-volatile memory cell according to an embodiment of the invention;

FIG. 3 illustrates a cross section of a portion of a non-volatile memory cell according to an embodiment of the invention;

FIGS. 4 and 5 are energy band diagrams that illustrates programming of a floating gate memory cell by hot electron injection and by tunneling of photo-generated electrons according to various embodiments of the invention;

FIG. 6 is a cross sectional view of a device according to an embodiment of the invention;

FIG. 7 illustrates a relationship between the gate current and between the gate voltage of an n-channel MOS transistor, according to an embodiment of the invention; and

FIGS. 8-9 illustrate methods for affecting a state of a non-volatile memory cell, according to an embodiment of the invention.

Claims

1. A method for altering a state of a non-volatile memory cell that comprises multiple terminals, a substrate, and a charge retainer surrounded by an insulator, the method comprises: illuminating the substrate with light such as to create electron-hole pairs within a first portion of the substrate positioned deep within the substrate and to create electron-hope pairs within a second portion of the substrate located near an upper surface of the substrate; andapplying at least one control voltage to at least one terminal of the non-volatile memory cell such as to cause electrons created in the first portion and in the second portion to propagate towards the upper surface of the substrate and to be injected into the charge retainer.

2. The method according to claim 1 wherein the applying comprises maintaining a first potential drop between an upper surface of the substrate and between other parts of the substrate and maintaining a second potential drop between the upper portion of the substrate and the charge retainer.

3. The method according to claim 1 wherein the applying and illuminating cause charged particles of the electron-hole pairs to tunnel through a third insulator region positioned between the substrate and between the charge retainer.

4. The method according to claim 1 wherein the applying and illuminating cause charged particles of the electron-hole pairs to accelerate towards the upper surface of the substrate and surmount a potential barrier between the upper surface of the substrate and between a third insulator layer positioned between the upper surface of the substrate and between the charge retainer.

5. The method according to claim 1 wherein the applying and illuminating cause charged particles of the electron-hole pairs to surmount a potential barrier between the upper surface of the substrate and between a third insulator layer positioned between the upper surface of the substrate and between the charge retainer and to cause multiple charged particles of the electro-hole pairs to tunnel through the third insulator region.

6. The method according to claim 1 wherein the illuminating comprises illuminating the non-volatile memory cell with photons that have photon energy that is higher than a band-gap energy of the substrate.

7. The method according to claim 1 wherein the illuminating comprises illuminating the non-volatile memory cell with photons that have photon energy that is smaller than a sum of the band-gap energy of the substrate and the potential barrier between the substrate and between a third insulator layer positioned between the substrate and between the charge retainer.

8. The method according to claim 1 wherein the illuminating comprises illuminating the non-volatile memory cell with photons that have photon energy that is higher than a band-gap energy of the substrate and smaller than a sum of the band-gap energy of the substrate and a potential barrier between the substrate and between a third insulator layer positioned between the substrate and between the charge retainer.

9. The method according to claim 1 further comprising defining a required state of the non-volatile memory cell and selectively repeating the stages of illuminating and applying until the memory cell is at the required state.

10. The method according to claim 1 further comprising defining a required state of the non volatile memory cell; and setting an initial intensity of the light according to the required state.

11. The method according to claim 1 further comprising altering an intensity of the light between two iterations of the illuminating.

12. The method according to claim 1 further comprising illuminating a first non-volatile memory cell and a second non-volatile memory cell that is adjacent to the first memory cell and wherein the method further comprises applying at least one control voltage to at least one terminal of the second non-volatile memory cell such as to substantially prevent charged particles created in the substrate to be injected into a charge retainer of the second non-volatile memory cell.

13. The method according to claim 1 further comprising illuminating a first and second group of non-volatile memory cells, altering a state of a first group of non-volatile memory cells while preventing non-volatile memory cells of the second group from altering their state.

14. The method according to claim 1 wherein the illuminating comprises illuminating a non-volatile cell in which the charge retainer is a floating gate.

15. The method according to claim 1 wherein the illuminating comprises illuminating a non-volatile cell in which the charge retainer is a charge trapping region.

16. The method according to claim 1 wherein the illuminating comprises illuminating the substrate by diffractive illumination.

17. The method according to claim 16 wherein the illuminating comprises directing at least one light beam towards multiple light absorptive portions of multiple non-volatile memory cells positioned above multiple semiconductor regions of the multiple non-volatile memory cells.

18. The method according to claim 1 wherein the illuminating comprises illuminating the non-volatile memory cells by a light source positioned substantially above the non-volatile memory call and positioned substantially in parallel to the non-volatile memory cell.

19. A device comprising a non-volatile memory cell, wherein the non-volatile memory cell comprises: a light source, multiple terminals, and a charge retainer surrounded by an insulator; wherein the light source is adapted to illuminate the substrate; wherein the substrate comprises a first portion positioned deep within the substrate and a second portion located near an upper surface of the substrate; and wherein the non-volatile memory cell is adapted, in response to the illumination of the substrate and in response to an appliance of at least one control voltage to at least one terminal out of the multiple terminals, to cause charged particles out of electron-hole pairs created in the first portion and in the second portion to propagate towards the upper surface of the substrate and to be injected into the charge retainer.

20. The device according to claim 19 wherein the non-volatile memory cell is adapted to allow charged particles out of the electron-hole pairs to tunnel through a third insulator region positioned between the substrate and between the charge retainer.

21. The device according to claim 19 wherein the non-volatile memory cell is adapted to allow charged particles of the electron-hole pairs to accelerate towards the upper surface of the substrate and to surmount a potential barrier between the substrate and between a third insulator layer positioned between the substrate and between the charge retainer.

22. The device according to claim 19 wherein the non-volatile memory cell is adapted to allow multiple charged particle of the electron-hole pairs to surmount a potential barrier between the substrate and between a third insulator layer positioned between the substrate and between the charge retainer and also allow multiple charged particles of the electron-hole pairs to tunnel through the third insulator layer.

23. The device according to claim 19 wherein the light source is adapted to illuminate the non-volatile memory cell with photons that have photon energy that is higher than a band-gap energy of the substrate.

24. The device according to claim 19 wherein the light source is adapted to illuminate the non-volatile memory cell with photons that have photon energy that is smaller than a sum of a band-gap energy of the substrate and a potential barrier between the substrate and between a third insulator layer positioned between the substrate and between the charge retainer.

25. The device according to claim 19 wherein the light source is adapted to illuminate the non-volatile memory cell with photons that have photon energy that is higher than a band-gap energy of the substrate and is smaller than a sum of a band-gap energy of the substrate and a potential barrier between the substrate and between a third insulator layer positioned between the substrate and between the charge retainer.

26. The device according to claim 19 further adapted to adjust an intensity of light generated by the light source.

27. The device according to claim 19 wherein the light source is adapted to illuminate a first non-volatile memory cell and a second non-volatile memory cell that is adjacent to the first memory cell and wherein the device is adapted to applying at least one control voltage to at least one terminal of the second non-volatile memory cell such as to substantially prevent electrons created in the substrate to be injected into a charge retainer of the second non-volatile memory cell.

28. The device according to claim 19 wherein the device comprises a first group of non-volatile cells and a second group of non-volatile cells; wherein the device is adapted to simultaneously illuminate the first group and the second group of non-volatile memory cells, allow non-volatile memory cells that belong to the first group to alter their state while prevent non-volatile memory cells of the second group from altering their state.

29. The device according to claim 19 wherein the charge retainer is a floating gate.

30. The device according to claim 19 wherein the charge retainer is a charge trapping region.

31. The device according to claim 19 wherein the light source illuminates the substrate by diffractive illumination.

32. The device according to claim 31 wherein the light source is adapted to illuminate multiple non-volatile memory cells of the device by directing at least one light beam towards multiple light absorptive portions of multiple non-volatile memory cells positioned above multiple bodies of the multiple non-volatile memory cells.

33. The device according to claim 19 wherein the light source is positioned substantially in parallel to the non-volatile memory cell.

34. A device that comprises: a first layer that comprises light absorptive control lines adapted to provide control signals to multiple non-volatile memory cells;a second layer that comprises light absorptive control lines adapted to provide control signals to multiple non-volatile memory cells;a third layer that comprises multiple charge retainers that are surrounded by an insulator; wherein the third layer is placed below the first and second layers; and a light source;wherein each non-volatile memory cell further comprises a substrate that comprises multiple semiconductor pn junctions defined between a body and other semiconductor regions of the non-volatile memory cell;wherein the substrate is placed below the third layer;wherein the device is adapted to alter its state by a propagation of photo-generated charged particles between the substrate and between the charge retainer;wherein the alteration of the state of the non-volatile memory cells is responsive to (i) a diffractive propagation of light through the first and second layers towards the substrate and (ii) a provision of control voltages to at least one light absorptive control line, wherein the diffractive propagation of light and the provision of at least one control voltage forces photo-generated charged particles to propagate between the substrate and between the charge retainer.

35. The device according to claim 34 wherein the device is adapted to alter its state while a reverse bias is maintained across at least one semiconductor pn junction within the substrate.

36. The device according to claim 34 wherein the device comprises a pair of semiconductor regions that form a semiconductor pn junction and wherein at least one semiconductor region of the pair is kept floating during the diffractive illumination.

37. The device according to claim 34 wherein the multiple non-volatile memory cells are arranged in a NAND format.

38. The device according to claim 34 wherein the multiple non-volatile memory cells are arranged in a NOR format.

39. The device according to claim 34 wherein the device is adapted to allow photo-generated charged particles to tunnel through an insulator positioned between the substrate and between the charge retainers.

40. The device according to claim 34 wherein the device is adapted to allow photo-generated charged particles to accelerate towards the upper surface of the substrate and to surmount a potential barrier between the substrate and between an insulator positioned between the substrate and between the charge retainers.

41. The device according to claim 34 wherein the device is adapted to allow multiple charged particle of the electron-hole pairs to surmount a potential barrier between the substrate and between an insulator positioned between the substrate and between the charge retainers and also allow multiple photo-generated charged particles to tunnel through the insulator.

42. The device according to claim 34 wherein the light source is adapted to illuminate the non-volatile memory cell with photons that have photon energy that is higher than band-gap energy of the substrate.

43. The device according to claim 34 wherein the light source is adapted to illuminate the non-volatile memory cell with photons that have photon energy that is smaller than a sum of a band-gap energy of the substrate and a potential barrier between the substrate and between an insulator positioned between the substrate and between the charge retainers.

44. The device according to claim 34 wherein the light source is adapted to illuminate the non-volatile memory cell with photons that have photon energy that is higher than a band-gap energy of the substrate and is smaller than a sum of a band-gap energy of the substrate and a potential barrier between the substrate and between an insulator positioned between the substrate and between the charge retainers.

45. The device according to claim 34 further adapted to adjust an intensity of light generated by the light source.

46. The device according to claim 34 wherein the light source is adapted to illuminate a first non-volatile memory cell and a second non-volatile memory cell that is adjacent to the first memory cell and wherein the device is adapted to applying at least one control voltage to at least one terminal of the second non-volatile memory cell such as to substantially prevent photo-generated electrons created in the substrate to be injected into a charge retainer of the second non-volatile memory cell.

47. The device according to claim 34 wherein the device comprises a first group of non-volatile memory cells and a second group of non-volatile memory cells; wherein the device is adapted to simultaneously illuminate the first group and the second group of non-volatile memory cells, allow non-volatile memory cells that belong to the first group to alter their state while prevent non-volatile memory cells of the second group from altering their state.

48. A method for altering a state of non-volatile memory cells, the method includes: illuminating, by diffractive illumination, a substrate of a non-volatile memory cell, wherein the illuminating comprises diffractive propagation of light through a first layer, a second layer and a third layer of a device, wherein the first layer comprises light absorptive control lines adapted to provide control signals to multiple non-volatile memory cells, the second layer comprises light absorptive control lines adapted to provide control signals to multiple non-volatile memory cells, the third layer comprises multiple charge retainers that are surrounded by an insulator; wherein the third layer is placed below the first and second layers; and a light source; wherein the substrate comprises multiple semiconductor pn junctions defined between a body and other semiconductor regions of the non-volatile memory cell; wherein the substrate is placed below the first, second and third layers; andproviding at least one control voltage to at least one terminal of the non-volatile memory cell such as to alter a state of the non-volatile memory cell by propagation of photo-generated charged particles from the substrate to the charge retainer.

49. The method according to claim 48 wherein the providing comprises maintaining a reverse bias across at least one semiconductor pn junction within the substrate.

50. The method according to claim 48 wherein the providing comprises maintaining at least one semiconductor region out of a pair of semiconductor regions that form a semiconductor pn junction floating.

51. The method according to claim 48 wherein the illuminating comprises illuminating multiple non-volatile memory cells that are arranged in a NAND format.

52. The method according to claim 48 wherein the illuminating comprises illuminating multiple non-volatile memory cells that are arranged in a NOR format.

53. The method according to claim 48 wherein the illuminating and providing cause photo-generated charged particles to tunnel through an insulator positioned between the substrate and between the charge retainers.

54. The method according to claim 48 wherein the illuminating and providing cause photo-generated charged particles to accelerate towards the upper surface of the substrate and surmount a potential barrier between an upper surface of the substrate and between an insulator positioned between the upper surface of the substrate and between the charge retainer.

55. The method according to claim 48 wherein the illuminating and providing cause photo-generated charged particles to surmount a potential barrier between an upper surface of the substrate and between an insulator positioned between the upper surface of the substrate and between the charge retainers and to cause multiple photo-generated charged particles to tunnel through the insulator.

56. The method according to claim 48 wherein the illuminating comprises illuminating the non-volatile memory cell with photons that have photon energy that is higher than a band-gap energy of the substrate.

57. The method according to claim 48 wherein the illuminating comprises illuminating the non-volatile memory cell with photons that have photon energy that is smaller than a sum of the band-gap energy of the substrate and the potential barrier between the substrate and between an insulator positioned between the substrate and between the charge retainers.

58. The method according to claim 48 wherein the illuminating comprises illuminating the non-volatile memory cell with photons that have photon energy that is higher than a band-gap energy of the substrate and smaller than a sum of the band-gap energy of the substrate and a potential barrier between the substrate and between an insulator positioned between the substrate and between the charge retainers.

59. The method according to claim 48 further comprising defining a required state of a non-volatile memory cell and selectively repeating the stages of illuminating and providing until the non-volatile memory cell is at the required state.

60. The method according to claim 48 further comprising defining a required state of a non volatile memory cell and setting an initial intensity of the light according to the required state.

61. The method according to claim 48 further comprising altering an intensity of the light between two iterations of the illuminating.

62. The method according to claim 48 further comprising illuminating a first non-volatile memory cell and a second non-volatile memory cell that is adjacent to the first memory cell and wherein the method further comprises applying at least one control voltage to at least one terminal of the second non-volatile memory cell such as to substantially prevent photo-generated charged particles created in the substrate to be injected into a charge retainer of the second non-volatile memory cell.

63. The method according to claim 48 further comprising illuminating a first and second group of non-volatile memory cells, altering a state of a first group of non-volatile memory cells while preventing non-volatile memory cells of the second group from altering their state.