Claims
- 1. A data processing device or system, comprising:
- an analog-to-digital converter;
- an electronic processor with an instruction pipeline connected to said analog-to-digital processor;
- means for decoding a conditional execution instruction within said instruction pipeline;
- means for conditioning the execution of a predetermined set of conditioned instructions following said conditional execution instruction within said instruction pipeline in response to a status condition specified in said conditional execution instruction;
- means for executing said set of conditioned instructions without flushing said instruction pipeline; and
- wherein means for conditioning further comprise:
- means for determining which status conditions of a set of predetermined status conditions have been selected by said conditional execution instruction with mask bits representative of said predetermined status conditions;
- means for determining which values are required by said conditional execution instruction for said selected set of predetermined status conditions with status bits representative of said predetermined values; and
- means for allowing normal execution of said conditioned instructions based on a logical combination of said mask bits and said status bits.
- 2. The data processing system of claim 1 further comprising an instruction memory connected to said electronic processor.
- 3. The data processing system of claim 1 further comprising a video output circuit connected to said electronic processor and a video display connected to said video output circuit.
- 4. The device or system of claim 1, wherein said means for executing further comprises:
- means for executing said set of conditioned instructions in a normal manner if said condition specified in said conditional instruction is present, or by changing said conditioned instructions to a no-operation (NOP) instruction if said condition specified in said conditional instruction is not present.
- 5. A data processing device or system, comprising:
- an analog-to-digital converter;
- an electronic processor with an instruction pipeline connected to said analog-to-digital processor;
- means for decoding a conditional execution instruction within said instruction pipeline;
- means for conditioning the execution of a predetermined set of conditioned instructions following said conditional execution instruction within said instruction pipeline in response to a status condition specified in said conditional execution instruction;
- means for executing said set of conditioned instructions without flushing said instruction pipeline; and
- wherein means for conditioning further comprise:
- means for determining which status conditions of a set of predetermined status conditions have been selected by said conditional execution instruction with mask bits representative of said predetermined status conditions;
- means for determining which values are required by said conditional execution instruction for said selected set of predetermined status conditions with status bits representative of said predetermined values;
- means for making a multiple status test in a single cycle by enabling testing of selected status conditions selected by said mask bits and ignoring status conditions not selected by said mask bits; and
- means for comparing an actual value each of said selected status conditions to a predetermined value contained in corresponding said status bit of the conditional execution instruction.
- 6. A data processing device or system, comprising:
- an analog-to-digital converter;
- an electronic processor with an instruction pipeline connected to said analog-to-digital processor;
- means for decoding a conditional execution instruction within said instruction pipeline;
- means for conditioning the execution of a predetermined set of conditioned instructions following said conditional execution instruction within said instruction pipeline in response to a status condition specified in said conditional execution instruction;
- means for executing said set of conditioned instructions without flushing said instruction pipeline;
- wherein said conditional execution instruction includes a pair of bits corresponding to each of said status conditions of said set of predetermined status conditions;
- wherein means for conditioning further comprise:
- means for determining which status conditions of a set of predetermined status conditions have been selected by said conditional execution instruction with mask bits representative of said predetermined status conditions; and
- wherein said means for determining which status conditions further comprises,
- means for using a first of said pair of bits as said mask bit for determining whether to consider a status condition; and
- means for using a second of said pair of bits as a level to test said actual value of said status condition against.
CROSS REFERENCE TO RELATED APPLICATIONS
This is a divisional application under 37 CFR 1.60, of pending prior application Ser. No. 08/289,028 filed on Aug. 10, 1994, which is a Divisional 1.60 of application Ser. No. 07/967,942 fild Oct. 28, 1992, now abandoned, which is a Continuation 1.62 of application Ser. No. 07/347,967, filed May 4,1989, now abandoned.
US Referenced Citations (9)
Divisions (2)
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Number |
Date |
Country |
Parent |
289028 |
Aug 1994 |
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Parent |
967942 |
Oct 1992 |
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Continuations (1)
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Number |
Date |
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Parent |
347967 |
May 1989 |
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