Scan chain arrangements

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CPC
G01R31/318536

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GPHYSICS G01Measuring instruments G01RMEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES G01R31/00Arrangements for testing electric properties Arrangements for locating electric faults Arrangements for electrical testing characterised by what is being tested not provided for elsewhere

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G01R31/318536Scan chain arrangements

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Area, cost, and time-effective scan coverage improvement
- Patent number 12,366,605
- Issue date Jul 22, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Interposer circuit
- Patent number 12,352,814
- Issue date Jul 8, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Test pattern generation using multiple scan enables
- Patent number 12,345,764
- Issue date Jul 1, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Shiv Kumar Vats
- G01 - MEASURING TESTING
Information Patent Grant
Machine-learning-based design-for-test (DFT) recommendation system...
- Patent number 12,333,227
- Issue date Jun 17, 2025
- Synopsys, Inc.
- Apik A Zorian
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic voltage frequency scaling to reduce test time
- Patent number 12,320,850
- Issue date Jun 3, 2025
- Mediatek Inc.
- Anshul Varma
- G01 - MEASURING TESTING
Information Patent Grant
Scan chains with multi-bit cells and methods for testing the same
- Patent number 12,306,248
- Issue date May 20, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Mohammed Moiz Khan
- G01 - MEASURING TESTING
Information Patent Grant
Saving and restoring scan states
- Patent number 12,306,249
- Issue date May 20, 2025
- Atmosic Technologies, Inc.
- Mohsen Shaaban
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit, an apparatus for testing an integrated circuit,...
- Patent number 12,306,250
- Issue date May 20, 2025
- Advantest Corporation
- Frank Mielke
- G01 - MEASURING TESTING
Information Patent Grant
Secured scan access for a device including a scan chain
- Patent number 12,298,346
- Issue date May 13, 2025
- Texas Instruments Incorporated
- Mudasir Kawoosa
- G01 - MEASURING TESTING
Information Patent Grant
Flip-flop device and method of operating flip-flop device
- Patent number 12,301,228
- Issue date May 13, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Greg Gruber
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data gating using scan enable pin
- Patent number 12,287,370
- Issue date Apr 29, 2025
- Apple Inc.
- FNU Rajeev Kumar
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain formation for improving chain resolution
- Patent number 12,282,063
- Issue date Apr 22, 2025
- Synopsys, Inc.
- Emil Gizdarski
- G01 - MEASURING TESTING
Information Patent Grant
Compression-based scan test system
- Patent number 12,265,121
- Issue date Apr 1, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit margin measurement for structural testing
- Patent number 12,241,933
- Issue date Mar 4, 2025
- PROTEANTECS LTD.
- Evelyn Landman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan chain analysis using predefined capture signature
- Patent number 12,216,161
- Issue date Feb 4, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Grant
Test-time optimization with few slow scan pads
- Patent number 12,203,985
- Issue date Jan 21, 2025
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Registers
- Patent number 12,158,499
- Issue date Dec 3, 2024
- Nordic Semiconductor ASA
- Matti Samuli Leinonen
- G01 - MEASURING TESTING
Information Patent Grant
TVF transition coverage with self-test and production-test time red...
- Patent number 12,146,911
- Issue date Nov 19, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus to implement a boundary scan for shared analo...
- Patent number 12,130,329
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Grant
Reconfigurable JTAG architecture for implementation of programmable...
- Patent number 12,123,912
- Issue date Oct 22, 2024
- University of Florida Research Foundation, Incorporated
- Swarup Bhunia
- G01 - MEASURING TESTING
Information Patent Grant
Scan frame based test access mechanisms
- Patent number 12,117,490
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan compression through pin data encoding
- Patent number 12,105,145
- Issue date Oct 1, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Grant
Emulation of JTAG/SCAN test interface protocols using SPI communica...
- Patent number 12,092,690
- Issue date Sep 17, 2024
- SILICONCH SYSTEMS PVT LTD
- Rakesh Kumar Polasa
- G01 - MEASURING TESTING
Information Patent Grant
Scan tree construction
- Patent number 12,092,691
- Issue date Sep 17, 2024
- Tsinghua University
- Can Xiang
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus to identify faults in processors
- Patent number 12,085,610
- Issue date Sep 10, 2024
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Grant
Wrapper cell design and built-in self-test architecture for 3DIC te...
- Patent number 12,066,490
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Grant
Scan flip-flops with pre-setting combinational logic
- Patent number 12,066,489
- Issue date Aug 20, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 12,057,183
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated test circuit, test assembly and method for testing an in...
- Patent number 12,055,587
- Issue date Aug 6, 2024
- Infineon Technologies AG
- Tobias Kilian
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Decompression circuit, circuit generation method, and IC chip
- Patent number 12,050,248
- Issue date Jul 30, 2024
- Huawei Technologies Co., Ltd.
- Yu Huang
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME
- Publication number 20250231235
- Publication date Jul 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mohammed Moiz Khan
- G01 - MEASURING TESTING
Information Patent Application
ARCHITECTURE FOR TESTING MULTIPLE SCAN CHAINS
- Publication number 20250199069
- Publication date Jun 19, 2025
- STMicroelectronics International N.V.
- Enea Dimroci
- G01 - MEASURING TESTING
Information Patent Application
MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFER
- Publication number 20250180645
- Publication date Jun 5, 2025
- QUALCOMM Incorporated
- Jais ABRAHAM
- G01 - MEASURING TESTING
Information Patent Application
TESTING CIRCUIT
- Publication number 20250155503
- Publication date May 15, 2025
- GLOBAL UNICHIP CORPORATION
- Yu-Lun Wan
- G01 - MEASURING TESTING
Information Patent Application
SYSTEM FOR AUTOMATED DATA RETRIEVAL FROM AN INTEGRATED CIRCUIT FOR...
- Publication number 20250123329
- Publication date Apr 17, 2025
- NVIDIA Corporation
- Padmanabham Patki
- G01 - MEASURING TESTING
Information Patent Application
Scan Data Transfer Circuits for Multi-die Chip Testing
- Publication number 20250093416
- Publication date Mar 20, 2025
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS
- Publication number 20250052813
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Application
SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION
- Publication number 20250035703
- Publication date Jan 30, 2025
- STMicroelectronics International N.V.
- Ankur BAL
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING
- Publication number 20250027992
- Publication date Jan 23, 2025
- Samsung Electronics Co., Ltd.
- Seaeun Park
- G01 - MEASURING TESTING
Information Patent Application
TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS
- Publication number 20250027994
- Publication date Jan 23, 2025
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME
- Publication number 20250020719
- Publication date Jan 16, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Mohammed Moiz Khan
- G01 - MEASURING TESTING
Information Patent Application
SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...
- Publication number 20240426908
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Andrea Floridia
- G01 - MEASURING TESTING
Information Patent Application
TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES
- Publication number 20240426907
- Publication date Dec 26, 2024
- STMicroelectronics International N.V.
- Shiv Kumar Vats
- G01 - MEASURING TESTING
Information Patent Application
LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME
- Publication number 20240426909
- Publication date Dec 26, 2024
- SAMSUNG ELECTRONICS CO,. LTD.
- Sangsoon IM
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING
- Publication number 20240418776
- Publication date Dec 19, 2024
- NORDIC SEMICONDUCTOR ASA
- Ashraf MOHAMMED
- G01 - MEASURING TESTING
Information Patent Application
TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...
- Publication number 20240402249
- Publication date Dec 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan Srinivasan
- G01 - MEASURING TESTING
Information Patent Application
Scan Chain Analysis Using Predefined Capture Signature
- Publication number 20240393394
- Publication date Nov 28, 2024
- Apple Inc.
- Bo Yang
- G01 - MEASURING TESTING
Information Patent Application
COMPRESSION-BASED SCAN TEST SYSTEM
- Publication number 20240393393
- Publication date Nov 28, 2024
- STMicroelectronics International N.V.
- Sandeep Jain
- G01 - MEASURING TESTING
Information Patent Application
CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION
- Publication number 20240385241
- Publication date Nov 21, 2024
- STMicroelectronics International N.V.
- Sandeep JAIN
- G01 - MEASURING TESTING
Information Patent Application
Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...
- Publication number 20240361385
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Anshuman Chandra
- G01 - MEASURING TESTING
Information Patent Application
Scan Flip-Flops With Pre-Setting Combinational Logic
- Publication number 20240361383
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Johnny Chiahao Li
- G01 - MEASURING TESTING
Information Patent Application
Segmented Boundary Scan Chain Testing
- Publication number 20240353490
- Publication date Oct 24, 2024
- Ee Mei Ooi
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS
- Publication number 20240345160
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G01 - MEASURING TESTING
Information Patent Application
MEMORY TIMING CHARACTERIZATION CIRCUITRY
- Publication number 20240319269
- Publication date Sep 26, 2024
- Intel Corporation
- Amit Agarwal
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND CO...
- Publication number 20240295604
- Publication date Sep 5, 2024
- STMicroelectronics International N.V.
- Gianluca TORTORA
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUS TO IMPLEMENT A BOUNDARY SCAN FOR SHARED ANALO...
- Publication number 20240288496
- Publication date Aug 29, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Prasanth Viswanathan Pillai
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN SECURITY CIRCUIT AND DRIVING METHOD THEREOF
- Publication number 20240280633
- Publication date Aug 22, 2024
- UIF (UNIVERSITY INDUSTRY FOUNDATION), YONSEI UNIVERSITY
- Sungho KANG
- G01 - MEASURING TESTING
Information Patent Application
FLIP-FLOP DEVICE AND METHOD OF OPERATING FLIP-FLOP DEVICE
- Publication number 20240275384
- Publication date Aug 15, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- GREG GRUBER
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN
- Publication number 20240241174
- Publication date Jul 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Mudasir KAWOOSA
- G01 - MEASURING TESTING

Scan chain arrangements

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Area, cost, and time-effective scan coverage improvement

Interposer circuit

Test pattern generation using multiple scan enables

Machine-learning-based design-for-test (DFT) recommendation system...

Dynamic voltage frequency scaling to reduce test time

Scan chains with multi-bit cells and methods for testing the same

Saving and restoring scan states

Integrated circuit, an apparatus for testing an integrated circuit,...

Secured scan access for a device including a scan chain

Flip-flop device and method of operating flip-flop device

Data gating using scan enable pin

Scan chain formation for improving chain resolution

Compression-based scan test system

Integrated circuit margin measurement for structural testing

Scan chain analysis using predefined capture signature

Test-time optimization with few slow scan pads

Registers

TVF transition coverage with self-test and production-test time red...

Methods and apparatus to implement a boundary scan for shared analo...

Reconfigurable JTAG architecture for implementation of programmable...

Scan frame based test access mechanisms

Scan compression through pin data encoding

Emulation of JTAG/SCAN test interface protocols using SPI communica...

Scan tree construction

Methods and apparatus to identify faults in processors

Wrapper cell design and built-in self-test architecture for 3DIC te...

Scan flip-flops with pre-setting combinational logic

Test access port architecture to facilitate multiple testing modes

Integrated test circuit, test assembly and method for testing an in...

Decompression circuit, circuit generation method, and IC chip

Patents Applicationslast 30 patents

SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME

ARCHITECTURE FOR TESTING MULTIPLE SCAN CHAINS

MODULAR SCAN DATA NETWORK FOR HIGH SPEED SCAN DATA TRANSFER

TESTING CIRCUIT

SYSTEM FOR AUTOMATED DATA RETRIEVAL FROM AN INTEGRATED CIRCUIT FOR...

Scan Data Transfer Circuits for Multi-die Chip Testing

BOUNDARY SCAN FOR SHARED ANALOG AND DIGITAL PINS

SCAN-SHIFT BUFFER ISOLATOR FOR DYNAMIC POWER REDUCTION

INTEGRATED CIRCUIT WITH MULTIPLEXER FOR TESTING

TEST-TIME OPTIMIZATION WITH FEW SLOW SCAN PADS

SCAN CHAINS WITH MULTI-BIT CELLS AND METHODS FOR TESTING THE SAME

SCAN-TESTABLE ELECTRONIC CIRCUIT AND CORRESPONDING METHOD OF TESTIN...

TEST PATTERN GENERATION USING MULTIPLE SCAN ENABLES

LOGIC BIST CIRCUIT AND SEMICONDUCTOR DEVICE INCLUDING SAME

INTEGRATED-CIRCUIT CHIP FOR RETENTION CELL TESTING

TVF TRANSITION COVERAGE WITH SELF-TEST AND PRODUCTION-TEST TIME RED...

Scan Chain Analysis Using Predefined Capture Signature

COMPRESSION-BASED SCAN TEST SYSTEM

CLUSTERING CLOCK CHAIN DATA FOR TEST-TIME REDUCTION

Wrapper Cell Design and Built-In Self-Test Architecture for 3DIC Te...

Scan Flip-Flops With Pre-Setting Combinational Logic

Segmented Boundary Scan Chain Testing

METHODS AND APPARATUS TO IDENTIFY FAULTS IN PROCESSORS

MEMORY TIMING CHARACTERIZATION CIRCUITRY

INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND CO...

METHODS AND APPARATUS TO IMPLEMENT A BOUNDARY SCAN FOR SHARED ANALO...

SCAN CHAIN SECURITY CIRCUIT AND DRIVING METHOD THEREOF

FLIP-FLOP DEVICE AND METHOD OF OPERATING FLIP-FLOP DEVICE

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

SECURED SCAN ACCESS FOR A DEVICE INCLUDING A SCAN CHAIN