Patent Application
20230345634
The present disclosure generally relates to information handling systems, and more particularly relates to a differential via design on a printed circuit board.
As the value and use of information continues to increase, individuals and businesses seek additional ways to process and store information. One option is an information handling system. An information handling system generally processes, compiles, stores, or communicates information or data for business, personal, or other purposes. Technology and information handling needs and requirements can vary between different applications. Thus information handling systems can also vary regarding what information is handled, how the information is handled, how much information is processed, stored, or communicated, and how quickly and efficiently the information can be processed, stored, or communicated. The variations in information handling systems allow information handling systems to be general or configured for a specific user or specific use such as financial transaction processing, airline reservations, enterprise data storage, or global communications. In addition, information handling systems can include a variety of hardware and software resources that can be configured to process, store, and communicate information and can include one or more computer systems, graphics interface systems, data storage systems, networking systems, and mobile communication systems. Information handling systems can also implement various virtualized architectures. Data and voice communications among information handling systems may be via networks that are wired, wireless, or some combination.
An information handling system includes a printed circuit board having a signal via fabricated through the printed circuit board. The signal via includes a conductive metal plating. The signal via also includes first and second via portions. The first via portion may be connected to a first trace of a differential pair. The second via portion may be connected to a second trace of the differential pair. The first and second via portions may be formed in the conductive metal plating.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the Figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements. Embodiments incorporating teachings of the present disclosure are shown and described with respect to the drawings herein, in which:
The use of the same reference symbols in different drawings indicates similar or identical items.
The following description in combination with the Figures is provided to assist in understanding the teachings disclosed herein. The description is focused on specific implementations and embodiments of the teachings, and is provided to assist in describing the teachings. This focus should not be interpreted as a limitation on the scope or applicability of the teachings.
PCB 100 includes a differential pair 102 and ground pads 104. Differential pair 102 includes pads 106 and 108. Each ground pad 104 may be physically and electrically coupled to a ground layer 110 of PCB 100 by a respective ground via 112 and ground trace 114. PCB 100 also includes signal vias 120 and 130. Signal via 120 is electrically and physically connected to pad 106 of differential pair 102 by a signal trace 122. Similarly, signal via 130 is electrically and physically connected to pad 108 of differential pair 102 by a signal trace 132. PCB 100 further includes ground vias 140 associated with signal vias 120 and 130. Ground vias 140, signal via 120, and signal via 130 may cover a particular length 150 on PCB 100.
In an example, a combination of ground pad 104, ground plane layer 110, ground via 112, and ground trace 114 may reduce crosstalk between differential pair 102 and an adjacent differential pair. The details of PCB manufacture, and particularly the forming of vias and traces on a PCB are known in the art and will not be further described herein, except as needed to illustrate the current embodiments.
PCB 100 may be utilized for transmission of high speed signals. In this situation, routing for the high speed signal on PCB 100 may need a lot of differential vias for signals. Additionally, PCB 100 may include a lot of ground vias to control a target impedance of a differential pair and to reduce crosstalk between adjacent differential pairs. The via design of PCB 100 may utilize via to via spacing to control the impedance of the differential pair, and may add one or more grounds vias to reduce crosstalk. This via design in PCB 100 may utilize a lot of routing space available in the PCB. In some cases, traditional differential via designs may exceed an available real estate for routing on PCB 100 when there is high density PCB routing.
Signal via 220 (portions 222 and 224) and ground vias 212 and 240 are utilized to interconnect two or more different metal layers within PCB 200. Additionally, signal via 220 and ground vias 212 and 240 may be utilized to connect the two or more different metal layers within PCB 200 with metal traces and/or metal pads on a surface of the PCB, such as pads 204, 206, and 208. While portions 222 and 224 of signal via 220 are illustrated and described as connected metal layers within PCB 200 to respective pads 206 and 208 via respective traces 232 and 234 on the surface of the PCB, traces 232 and 234 may be located within any layer within the PCB and portions 222 and 224 of signal via 220 may perform substantially similar functions without varying from the scope of this disclosure.
In an example, signal via 220 with via portions 222 and 224 may create a smaller structure as compared to signal vias 120 and 130 of PCB 100 in
After signal via 302 has been plated, two sections 310 and 312 of the plating of the signal via may be removed in any suitable manner. For example, a drill may be utilized to drill holes corresponding to sections 310 and 312 in signal via 302 as shown in
In an example, removed sections 310 and 312 would preferably be located along a line of symmetry for signal via 302, such that via portions 320 and 322 may be the same size. In an exemplary embodiment, the outer diameter of signal via 302 may be 25 mil and the diameter each of sections 310 and 312 may be 15 mil. In this embodiment, a distance from the center of section 310 to the center of section 312 may be 25 mil, a distance from the center of section 310 to the center of signal via 302 may be 12.5 mil, and a distance from the center of section 312 to the center of signal via 302 may be 12.5 mil. Additionally, in this embodiment, a distance from an inner edge of section 310 to an inner edge of section 312 may be 5 mil, a minimum spacing from an edge of section 310 to trace 304 or 306 may be 4 mil, and a minimum spacing from an edge of section 312 to trace 304 or 306 may be 4 mil. One of ordinary skill in the art would recognize that mil is a unit of measurement utilized in routing on PCBs, and one mil equals one-thousandth of an inch or two hundred fifty four ten-thousandths of a millimeter.
However, the locations for a drill to remove sections 310 and 312 may vary slightly, within a tolerance of +/−2 mil, in one or more directions from a desired drilling location. For example, the drill hole for removed section 310 may be slightly to the left of the line of symmetry for signal via 302, and the drill hole for removed section 312 may also be slightly to the left of the line of symmetry as shown in
At block 404, a via is fabricated in a PCB. In an example, the via may be any suitable type of via including, but not limited to, a through hole via, a micro via, and a skip via. At block 406, the via is plated with a conductive material. In an example, the conductive material may be copper. The details of PCB manufacture, and particularly the forming of vias and traces on a PCB are known in the art and will not be further described herein, except as needed to illustrate the current embodiments.
At block 408, first and second sections of the conductive material plated on the via are removed. In an example, the first and second sections may be removed by any suitable manner, such as drilling the first and second sections out of the conductive material or the like. In certain examples, the removal of the first and second sections may create first and second portions of the conductive material plated on the via. At block 410, a first trace is routed from the first portion of the conductive material to a first pad of a differential pair. At block 412, a second trace is routed from the second portion of the conductive material to a second pad of the differential pair, and the flow ends at block 414. In an example, the electrical communication from the first pad to the first portion of the conductive material through the first trace may provide a first signal path for a differential signal transmitted on the differential pair. The electrical communication from the second pad to the second portion of the conductive material through the second trace may provide a second signal path for the differential signal.
Information handling system 500 can include devices or modules that embody one or more of the devices or modules described below, and operates to perform one or more of the methods described below. Information handling system 500 includes a processors 502 and 504, an input/output (I/O) interface 510, memories 520 and 525, a graphics interface 530, a basic input and output system/universal extensible firmware interface (BIOS/UEFI) module 540, a disk controller 550, a hard disk drive (HDD) 554, an optical disk drive (ODD) 556, a disk emulator 560 connected to an external solid state drive (SSD) 562, an I/O bridge 570, one or more add-on resources 574, a trusted platform module (TPM) 576, a network interface 580, a management device 590, and a power supply 595. Processors 502 and 504, I/O interface 510, memory 520, graphics interface 530, BIOS/UEFI module 540, disk controller 550, HDD 554, ODD 556, disk emulator 560, SSD 562, I/O bridge 570, add-on resources 574, TPM 576, and network interface 580 operate together to provide a host environment of information handling system 500 that operates to provide the data processing functionality of the information handling system. The host environment operates to execute machine-executable code, including platform BIOS/UEFI code, device firmware, operating system code, applications, programs, and the like, to perform the data processing tasks associated with information handling system 500.
In the host environment, processor 502 is connected to I/O interface 510 via processor interface 506, and processor 504 is connected to the I/O interface via processor interface 508. Memory 520 is connected to processor 502 via a memory interface 522. Memory 525 is connected to processor 504 via a memory interface 527. Graphics interface 530 is connected to I/O interface 510 via a graphics interface 532, and provides a video display output 536 to a video display 534. In a particular embodiment, information handling system 500 includes separate memories that are dedicated to each of processors 502 and 504 via separate memory interfaces. An example of memories 520 and 530 include random access memory (RAM) such as static RAM (SRAM), dynamic RAM (DRAM), non-volatile RAM (NV-RAM), or the like, read only memory (ROM), another type of memory, or a combination thereof.
BIOS/UEFI module 540, disk controller 550, and I/O bridge 570 are connected to I/O interface 510 via an I/O channel 512. An example of I/O channel 512 includes a Peripheral Component Interconnect (PCI) interface, a PCI-Extended (PCI-X) interface, a high-speed PCI-Express (PCIe) interface, another industry standard or proprietary communication interface, or a combination thereof. I/O interface 510 can also include one or more other I/O interfaces, including an Industry Standard Architecture (ISA) interface, a Small Computer Serial Interface (SCSI) interface, an Inter-Integrated Circuit (I2C) interface, a System Packet Interface (SPI), a Universal Serial Bus (USB), another interface, or a combination thereof. BIOS/UEFI module 540 includes BIOS/UEFI code operable to detect resources within information handling system 500, to provide drivers for the resources, initialize the resources, and access the resources. BIOS/UEFI module 540 includes code that operates to detect resources within information handling system 500, to provide drivers for the resources, to initialize the resources, and to access the resources.
Disk controller 550 includes a disk interface 552 that connects the disk controller to HDD 554, to ODD 556, and to disk emulator 560. An example of disk interface 552 includes an Integrated Drive Electronics (IDE) interface, an Advanced Technology Attachment (ATA) such as a parallel ATA (PATA) interface or a serial ATA (SATA) interface, a SCSI interface, a USB interface, a proprietary interface, or a combination thereof. Disk emulator 560 permits SSD 564 to be connected to information handling system 500 via an external interface 562. An example of external interface 562 includes a USB interface, an IEEE 1394 (Firewire) interface, a proprietary interface, or a combination thereof. Alternatively, solid-state drive 564 can be disposed within information handling system 500.
I/O bridge 570 includes a peripheral interface 572 that connects the I/O bridge to add-on resource 574, to TPM 576, and to network interface 580. Peripheral interface 572 can be the same type of interface as I/O channel 512, or can be a different type of interface. As such, I/O bridge 570 extends the capacity of I/O channel 512 when peripheral interface 572 and the I/O channel are of the same type, and the I/O bridge translates information from a format suitable to the I/O channel to a format suitable to the peripheral channel 572 when they are of a different type. Add-on resource 574 can include a data storage system, an additional graphics interface, a network interface card (NIC), a sound/video processing card, another add-on resource, or a combination thereof. Add-on resource 574 can be on a main circuit board, on separate circuit board or add-in card disposed within information handling system 500, a device that is external to the information handling system, or a combination thereof.
Network interface 580 represents a NIC disposed within information handling system 500, on a main circuit board of the information handling system, integrated onto another component such as I/O interface 510, in another suitable location, or a combination thereof. Network interface device 580 includes network channels 582 and 584 that provide interfaces to devices that are external to information handling system 500. In a particular embodiment, network channels 582 and 584 are of a different type than peripheral channel 572 and network interface 580 translates information from a format suitable to the peripheral channel to a format suitable to external devices. An example of network channels 582 and 584 includes InfiniBand channels, Fibre Channel channels, Gigabit Ethernet channels, proprietary channel architectures, or a combination thereof. Network channels 582 and 584 can be connected to external network resources (not illustrated). The network resource can include another information handling system, a data storage system, another network, a grid management system, another suitable resource, or a combination thereof.
Management device 590 represents one or more processing devices, such as a dedicated baseboard management controller (BMC) System-on-a-Chip (SoC) device, one or more associated memory devices, one or more network interface devices, a complex programmable logic device (CPLD), and the like, that operate together to provide the management environment for information handling system 500. In particular, management device 590 is connected to various components of the host environment via various internal communication interfaces, such as a Low Pin Count (LPC) interface, an Inter-Integrated-Circuit (I2C) interface, a PCIe interface, or the like, to provide an out-of-band (00B) mechanism to retrieve information related to the operation of the host environment, to provide BIOS/UEFI or system firmware updates, to manage non-processing components of information handling system 500, such as system cooling fans and power supplies. Management device 590 can include a network connection to an external management system, and the management device can communicate with the management system to report status information for information handling system 500, to receive BIOS/UEFI or system firmware updates, or to perform other task for managing and controlling the operation of information handling system 500. Management device 590 can operate off of a separate power plane from the components of the host environment so that the management device receives power to manage information handling system 500 when the information handling system is otherwise shut down. An example of management device 590 include a commercially available BMC product or other device that operates in accordance with an Intelligent Platform Management Initiative (IPMI) specification, a Web Services Management (WSMan) interface, a Redfish Application Programming Interface (API), another Distributed Management Task Force (DMTF), or other management standard, and can include an Integrated Dell Remote Access Controller (iDRAC), an Embedded Controller (EC), or the like.
Management device 590 may further include associated memory devices, logic devices, security devices, or the like, as needed or desired.
Although only a few exemplary embodiments have been described in detail herein, those skilled in the art will readily appreciate that many modifications are possible in the exemplary embodiments without materially departing from the novel teachings and advantages of the embodiments of the present disclosure. Accordingly, all such modifications are intended to be included within the scope of the embodiments of the present disclosure as defined in the following claims. In the claims, means-plus-function clauses are intended to cover the structures described herein as performing the recited function and not only structural equivalents, but also equivalent structures.
The above-disclosed subject matter is to be considered illustrative, and not restrictive, and the appended claims are intended to cover any and all such modifications, enhancements, and other embodiments that fall within the scope of the present invention. Thus, to the maximum extent allowed by law, the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents, and shall not be restricted or limited by the foregoing detailed description.
