The invention relates to high speed analog-to-digital converters (ADC) and, more particularly, to digital equalization in frequency down converters intended for wireless receivers.
Down converters in wireless receivers perform a transformation of a radio frequency (RF) signal into a baseband signal centered at the zero frequency. In high performance equipment, digital down converters are used, making it necessary to convert an analog RF signal into a digital signal. Typically, a high speed ADC is used because of the high frequency of the RF signal.
High speed analog to digital converters are built as composite ADCs that consist of a number of interleaved sub-ADCs with a common input and sequential timing. In general, the amplitude and phase frequency responses of the different sub-ADCs are not identical, resulting in specific signal distortions, for example, the appearance of spurious frequency components. To prevent these distortions, equalization of the responses of the sub-ADCs is used (see, for example, U.S. Pat. No. 7,408,495).
A block diagram of a conventional digital down converter with an equalizer is shown in
The ADC equalizer and low pass filters in the block diagram of
It is possible to reduce to some extent, the required number of multipliers in the conventional down converter of the type shown in
A down converter with a reduced number of multipliers was suggested in U.S. Pat. No. 9,148,162. In a down converter according to the '162 patent, equalization is combined with down conversion and performed in I and Q branches separately. Furthermore, three cascade-connected units in each branch (equalizer, mixer and low pass filter) are replaced by a single equivalent finite impulse response filter (FIR). A decimator is placed inside that FIR before the multipliers. As a result, the frequency of each multiplication in the down converter is lowered and the number of required multipliers is reduced significantly.
A block diagram of a digital down converter with equalization in accordance with U.S. Pat. No. 9,148,162 is shown in
The reduction of the number of required multipliers in the block diagram of
In particular, the down converter according to
The FIR-decimators incorporated in the block diagram of
It is desirable to provide an improved digital down converter, which is able to equalize asymmetrical frequency responses, as well as symmetrical ones, and makes possible implementation by conventional computing devices.
A digital down converter, for example, useful in radio receivers, is a device generally including a composite ADC, that performs demodulation of a received radio frequency signal, converting the signal into a pair of baseband signals: an in phase baseband signal I, and a quadrature baseband signal Q. The main parameters of a frequency down converter are carrier frequency Fc, sampling rate B of the modulated I/Q baseband signals, sampling frequency Fs of the ADC, the number P of sub-ADCs in the used composite ADC, the complex valued frequency responses H(p, F) of the different sub-ADCs (p being a number of a sub-ADC), and the operation frequency Fo of the used computing resources.
In that structure, the digital down converter (the “DDC”) carries out several operations:
The down converter according to the block diagram of
The prior art down converter according to the block diagram of
According to the present invention, the determination of a next pair of the output I and Q samples is carried out by a calculation of a convolution of a corresponding piece of the input signal with a proper set of coefficients. Those coefficients are determined in such a way that the convolution calculation is equivalent to the execution of the operations just listed. The convolution calculation is performed by a set of processing units operating in parallel, thus providing for compliance with the inner structure of contemporary computing devices, such as FPGAs.
In the present invention, equalization is performed using a complex signal processing approach (see, for example, K. W. Martin, “Complex Signal Processing Is Not Complex”, IEEE Trans. Circuits and Systems, vol. 51, pp. 132-139, September 2004). An asymmetrical (in the frequency domain) equalizer with a transfer function that does not have the conjugate symmetry of real filters, is built by using cross-coupling between real and imaginary signal paths. This implies that the equalizer performs a convolution of the processed signal with a set of complex coefficients.
It is known, that to ensure an accurate compensation of frequency distortions in a composite ADC, the equalizer coefficients should be calculated taking into account not only the frequency responses of the sub-ADCs which produce current samples, but also the frequency responses of the ADCs which produced adjacent samples as well. The herein illustrated embodiment of the present invention is configured to calculate coefficients using the frequency responses of all the sub-ADCs of the composite ADC. This system and method is novel and is more straightforward than previously known ones and is suitable for calculation of complex equalizer coefficients.
A block diagram of a first embodiment of a digital down converter 10 is shown in
An analog input signal on input line 30 is converted by ADC 31 into a high speed digital signal with a sampling rate Fs. The data from the ADC 31 are transmitted to the following units through bus 32, which preferably is a certain type, for example, LVDC or Serializer/Deserializer (SerDes), although other types can be used. The bus receiver 41 divides the input data stream into M=Fs/Fo lines, each line having data frequency Fo, equal to the operation frequency of the apparatus.
The lines from bus receiver 41 are applied to the inputs of the mixers unit 42. At mixers unit 42, the sample with a number n, which arrived over one of the lines, is multiplied by cos (2π·Fc/Fs·n) and simultaneously by sin (2π·Fc/Fs·n). The two products are placed at the corresponding outputs 1c, . . . , Mc and 1s, . . . , Ms, of the mixers unit 42, wherein the number of outputs is 2·M.
The outputs of the mixers unit 42 are connected to the inputs of a pair of samples distributors 43 by cosine lines 1c, . . . , Mc and sine lines 1s, . . . , Ms. During a period of the frequency Fo, each of the samples distributors 43 receives M samples. A buffer register, incorporated in the samples distributor 43, delays each input sample by one period of the frequency Fo. In that way, a second set of M samples is created. The incoming samples and the delayed samples together form a set of 2M samples, wherein those samples are numbered in accordance with the order of appearance in the input signal.
The number of outputs, K, of each of the samples distributor 43, equals the ratio B/Fo, where B is the sampling rate of the baseband signals at the outputs of the down converter. The ratio of the ADC sampling rate Fs to the sampling rate of the baseband signals at the outputs of the down converter B is called the decimation factor DF.
The samples distributor 43 produces at the output with the number i (0≦i<K) a word Wi according to a rule: Wi={Si·DF, Si·DF+1, . . . , Si·DF+L−1}, where Sm is a sample with the number m from the set of 2M samples. In the samples distributor 43, which is connected to the mixers unit 42 by the cosine lines, the produced word Wi is placed on a bus labeled Bic, whereas in the samples distributor 43, which is connected to the mixers unit 42 by the sine lines, the produced word Wi is placed on a bus labeled Bis. The number of samples in a word Wi equals L, therefore the number of lines in each output bus of the samples distributors 43 equals L also.
The output bus of the samples distributor 43 with a number i, is connected to one of K processing units 34 with the same number. The bus Bic leads to an I input of the processing unit 34 with the number i and the bus Bis leads to a Q input of the processing unit 34 with the number i.
The processing unit 34 with the number i processes the two words received from the samples distributors 43 and produces at its two outputs, samples Ii and Qi of resulting baseband signals. The set of samples Ii, 0≦i<K forms the output I of the down converter, and the set of samples Qi, 0≦i<K forms the output Q of the down converter.
The samples that come to I and Q inputs of the processing unit 34 may be considered as a real and imaginary parts of a complex sample Zn, where n is the number of the sample in the initial signal produced by ADC 31. The processing unit 34 calculates the outputs samples Ii and Qi as a convolution of the samples Zn with prepared-in-advance complex coefficients Cp,k, which control the operation of the down converter, according to:
where p is the number of sub-ADC that produced the middle sample of the word Wi, and k is the number of coefficient in the set of L coefficients.
As can be readily appreciated, due to the arrangement of the samples distributor 35 described above, each of the processing units 34 receives at its input a set of L samples, these samples constituting a piece of the digital signal produced by ADC 31. The pieces that come to the inputs of the different K processing units 34 are spaced in the digital signal by an interval equal to the decimation factor DF. For this reason, the samples rate at the outputs of the down converter is Fo·K=B, which equals the rate of processed pieces succession in the digital signal.
All processing units are the same, and the distinction lies in the sets of samples coming to the inputs and in the sets of coefficients loaded in them. A block diagram of a processing unit is shown in
The equalization of the sub-ADCs misalignment in a composite ADC requires the use of P sets of coefficients Cp,k, a set containing L coefficients. The number p of a set (0≦p<P) equals the number of sub-ADC that produced processed sample.
The block diagram of the processing unit is a conventional block diagram of a complex filter. The operation of a processing unit is controlled by an assembly of sets of complex coefficients {Cp,k} that are loaded into it. The real parts of the of complex coefficients Dp,k=Re(Cp,k) are loaded into the direct branches of the processing unit—into the arithmetic units 52 and 55. The imaginary parts of the of complex coefficients Ep,k=Im(Cp,k) are loaded into the cross branches of the processing unit—into the arithmetic units 53 and 54.
A block diagram of an exemplary arithmetic unit 34 is shown in the
To analyze the operation of the down converter, consider that a complex exponential s0(n)=exp(j·2π·F/Fs·n) is applied to the input of the ADC 31 (where n is the number of a current sample). The sample with the number n is processed by an sub-ADC with the number p=n mod(P), where P is the number of sub-ADCs in the composite ADC. If the complex frequency response of the sub-ADC with the number p is Hp(F), then the output of ADC is s1(n)=Hp(F)·exp(j·2π·F/Fs·n). The multipliers in the mixers unit 34 produce two products: s1(n)·cos(2π·Fc/Fs·n) and s1(n)·sin (2π·Fc/Fs·n). This operation is equivalent to multiplication of the samples s1(n) by a complex exponential exp(−j·2π·Fc/Fs·n) and generation of a product exp(j·2π·(F−Fc)/Fs·n). The samples distributors 43 assemble these products into words with the length L and send them to the processing units 34. The processing units 34 forms a convolution of received words with the coefficients C(p,k), so that the sample Z(n) at the output of the down converter equals
and the frequency response FR(F) of the down converter equals
The calculations of the coefficients C(p, k) are based on the requirement that the frequency response FR(F) of the down converter equals a target response T[F], this requirement leading to a following equation for determination of the control coefficients.
Since the number of the control coefficients equals L, it is possible to ensure that the previous equation is true at L frequencies Fm, 0≦m<L. It brings us to P systems of L linear equations each with the control coefficients as unknowns:
The solution of the received set of P system of linear equations determines the P sets, containing each of the L control coefficients. The L control coefficients are loaded into the coefficients memory of the processing units 34 and ensure that the joint operation of ADC 31, mixers unit 42, samples distributors 43 and K processing units 34 perform a transformation of the input analog signal into I/Q baseband signals, which is completely equivalent to the transformation performed by a conventional down converter of the
In some cases, a different design of a down converter is preferable, which may lead to further reduction of required number of multipliers. A block diagram of a corresponding exemplary embodiment of the present invention is shown in
In this exemplary embodiment of the present invention, the processing unit 34′ is described by the block diagram of
The above described method of digital down conversion with equalization, was verified using a computer simulation. In that simulation, a 16-level quadrature modulated signal was generated with sample rate 2 Gs/s. That, signal was transmitted through a square-root raised cosine filter, up-converted with a 10 GHz carrier frequency and applied to a composite ADC having 40 sub-ADCs. The 40 sub-ADC model was used to simulate ADC distortions at high frequency. The signal produced by the ADC, was down-converted using equalizer coefficients calculated with a square-root raised cosine target filter according to the present invention. The quality of the demodulated down-converted signal was estimated using an error vector magnitude (EVM) method.
In summary, the forms of the invention illustrated in both
In the form of the invention illustrated in
In the form of the invention illustrated in
In the form of
Although the foregoing description of the embodiment of the present invention contains some details for purposes of clarity of understanding, the invention is not limited to the detail provided. There are many alternative ways of implementing the invention. The disclosed embodiments are illustrative and not restrictive.
Number | Name | Date | Kind |
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7408495 | Stein et al. | Aug 2008 | B2 |
8831085 | Hezar | Sep 2014 | B2 |
9148162 | Stein et al. | Sep 2015 | B2 |
20160241253 | Taratorin et al. | Aug 2016 | A1 |
Entry |
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Co-pending U.S. Appl. No. 15/229,578, filed Aug. 5, 2016, in the name of Guzik Technical Enterprises. |