Diode and Power Circuit

Abstract

A diode and a power circuit are provided. The diode may include: a first electrode layer; a drift layer located above the first electrode layer, a doping concentration of the drift layer is less than that of the first electrode layer; and the drift layer includes an active region and a terminal region surrounding the active region; a second electrode layer disposed in the active region, where the second electrode layer and the drift layer are doped with impurities of different properties; and the second electrode layer includes a first region and a second region surrounding the first region, and the first region and the second region are separated by a first insulation trench, where the first region is connected to a power supply through a first conductor, and the second region is connected to the power supply through a second conductor, a first resistor, and the first conductor sequentially.

Description

Claims

1-12. (canceled)

13. A diode, comprising: a first electrode layer;a drift layer located above the first electrode layer, wherein the drift layer and the first electrode layer are doped with impurities of a same property, a second doping concentration of the drift layer is less than a first doping concentration of the first electrode layer, and the drift layer comprises an active region and a terminal region surrounding the active region; anda second electrode layer disposed in the active region, wherein the second electrode layer and the drift layer are doped with impurities of different properties, the second electrode layer comprises a first region and a second region surrounding the first region, and the first region and the second region are separated by a first insulation trench,a first conductor disposed above the first region;a second conductor disposed above the second region; anda first resistor disposed between the first conductor and the second conductor,wherein the first region is connected to a power supply through the first conductor, and the second region is connected to the power supply through the second conductor, the first resistor, and the first conductor sequentially.

14. The diode according to claim 13, wherein a second depth by which the second region extends into the active region is greater than a first depth by which the first region extends into the active region.

15. The diode according to claim 13, wherein the first region comprises a plurality of third regions above the active region, adjacent third regions in the plurality of third regions are separated by a second insulation trench, and a fourth depth by which the second insulation trench extends into the active region is greater than a third depth by which a third region of the plurality of third regions extends into the active region.

16. The diode according to claim 13, wherein a barrier layer is disposed between the first region and the active region, and the barrier layer is configured to slow down migration of a carrier between the first region and the active region.

17. The diode according to claim 13, wherein the first resistor is made of polycrystalline silicon.

18. The diode according to claim 13, wherein a first semiconductor layer is disposed between the drift layer and the first electrode layer, the drift layer and the first semiconductor layer are doped with impurities of the same property, and a third doping concentration of the first semiconductor layer is between the second doping concentration of the drift layer and the first doping concentration of the first electrode layer.

19. The diode according to claim 13, wherein the first region and the second region are doped with an acceptor impurity, and the first electrode layer and the drift layer are doped with a donor impurity, orwherein the first region and the second region are doped with a donor impurity, and the first electrode layer and the drift layer are doped with an acceptor impurity.

20. The diode according to claim 13, wherein at least one field limiting ring is disposed in the terminal region.

21. The diode according to claim 20, wherein a metal field plate is disposed above the field limiting ring.

22. The diode according to claim 21, wherein the diode further comprises a resistive field plate surrounding the metal field plate.

23. The diode according to claim 13, wherein the diode further comprises a cut-off ring surrounding an upper portion of the terminal region.

24. A power circuit, comprising: an insulated gate bipolar transistor; anda diode, the diode including: a first electrode layer;a drift layer located above the first electrode layer, wherein the drift layer and the first electrode layer are doped with impurities of a same property, a second doping concentration of the drift layer is less than a first doping concentration of the first electrode layer, and the drift layer comprises an active region and a terminal region surrounding the active region; anda second electrode layer disposed in the active region, wherein the second electrode layer and the drift layer are doped with impurities of different properties, the second electrode layer comprises a first region and a second region surrounding the first region, and the first region and the second region are separated by a first insulation trench,a first conductor disposed above the first region;a second conductor disposed above the second region; anda first resistor disposed between the first conductor and the second conductor,wherein the first region is connected to a power supply through the first conductor, and the second region is connected to the power supply through the second conductor, the first resistor, and the first conductor sequentially.

25. The power circuit according to claim 24, wherein a second depth by which the second region extends into the active region is greater than a first depth by which the first region extends into the active region.

26. The power circuit according to claim 24, wherein the first region comprises a plurality of third regions above the active region, adjacent third regions in the plurality of third regions are separated by a second insulation trench, and a fourth depth by which the second insulation trench extends into the active region is greater than a third depth by which a third region of the plurality of third regions extends into the active region.

27. The power circuit according to claim 24, wherein a barrier layer is disposed between the first region and the active region, and the barrier layer is configured to slow down migration of a carrier between the first region and the active region.

28. The power circuit according to claim 24, wherein the first resistor is made of polycrystalline silicon.

29. The power circuit according to claim 24, wherein a first semiconductor layer is disposed between the drift layer and the first electrode layer, the drift layer and the first semiconductor layer are doped with impurities of the same property, and a third doping concentration of the first semiconductor layer is between the second doping concentration of the drift layer and the first doping concentration of the first electrode layer.

30. The power circuit according to claim 24, wherein the first region and the second region are doped with an acceptor impurity, and the first electrode layer and the drift layer are doped with a donor impurity, orwherein the first region and the second region are doped with a donor impurity, and the first electrode layer and the drift layer are doped with an acceptor impurity.

31. The power circuit according to claim 24, wherein at least one field limiting ring is disposed in the terminal region.

32. The power circuit according to claim 31, wherein a metal field plate is disposed above the field limiting ring.