Direct Contact to Area Efficient Body Tie Process Flow

Abstract

A process flow for fabricating shallow trench isolation (STI) devices with direct body tie contacts is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, body tie contacts are etched through the nitride layer and STI oxide layer, directly to the body tie. This process flow provides a direct body tie contact to mitigate floating body effects but also eliminates hysteresis and transient upset effects common in non-direct body tie contact configurations, without the critical alignment requirements and critical dimension control of the layout.

Description

FIELD OF THE INVENTION

The present invention relates to Field Effect Transistor (FET) fabrication processes, and more particularly, to a process flow providing direct contact to the body tie silicon.

BACKGROUND

One issue that FETs fabricated in a Silicon on Insulator (SOI) substrate may experience is a floating body effect. In such FETs, floating body effects are a result of having a body region that is electrically isolated from a bulk substrate. In order to supply a voltage potential to the body, and therefore mitigate floating body effects, an applied bias is often supplied from a body-contact to the body. When a body-contact receives an applied bias, which may be a ground or a positive or negative potential, it carries it to the body via a body tie. Often, the body-tie is formed in device layer silicon and runs beneath an oxide, and in general, the body tie allows the body region and the body-contact to be in remote locations in an SOI substrate.

Conventional SOI devices without body ties are susceptible to hysteresis and transient upset effects. Body tie contacts can help control the hysteresis and transient upset effects, but the layout density of current area efficient body tie fabrication process flows is limited by the n or p masking layer alignment and critical dimension control in order to contact the body tie. As such, a fabrication process flow that eliminates the critical alignment and dimension control requirements to improve the layout density, while mitigating body effects, is desired.

SUMMARY

In an exemplary embodiment, a process flow for fabricating a shallow trench isolation (STI) device with direct body tie contact is provided. The process flow follows steps similar to standard STI fabrication methods except that in one of the etching steps, an opening is etched through the nitride mask and STI oxide layer, directly to the body tie silicon. This adjustment in the process flow allows contacts to be directly landed on the body tie, thus addressing the issues related to floating body effects by providing a direct body contact that eliminates hysteresis and transient upset effects common in non body contact configurations, without the critical alignment requirements and critical dimension control of the layout as in previous body contact configurations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a pictorial diagram illustrating a top view of the layout configuration with direct body tie contact, according to an embodiment of the present invention.

FIG. 2 a is a pictorial diagram of a cross-section cut through the top view of FIG. 1, according to an embodiment of the present invention.

FIG. 2 b is a pictorial diagram of a cross-section cut through the top view of FIG. 1 during an n+ implant step, according to an embodiment of the present invention.

FIG. 3 is a flow diagram of an STI scheme, according to an embodiment of the present invention.

DETAILED DESCRIPTION

FIG. 1 is a pictorial diagram illustrating a top view of the layout configuration of a Shallow Trench Isolation (STI) device 100. The STI device 100 comprises a buried oxide layer 102, over which an n+ drain 106, n+ source 108 and p+ tap 112 are formed with a body tie layer 104 in between. A gate 110a,b is formed between the n+ drain 106 and n+ source 108 regions. Each of the n+ drain 106, n+ source 108, gate 110 and p+ tap 112 are accessed via contacts 114, 116, 118, and 120 respectively.

Note that the layout configuration of the STI device 100 has a body contact in a separate active area 112 from the source and drain. Unless the body tie silicon 104 is electrically connected by the standard contact 120 through the p+ tap 112 or the direct body tie contact 122, the STI device 100 may be susceptible to hysteresis and transient upset effects. However, a direct body tie contact 122 provides a direct connection to the body tie 104 eliminating the need for critical alignment and dimension control requirements in the n+/p+ lithography processes as well as the elimination of the p+ tap 112 feature. This improves the layout density while reducing the cost of the n+/p+ lithography steps.

FIG. 3 is a flow diagram of an STI scheme 300, according to an embodiment of the present invention. The fabrication process flow of the STI device 100 begins with the step of providing an SOI wafer with a top silicon layer 302, followed by the step of patterning the top silicon with a photoresist mask 304. Once the hardmask is formed, two separate silicon etching steps 306 are performed to form the multi-tiered body tie 104 structure. After the structures are formed, the steps of oxide deposition 308 and oxide planarization 310 are performed, after which the forming of a gate oxide and polysilicon gate layer 312 step takes place. After the formation of the gate layer, doping levels of the n+ drain 106 and n+ source 108 are established 314 by a series of implants. This series of implants requires separate masks for n+ doping and p+ doping. After the establishment of the source and drain doping levels 314, the formation of contacts 316 takes place. A drain contact 114, a source contact 116, a gate contact 118 and a p+ tap contact 120 are formed at the drain region 106, the source 108 region, the gate region 110 and the p+ tap region 112, respectively.

At this point, an additional step of etching through to the body tie silicon 318 is included. An opening is etched through the nitride etch-stop layer down to the body tie silicon 104, after which a direct contact 122 to the body-tie 104 is formed 320. This adjustment to the process flow removes the requirement that a body tie contact must occur in a normal active area, which is a feature that must be lithographically designated in the active area masking and etch steps, the n+ and p+ masking and doping steps, and the implantation step.

FIG. 2 a is a pictorial diagram of the cross-section cut through along the X-X′ plane of the STI device configuration shown in FIG. 1. Buried oxide layer 202 isolates the device silicon areas 204, 208, 212 and 214 from the silicon substrate 201. A deposited and subsequently CMP planarized oxide 206 comprises the STI oxide isolation. The n+ source 208, p+ tap 212 and multi-tiered body tie 204 structures correspond to the n+ source 108 region, p+ tap 112 region, and body tie 104 region in FIG. 1, respectively. The multi-tiered body tie structure 204 is formed by two separate silicon etches as described above. A layer of silicon 214 remains after the silicon etches. A nitride layer 210 provides a hard mask etch stop for potential subsequent processing steps and the STI oxide layer 206 blocks the n+ and p+ source and drain implants from doping the underlying body tie silicon layer 214.

P+ contact 220, n+ source contact 216, and direct body tie contact 222 correspond to p+ tap contact 120, n+ source contact 116 and direct body tie contact 122 in FIG. 1, respectively. As shown, p+ tap contact 220 and n+ source contact 216 connects to the p+ tap 212 and n+ source 208 respectively by etching through the nitride layer 210. The direct body tie contact 222 connects to the body tie 204 by etching through the nitride layer as well as the STI oxide layer. The direct body tie contact 222 is oriented vertically and of unitary construction. The interface of where the direct contact occurs is such that a least a portion of the direct body tie contact 222 overlays at least a portion of the body tie structure 204. In an alternative embodiment, if the selectivity to the source, drain, or gate contact areas are not sufficient to etch to the body tie, then the body tie contact lithography etch can be done before the source, drain and gate contacts are formed.

In another alternative embodiment, the p+ tap feature can be eliminated in this direct body tie contact configuration, since it is no longer needed. Eliminating the p+ tap feature also eliminates the need for a photoresist mask feature at a minimum design rule distance from the n-channel transistor during the n+ implant. FIG. 2b is a pictorial diagram of the cross-section cut through along the X-X′ plane of the STI device configuration shown in FIG. 1, during an n+ implant step. For reference, the columns 220′, 216′, and 222′ are where contacts 220, 216 and 222 will be formed in a later step, as shown in FIG. 2a. The photoresist 224 is necessary when a p+ tap feature is implemented, but can be left out in this alternative embodiment. As such, eliminating the p+ tap feature can improve the density as well as reduce the lithography costs of the device.

Further, an additional lithography and implant step can be performed after the direct body tie contact has been formed to increase the doping in the direct body tie contact to reduce contact resistance. In this case, the direct body tie contact implants only go into the contact areas so n+ and p+ spacing requirements are still relaxed. Note that dopant activation to improve performance can optionally occur in a typical contact TiN liner anneal step. In view of the various embodiments of the present invention, the best case scenario requires no additional processing, and the worst case scenario requires one additional contact mask and etch step, and two reuses of well masks during two additional implants.

Although the presented method has been described with reference to an STI scheme in an SOI process, it may, however, be carried out at other points of an SOI process. The presented direct body-tie contact may be particularly advantageous in radiation hardened circuits. However, it is also contemplated that such a body-tie may also be used where appropriate in a non-radiation hardened circuit. It should be understood, therefore, that the illustrated examples are examples only and should not be taken as limiting the scope of the present invention. Also, the claims presented below should not be read as limited to the described order or elements unless stated to that effect. Therefore, all examples that come within the scope and spirit of the following claims and equivalents thereto are claimed as the invention.

Claims

1. A method for fabricating a semiconductor device comprising: fabricating source and drain active regions;fabricating a multi-tiered body tie structure; andforming contacts to the source, drain and body tie, wherein the body tie contact is coupled directly to the body tie silicon.

2. The method as in claim 1, further comprising etching through any intermediate layers such that the contacts can directly couple with the respective active regions and body tie.

3. The method of claim 1, wherein the body tie contact is vertically oriented.

4. The method of claim 1, wherein the body tie contact is of unitary construction.

5. The method of claim 1, wherein at least a portion of the body tie contact overlays at least a portion of the body tie structure.

6. The method as in claim 1, further comprising performing dopant implantation after the contacts have been formed to reduce contact resistance.

7. The method as in claim 1, wherein fabricating a multi-tiered body tie structure comprises at least two separate etching steps.

8. A semiconductor device having a multi-tiered structure comprising: a multi-tiered silicon layer with a body tie;an oxide layer overlaying the multi-tiered silicon layer with a body tie; anda body tie contact providing a direct electrical connection to the body tie silicon.

9. The semiconductor device of claim 8, further comprising source, drain and gate regions.

10. The semiconductor device of claim 9, wherein the source and drain are n-type.

11. The semiconductor device of claim 9, wherein the source and drain are p-type.

12. The semiconductor device of claim 8, wherein a least a portion of the body tie contact overlays at least a portion of the body tie.

13. The semiconductor device of claim 8, wherein the body tie contact is vertically oriented.

14. The semiconductor device of claim 8, wherein the body tie contact is of unitary construction.

15. A method for fabricating a semiconductor device comprising: providing an SOI wafer with a top silicon layer;patterning the top silicon layer;etching the top silicon layer to form multi-tiered body tie, source, and drain structures;depositing an oxide layer over the multi-tiered silicon structures;planarizing the oxide layer;patterning and forming a gate layer;establishing doping levels in the source and drain structures via implants;forming contacts to the source, drain, and gate structures;etching through portions of the oxide layer and multi-tiered silicon structure to the body tie structure; andforming a body tie contact directly to the body tie structure.

16. The method of claim 15, wherein the body-tie contact is oriented vertically.

17. The method of claim 15, wherein the body-tie contact is of unitary construction.

18. The method of claim 15, wherein at least a portion of the body tie contact overlays at least a portion of the body tie structure.

19. The methods of claim 15, further comprising performing dopant implantation after the contacts have been formed to reduce contact resistance.

20. The method of claim 15, wherein etching the top silicon layer to form multi-tiered body tie, source and drain structures comprises at least two separate etching steps.