Patent Application
20250218937
Formation of back-side contacts and/or gate vias is limited, sometimes severely, by edge placement errors between back-side patterns and front-side features. Typical patterning misalignments may be dwarfed by wafer distortions at least along certain orientations. Such misalignments may significantly degrade integrated circuit (IC) device performance or prevent further down-scaling of transistor arrays.
New techniques, structures, and materials are needed to improve front- and back-side feature alignments.
The material described herein is illustrated by way of example and not by way of limitation in the accompanying figures. For simplicity and clarity of illustration, elements illustrated in the figures are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference labels have been repeated among the figures to indicate corresponding or analogous elements, e.g., with the same or similar functionality. The disclosure will be described with additional specificity and detail through use of the accompanying drawings:
In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. The various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter.
References within this specification to “one embodiment” or “an embodiment” mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase “one embodiment” or “in an embodiment” does not necessarily refer to the same embodiment. In addition, the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled.
The terms “over,” “to,” “between,” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
The terms “coupled” and “connected,” along with their derivatives, may be used herein to describe structural relationships between components. These terms are not intended as synonyms for each other. Rather, in particular embodiments, “connected” may be used to indicate that two or more elements are in direct physical or electrical contact with each other. “Coupled” may be used to indicate that two or more elements are in either direct or indirect (with other intervening elements between them) physical or electrical contact with each other, and/or that the two or more elements co-operate or interact with each other (e.g., as in a cause-and-effect relationship, an electrical relationship, a functional relationship, etc.).
The term “circuit” or “module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The term “signal” may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of “a,” “an,” and “the” include plural references. The meaning of “in” includes “in” and “on.”
The vertical orientation is in the z-direction and recitations of “top,” “bottom,” “above,” and “below” refer to relative positions in the z-dimension with the usual meaning. However, embodiments are not necessarily limited to the orientations or configurations illustrated in the figure.
The terms “substantially,” “close,” “approximately,” “near,” and “about,” generally refer to being within +/−10% of a target value (unless specifically specified). Unless otherwise specified in the specific context of use, the term “predominantly” means more than 50%, or more than half. For example, a composition that is predominantly a first constituent means more than half of the composition is the first constituent. The term “primarily” means the most, or greatest, part. For example, a composition that is primarily a first constituent means the composition has more of the first constituent than any other constituent. A composition that is primarily first and second constituents means the composition has more of the first and second constituents than any other constituent.
Unless otherwise specified the use of the ordinal adjectives “first,” “second,” and “third,” etc., to describe a common object, merely indicate that different instances of like objects to which are being referred and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.
For the purposes of the present disclosure, phrases “A and/or B” and “A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase “A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).
Views labeled “cross-sectional,” “profile,” and “plan” correspond to orthogonal planes within a cartesian coordinate system. Thus, cross-sectional and profile views are taken in the x-z and y-z planes, and plan views are taken in the x-y plane. Typically, profile views in the x-z plane are cross-sectional views. Where appropriate, drawings are labeled with axes to indicate the orientation of the figure.
Materials, structures, and techniques are disclosed to improve the alignment and scaling of integrated circuit (IC) devices having transistors between and coupled to front- and back-side interconnect networks.
Typical patterning methods may be insufficiently precise to properly align front- and back-side features in IC devices, particularly given the nonstop scaling down of devices. A method is described to form back-side arrays of sacrificial materials precisely aligned to transistor structures formed on a front side. Directed self-assembly (DSA) may be used to form an array or grating of contacts and dielectric structures on a back side to precisely match a similar array on a front side. The DSA grating may be aligned with transistor gate electrodes revealed on the back side and allow for further self-aligned back-side contacts and vias. Self-alignment may be limited to a single, key dimension (e.g., parallel to a longitudinal direction of a channel region).
Such self-aligned features enable back-side interconnects with continued device scaling. In addition to near-perfect alignment between front- and back-side features (e.g., front- and back-side spacer layers), described structures may include gate electrodes with thick bottoms to facilitate back-side reveal and subsequent alignment.
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Notably, the gate electrode may be received (or formed) with an unconventional thickness of metal under a channel region. For example, in embodiments having channel regions in stacks of nanoribbons and extending through the gate electrodes, a lowest nanoribbon in a stack (e.g., opposite or away from an interconnect network over the transistor structures) may have a same thickness, or less, of metal opposite or away from an interconnect network as between adjacent nanoribbons. That is, a vertical pitch or distance between adjacent nanoribbons may determine a consistent thickness of metal between adjacent nanoribbons, and the lowest nanoribbon in a stack may have approximately the same thickness of metal under the lowest nanoribbon (e.g., away from the interconnect network and the other nanoribbons). In some embodiments described herein, a gate electrode has gate metal under the nanoribbon stack with a thickness of two or three times the thickness of gate metal between adjacent nanoribbons. Such a thickness may facilitate further processing operations, such as back-side processing operations, as described elsewhere herein. In some embodiments, a gate electrode has gate metal under the nanoribbon stack with a thickness of one-and-a-half times the thickness of gate metal between adjacent nanoribbons. Such a thickness may be sufficient to facilitate further processing operations, e.g., more tightly controlled operations (such as polishing or other planarizing or recessing processes) than those requiring larger thicknesses.
In some embodiments, the transistor structures are formed after receiving the substrate. In some such embodiments, the gate electrodes are formed over and around stacks of nanoribbons such that the nanoribbons extend through the gate electrodes. In some such embodiments, the forming the gate electrodes includes depositing a gate metal (e.g., on a substrate surface) to a first thickness between a surface of the gate electrodes and the lowest of the nanoribbons, nearest to the surface, and to a second thickness between the lowest of the nanoribbons and a next-lowest of the nanoribbons (e.g., next-nearest to the surface), and the first thickness is greater than one-and-a-half times the second thickness. In some embodiments, the first thickness is greater than two or three times the second thickness. The gate electrode surface under the nanoribbon stack may be at (e.g., interface with) the substrate surface that the gate metal is deposited on. The thickness of the gate metal between the surface and the nanoribbon may be set by any suitable means. In some embodiments, the dimension is set by a sacrificial material under the nanoribbon stack whose thickness (before removal of the sacrificial material) is the eventual thickness (once the sacrificial material is removed) of the gate metal under the stack. In some such embodiments, this same sacrificial material is utilized to set the pitch between adjacent nanoribbons and so the thickness of gate metal between adjacent nanoribbons.
The interconnect network may be or include one or more metallization layers. As used herein, the term “metallization layer” describes layers with interconnections or wires that provide electrical routing, generally formed of metal or other electrically conductive material. Adjacent metallization layers may be formed of different materials and by different methods. Adjacent metallization layers are interconnected by vias that may be characterized as part of the metallization layers or between the metallization layers. In some embodiments, front-side metallization layers are formed over and immediately adjacent transistor structures. Front-side metallization layers may include M0 (metal 0), V0 (via 0), M1, M2/V1, M3/V2, M4/V3, and M4-M12, or any number of metallization layers such as eight or more metallization layers. Metallization layers are embedded within dielectric materials, for example, with interconnected metal lines and vias extending through dielectric material.
Metallization layers may be formed by any suitable means and may include any suitable materials. In many embodiments, metallization layers are in interconnect structures having one or more of copper (Cu), tungsten (W), ruthenium (Ru), molybdenum (Mo), gold (Au), tantalum (Ta), cobalt (Co), aluminum (Al), and nickel (Ni), including in alloys. Metallization layers may include any of these or other metals. In some embodiments, metallization layers include nitrides of metals, e.g., tantalum and titanium (Ti). Metallization layers may include other electrically conductive materials, including non-metals. Metallization layers may be built up in a back-end-of-line (BEOL) process. Although metallization layers may be built up in a BEOL process in some exemplary embodiments, other means of forming metallization layers may be utilized.
The substrate may include any suitable material or materials. Any suitable semiconductor or other material can be used. The substrate may be any suitable substrate, such as a wafer, die, etc. The substrate may include a semiconductor material that transistors can be formed out of and on, including a crystalline material, such as monocrystalline or polycrystalline silicon (Si), germanium (Ge), silicon germanium (SiGe), a III—V alloy material (e.g., gallium arsenide (GaAs)), a silicon carbide (SiC), a sapphire (Al2O3), or any combination thereof. In some embodiments, the substrate includes crystalline silicon and subsequent components are also silicon. The substrate may be a silicon-on-insulator (SOI) substrate. One or more fins, nanoribbons, etc., of semiconductor material may be included in or on the substrate. The fin or fins may be of the same material as the substrate or formed, e.g., deposited, on the substrate. The substrate may also include semiconductor materials, metals, dielectrics, dopants, and other materials commonly found in IC substrates. In many embodiments, the received substrate includes metallization layers in an interconnect structure on one side (e.g., a front side), coupled to transistor structures, and a thickness of crystalline material (such as a semiconductor material) under the transistor structures (e.g., on a back side).
Metallization layer 211 is over and coupled to transistor structures 220. For example, metallization layer 211 is over and coupled to some of drain and source regions 222, 223. Some of drain and source regions 222, 223 are not coupled to layer 211, but will be coupled to an interconnect layer and network opposite layer 211, e.g., a back-side interconnect layer and network. Metallization layer 211 is part of an interconnect or metallization network 213 over transistor structures 220, e.g., a front-side interconnect network 213. Metallization layers 211 and network 213 may be substantially as described at operation 101 of
Transistor structures 220 may be field-effect transistors (FETs) having channel regions 226 of any suitable structure coupling drain and source regions 222, 223, as shown in view 203. In some embodiments, as shown in
Channel regions 226 may be of any suitable material and composition for a channel of a transistor. In some examples, channel regions 226 are substantially silicon. In other embodiments, channel regions 226 include germanium (e.g., Si1-XGeX, Ge1-XSnX, or substantially pure Ge). In some embodiments, channel regions 226 include a transition metal and a chalcogen. The transition metal may be any transition metal such as any element of groups 4 through 11, the group 3 elements scandium and yttrium, and the inner transition metals (e.g., f-block lanthanide and actinide series). Notable transition metals are molybdenum and tungsten. The chalcogen may be sulfur, selenium, or tellurium. In still other embodiments, channel region 226 includes one or more metals and oxygen (i.e., metal oxide semiconductor), such as, but not limited to, indium, gallium zinc oxide (IGZO).
Channel regions 226 are advantageously crystalline. Although the crystalline semiconductor includes polycrystalline thin film material, channel regions 226 may be substantially monocrystalline. In some embodiments where channel region 226 is substantially pure silicon, the crystallinity of channel region 226 is cubic with a top surface having crystallographic orientation of (100), (111), or (110), for example. Other crystallographic orientations are also possible. Channel regions 226 may also be polycrystalline or amorphous, for example in certain metal chalcogen and/or metal oxide embodiments.
As illustrated in views 202, 203, transistor structure 220 includes gate electrode 224 adjacent channel region 226 and between drain and source regions 222, 223 as part of a gate structure. The gate structure includes at least gate electrode 224 and a gate dielectric (not shown) over channel region 226. Gate electrode 224 may include one or more gate metals, such as a liner metal and a bulk metal enclose by the liner metal. A gate metal liner may include multiple layers of liner metal, and a bulk metal may also include multiple metals. Gate metal(s) may be chosen due to a metal workfunction, which may have an effect on a transistor voltage threshold VTH. Gate electrode 224 may include any of the metals previously described, e.g., for metallization layers 211 (such as tantalum, titanium, tungsten, etc.), and/or other metals (e.g., for workfunction considerations).
A gate contact or via 214 may connect and couple gate electrode 224 to layer 211. Contacts or vias (not shown) may couple a given gate electrode 224 to upper layer 211 but just in front of or behind the viewing plane of, e.g., view 203. Other gate electrodes 224 may be coupled to a metallization layer opposite metallization layer 211. Gate contact or via 214 may include any of the metals previously described, e.g., for metallization layers 211, such as tungsten, titanium, molybdenum, etc.
A gate structure includes a gate dielectric (not shown) between channel region 226 and a gate metal of gate electrode 224, e.g., to provide electrical insulation between channel region 226 and gate electrode 224 and to electrostatically control of transistor structure 220. For example, a gate dielectric between channel region 226 and gate electrode 224 might be shown as around nanoribbons 221 in view 202 and above and below nanoribbons 221 in view 203. A gate dielectric may have more than one layer and may be of any suitable material(s). The one or more layers of gate dielectric may include a silicon oxide (such as SiO2), a silicon oxynitride, etc. Advantageously, the gate dielectric includes a high-permittivity (“high-K”) dielectric, which may improve transconductance. For example, a high-K dielectric may result in increased conductance of transistor structure 220 (through channel region 226) for a given gate bias.
An upper gate layer 234 is on (e.g., in contact with) gate electrode 224, as shown in views 202, 203. Gate layer 234 is an insulator structure over gate electrode 224, between gate electrode 224 and upper metallization layer 211. Gate layer 234 is advantageously a low-K dielectric structure or layer, e.g., to minimize capacitances between electrode 224 and adjacent conductors, such as metallization layers 211. Gate layer 234 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). Gate layer 234 advantageously has an etch selectivity with adjacent dielectric structures, such as dielectric structure 235 adjacent and between transistor structures 220 (as shown in views 201, 202). In many embodiments, gate layer 234 includes silicon and nitrogen.
Drain and source regions 222, 223 are electrically and physically coupled to opposite ends of channel regions 226. Drain and source regions 222, 223 are impurity doped regions, e.g., regions of semiconductor material doped with one or more electrically active impurities and having increased charge-carrier availabilities and associated conductivities. Drain and source regions 222, 223 may be doped with an opposite type (e.g., n- or p-type) or of similar type to channel region 226. Drain and source regions 222, 223 may include a predominant semiconductor material, and one or more n-dopants (such as phosphorus, arsenic, or antimony) or p-type impurities (such as boron or aluminum). Other dopant materials may be used. Any suitable means of formation may be used. Regions 222, 223 may be epitaxially grown semiconductor regions, for example, of a Group IV semiconductor material (e.g., Si, Ge, SiGe, GeSn alloy). Other semiconductor materials may be employed. Regions 222, 223 are substantially crystalline. Drain and source regions 222, 223 may be polycrystalline or substantially monocrystalline, e.g., having long-range order at least adjacent ends of channel regions 226 and merging or joining into a unitary body with few grain boundaries.
In many embodiments, transistor structures 220 are physically symmetrical about channel regions 226 and gate electrode 224, and identifiers drain and source regions 222, 223 may be reversed interchangeably in many contexts. However, the classification of drain and source regions 222, 223 may be by the electrical relationships of transistor structure 220 and regions 222, 223 to other components in a given circuit (e.g., and the consequent direction of current flow through structure 220 and regions 222, 223). In some embodiments, at least some drain regions 222 are coupled to an upper metallization layer 211, and at least some source regions 223 are coupled to a lower metallization layer, opposite an upper metallization layer 211.
Drain and source regions 222, 223 may be separated from gate electrodes 224 by gate spacer layers 225 between gate electrode 224 and regions 222, 223. In many embodiments, gate spacer layers 225 are in contact with gate electrode 224 and regions 222, 223. Gate spacer layers 225 extend above the tops of gate electrode 224 and are in contact with upper gate layers 234, as shown in view 203. Gate spacer layers 225 are layers of insulator material, advantageously of low-K dielectric material, e.g., to minimize capacitances between electrode 224 and adjacent conductors, such as region 222, 223. Gate spacer layer 225 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). Gate spacer layer 225 advantageously has an etch selectivity with adjacent dielectric structures, such as layer 234, dielectric structure 235, etc. In many embodiments, gate spacer layer 225 includes silicon, oxygen, carbon, and nitrogen.
Gate spacer layers 225 are also between upper gate layers 234 and dielectric structures 232, which are over drain and source regions 222, 223. Dielectric structures 232 may be similar to gate layers 234, but as insulator structures 232 over regions 222, 223 rather than gate electrode 224. Insulator structures 232 are between drain and source regions 222, 223 and upper metallization layer 211. Structure 232 is advantageously a low-K dielectric structure or layer, e.g., to minimize capacitances between regions 222, 223 and adjacent conductors, such as metallization layers 211. Dielectric structure 232 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). Dielectric structure 232 advantageously has an etch selectivity with adjacent dielectric structures, such as layers 225, 234. In some embodiments, insulator structures 232 have a same composition, and are continuous with, dielectric structure 235 adjacent and between transistor structures 220, as shown in view 201.
Dielectric structures 235 are between transistor structures 220, for example, between gate electrodes 224 and between drain and source regions 222, 223. Dielectric structures 235 isolate adjacent transistor structures 220 and advantageously include a low-K dielectric material. Dielectric structures 235 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). In many embodiments, dielectric structures 235 include silicon and oxygen.
Some drain and source regions 222, 223 are coupled to metallization layer 211 by vias or contacts 231 on and over regions 222, 223. Drain and source regions 222, 223 not contacted by vias or contacts 231 may be coupled to a metallization layer opposite metallization layer 211. Contacts 231 are through dielectric structures 232 or in place of dielectric structures 232 over regions 222, 223. Contacts 231 are metal structures that couple transistor structure 220 to interconnect layers 211. In some embodiments, additional metallization structures (not shown) couple contacts 231 to layer 211. For example, drain and source contact vias may couple with contacts 231 and layer 211 in a plane behind or in front of the plane of view 203. In some embodiments, contacts 231 directly contact layer 211, e.g., much like via 214 couples gate electrode 224 to interconnect layer 211. In some embodiments, one or more additional metallization structures (not shown) are between contact 231 and layer 211, and the structure(s) couple contact 231 to layer 211. Drain and source contacts 231 may include any of the metals previously described, e.g., for metallization layers 211, such as tungsten, titanium, molybdenum, etc.
Substrate 299 may be much as described of the substrate at operation 101 of
Dielectric structures 285 are under regions 222, 223, e.g., between crystalline base material in both the x- and y-directions. Dielectric structures 285 are isolation structures on regions 222, 223 and may be of a fill material, e.g., filling an opening formed when cutting a semiconductor fin into separate channel regions 226. Dielectric structures 285 may be of any suitable material. In some embodiments, structures 285 include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). In some embodiments, dielectric structures 285 have a same or similar composition as gate spacer layer 225. In some embodiments, structures 285 include silicon, oxygen, carbon, and nitrogen.
Isolation structures 295 are between adjacent dielectric structures 285 and between adjacent subfins (under gate electrodes 224). Isolation structures 295 may be shallow-trench isolation (STI) structures 295 and may have a composition similar to dielectric materials 215 or structures 235. Isolation structures 295 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). In many embodiments, isolation structures 295 include silicon and oxygen.
Expanded view 205 shares the viewing plane of view 203 and provides more detail about the pitches of nanoribbons 221 and related metal thicknesses of gate electrode 224. A lowest surface 228 of gate electrode 224 is under nanoribbons 221. The lowest surface 228 of gate electrode 224 is furthest from front-side layers 211 and nearest a back-side of substrate 299. In the exemplary embodiment of
Similar relationships may be defined more directly by the metal thicknesses T1, T2 of gate electrode 224. In some embodiments, metal thickness T1 between lowest surface 228 and the lowest of the nanoribbons 221A is greater than 1.5 times thickness T2 between nanoribbons 221A, 221B. In some embodiments, metal thickness T1 between lowest surface 228 and the lowest of the nanoribbons 221A is greater than two times thickness T2 between nanoribbons 221A, 221B. For example, thickness T2 between nanoribbons 221A, 221B may be about 8 nm, and thickness T1 between lowest surface 228 and the lowest of the nanoribbons 221A may be about 17 nm.
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In some embodiments, the gate electrode is received or formed with an unconventionally thick bottom metal under the channel region, for example, to facilitate the back-side recessing to the gate electrode bottom. Revealing a back side of the gate electrodes on a back side of the substrate exposes the bottom surface of the gate electrode (under the channel region, but now facing up from the inverted substrate). The recessing of the substrate and revealing of the gate electrodes may remove some thickness of the gate meal, but the revealing retains a thickness of the gate electrode between the exposed surface and the channel region (e.g., a nearest of the nanoribbons). The retained thickness is less than or equal to the initial (received or formed) thickness. A well-controlled revealing operation (such as a CMP) may not require so thick a bottom gate metal and may remove a smaller thickness of gate metal from the gate electrode bottom.
Besides the inverted orientation, views 301, 302, 303 show similar views of device 200. Notably, the crystalline base material and structures 285, 295 have been removed from the back side of substrate 299. Plan view 304 illustrates the back side of substrate 299 and shows the array of gate electrodes 224 between drain and source regions 222, 223. Gate spacer layers 225 are between gate electrodes 224 and regions 222, 223. Dielectric structure 235 extends in the y-direction between coupled electrodes 224 and regions 222, 223.
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First and second block co-polymer sacrificial materials may be deployed as tail or functional groups connected to the first and second groups, respectively, of self-assembled monolayers. Example block co-polymers are polystyrene and polymethylmethacrylate, but any suitable sacrificial materials may be utilized. The directed self-assembly may form long-range ordered structures precisely aligned with either the gate electrodes (e.g., the first rows of first sacrificial materials) or the drain and source regions (e.g., the second rows of second sacrificial materials). The ordered structures of sacrificial material bridge the dielectric material(s) separating like structures to form alternating rows of sacrificial material. The self-alignment enabled by the organic monolayers obviates any need for patterning the sacrificial materials and is advantageously much more precise than lithographic patterning. Misalignment of around 5 nm between structures over and under gate electrodes or drain and source regions can be expected just due to typical lithographic patterning. In many embodiments, the sacrificial materials (and subsequent replacement structures) self-assembled on a back side are substantially vertically aligned with front-side structures. Used herein, the term “substantially vertically aligned” denotes an alignment (e.g., of sidewalls) within 5 nm, i.e., having a misalignment of less than 5 nm. More precise alignments can be expected with directed self-assembly of monolayers on the gate electrode array. In some embodiments, the sacrificial materials (and subsequent replacement structures) self-assembled on a back side are precisely vertically aligned with front-side structures. Used herein, the term “precisely vertically aligned” denotes an alignment (e.g., of sidewalls) within 2 nm, i.e., having a misalignment of less than 2 nm. Otherwise, with patterning a back side, misalignments of around 15 or 20 nm can be expected in some dimensions due to wafer distortion (e.g., along certain axes relative to a crystallographic orientation).
The self-alignment enabled by the organic monolayers precisely aligns (e.g., nearly perfectly aligns) the sacrificial materials (and so subsequent replacement structures) with the respective gate electrodes or drain and source regions.
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Methods 100 continue at operation 105 with forming gate insulators by replacing the first sacrificial material with a first dielectric material. The first dielectric material may be any suitable dielectric material and may be deposited by any suitable means. The first dielectric material may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). The first dielectric material (and so back-side gate insulators) will advantageously have an etch selectivity with subsequent dielectric structures, which may include oxygen. In many embodiments, the first dielectric material of the back-side gate insulators includes silicon and nitrogen. In some embodiments, the first dielectric material is deposited conformally over the gate electrodes and the second sacrificial material. In some such embodiments, the first dielectric material is deposited by an atomic layer deposition (ALD). In some embodiments, the first dielectric material is deposited above a top surface of the second sacrificial material and is subsequently recessed back down. In some such embodiments, a polish (e.g., CMP) or etch is used to recess back the first dielectric material down to the level of, and to expose, the second sacrificial material.
Back-side gate insulators 524 are on (e.g., in contact with) gate electrodes 224, as shown in views 502, 503. Insulator 524 is an insulator structure over gate electrode 224 (while substrate 299 is inverted), between gate electrode 224 and the back side of substrate 299. Back-side gate insulator 524 is advantageously a low-K dielectric structure or layer, e.g., to minimize capacitances between electrode 224 and adjacent conductors, such as subsequently formed metallization layers. Insulator 524 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). Back-side gate insulator 524 advantageously has an etch selectivity with adjacent dielectric structures, such as dielectric structure 235 adjacent and between transistor structures 220 (as shown in views 201, 202). In many embodiments, insulator 524 includes silicon and nitrogen.
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Spacer layer 624 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). Spacer layer 624 advantageously has an etch selectivity with adjacent dielectric structures, such as layer 234, dielectric structure 235, etc. In many embodiments, spacer layer 624 includes silicon, oxygen, carbon, and nitrogen.
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Back-side drain and source dielectric structures 722 may be similar to front-side dielectric structures 232. As shown in views 701, 703, insulator structures 722 are on drain and source regions 222, 223 and opposite upper metallization layer 211 (which are on a bottom, front-side of inverted substrate 299). Structure 722 is advantageously a low-K dielectric structure or layer, e.g., to minimize capacitances between regions 222, 223 and adjacent conductors, such as subsequently formed metallization layers. Dielectric structure 722 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). Dielectric structure 722 advantageously has an etch selectivity with adjacent dielectric structures, such as layers 225, 624 and insulators 524. In some embodiments, insulator structures 722 have a same composition as dielectric structure 232.
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The back-side contacts to at least some of the gate electrodes and the drain and source regions may be formed by any suitable means, for example, by anisotropic dry etching and subsequent deposition of a conductive material, such as a metal. The dry etch may be by, e.g., a reactive ion etch (RIE), such as a deep RIE (DRIE). The deposition may be by, e.g., a PVD or chemical vapor deposition (CVD). In at least some embodiments, a second interconnect or metallization network is formed on the back side, and the back-side interconnect or metallization network is coupled to the back-side contacts and to the first metallization network on the front side. Back-side interconnect or metallization layers may be formed by patterning, etching, and metallizing similar to that used for forming back-side contacts or front-side interconnect or metallization layers. Subsequent layers of dielectric materials may be built up iteratively, one over another, after a previous, lower interconnect layer is patterned and metallized. Back-side contacts and interconnect or metallization layers may include the same or other materials (e.g., metals and dielectrics) described for front-side interconnect or metallization layers, for example, at
In some embodiments, additional dielectric layer 915 is deployed over insulators 524, dielectric structures 722, contacts 822, etc., as shown in views 901, 902, 903. In some such embodiments, layer 915 is an inter-layer dielectric (ILD) layer 915 deployed to provide, for example, additional electrical isolation, improved reliability, etch selectivity, etc. ILD layer 915 may have the same or different composition as other dielectric structures in device 200, such as material 215, structure 235, insulators 524, structures 722, etc. Layer 915 may include silicon (for example, in an oxide, nitride, carbide, etc., of silicon). In many embodiments, ILD layer 915 includes silicon and oxygen.
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Device 200 includes front- and back-side metallization layers 211, 1012 and transistor structure 220. Transistor structure 220 includes a stack of nanoribbons 221 between and coupling drain and source regions 222, 223, and gate electrode 224 adjacent nanoribbons 221. Front-side metallization layer 211 is over and coupled to drain region 222. Source region 223 is over and coupled to back-side metallization layer 1012. Note that, although not separately labeled, the ILD of
In some embodiments, gate electrodes have a first vertical pitch P1 greater a second vertical pitch P2, and a first metal thickness T1 greater than thickness T2, much as described at
Device 200 includes front-side gate layer 234 on gate electrode 224 and between front-side metallization layer 211 (and network 213) and gate electrode 224. Device 200 includes back-side gate insulators 524 on gate electrode 224 and between gate electrode 224 and the back-side metallization layer (and network 1014, over and coupled to back-side contact 822 on source region 223). In some embodiments, a first sidewall SW1 of front-side gate layer 234 is substantially vertically aligned over a second sidewall SW2 of back-side gate insulators 524, and a third sidewall SW3 of the gate layer 234 is substantially vertically aligned over a fourth sidewall SW4 of back-side gate insulators 524. In some such embodiments, first sidewall SW1 is precisely vertically aligned over second sidewall SW2, and third sidewall SW3 is precisely vertically aligned over fourth sidewall SW4.
Back-side drain dielectric structure 722 is on drain region 222 and between the back-side metallization layer 1012 (and network 1014) and drain region 222. Gate spacer layer 225 is between gate electrode 224 and drain region 222 and in contact with gate electrode 224, gate layer 234, and drain region 222. Back-side spacer layer 624 is in contact with back-side gate insulator 524, back-side drain dielectric structure 722, and front-side gate spacer layer 225. In some embodiments, front- and back-side spacer layers 225, 624 have a same composition as formed. However, due to exposure to extra processing received by the first-formed layers 225, a chemical or physical interface may be observed where layers 225, 624 adjoin. Such an interface may show, e.g., a stoichiometric difference between the layers. Other interfaces may be observed.
In some embodiments, a fifth sidewall SW5 of back-side drain dielectric structure 722 is substantially vertically aligned with a sixth sidewall SW6 of front-side gate spacer layer 225 between drain region 222 and front-side metallization layer 211, and a seventh sidewall SW7 of back-side drain dielectric structure 722 is substantially vertically aligned over an eighth sidewall SW8 of a second front-side gate spacer layer 225 where drain region 222 is on and between the first and second front-side gate spacer layer 225. In some such embodiments, fifth sidewall SW5 is precisely vertically aligned over sixth sidewall SW6, and seventh sidewall SW7 is precisely vertically aligned over eighth sidewall SW8.
In
Interconnectivity of transistor structures 220 (and other transistors, etc.), signal routing to and from memory arrays, etc., power delivery, etc., and routing to an outside device (not shown), is provided by front-side metallization layers 211 and network 213, back-side metallization layers 1012 and network 1014, and package-level interconnects 1106. In the example of
In the illustrated example, front-side metallization layers 211 include M0, V0, M1, M2/V1, M3/V2, M4/V3, and M4-M12. However, front-side metallization layers 211 may include any number of metallization layers such as eight or more metallization layers. Similarly, back-side metallization layers 1012 include BM0, BM1, BM2, and BM3. However, back-side metallization layers 1012 may include any number of metallization layers such as two to five metallization layers. Front-side metallization layers 211 and back-side metallization layers 1012 are embedded within dielectric materials 1153, 1154. Furthermore, optional metal-insulator-metal (MIM) devices such as diode devices may be provided within back-side metallization layers 1012. Other devices such as capacitive memory devices may be provided within front-side metallization layers 211 and/or back-side metallization layers 1012.
Also as shown, server machine 1206 includes a battery and/or power supply 1215 to provide power to devices 1250, and to provide, in some embodiments, power delivery functions such as power regulation. Devices 1250 may be deployed as part of a package-level integrated system 1210. Integrated system 1210 is further illustrated in the expanded view 1220. In the exemplary embodiment, devices 1250 (labeled “Memory/Processor”) includes at least one memory chip (e.g., random-access memory (RAM)), and/or at least one processor chip (e.g., a microprocessor, a multi-core microprocessor, or graphics processor, or the like) having the characteristics discussed herein. In an embodiment, device 1250 is a microprocessor including a static RAM (SRAM) cache memory. As shown, device 1250 may be an IC device having back-side contacts through self-aligned dielectric layers, as discussed herein. Device 1250 may be further coupled to (e.g., communicatively coupled to) a board, an interposer, or a substrate 1199 along with, one or more of a power management IC (PMIC) 1230, RF (wireless) IC (RFIC) 1225 including a wideband RF (wireless) transmitter and/or receiver (TX/RX) (e.g., including a digital baseband and an analog front end module further includes a power amplifier on a transmit path and a low noise amplifier on a receive path), and a controller 1235 thereof. In some embodiments, RFIC 1225, PMIC 1230, controller 1235, and device 1250 include having back-side contacts through self-aligned dielectric layers.
Computing device 1300 may include a processing device 1301 (e.g., one or more processing devices). As used herein, the term “processing device” or “processor” indicates a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory. Processing device 1301 may include a memory 1321, a communication device 1322, a refrigeration device 1323, a battery/power regulation device 1324, logic 1325, interconnects 1326 (i.e., optionally including redistribution layers (RDL) or metal-insulator-metal (MIM) devices), a heat regulation device 1327, and a hardware security device 1328.
Processing device 1301 may include one or more digital signal processors (DSPs), application-specific ICs (ASICs), central processing units (CPUs), graphics processing units (GPUs), cryptoprocessors (specialized processors that execute cryptographic algorithms within hardware), server processors, or any other suitable processing devices.
Computing device 1300 may include a memory 1302, which may itself include one or more memory devices such as volatile memory (e.g., dynamic random-access memory (DRAM)), nonvolatile memory (e.g., read-only memory (ROM)), flash memory, solid state memory, and/or a hard drive. In some embodiments, memory 1302 includes memory that shares a die with processing device 1301. This memory may be used as cache memory and may include embedded dynamic random-access memory (eDRAM) or spin transfer torque magnetic random-access memory (STT-MRAM).
Computing device 1300 may include a heat regulation/refrigeration device 1306. Heat regulation/refrigeration device 1306 may maintain processing device 1301 (and/or other components of computing device 1300) at a predetermined low temperature during operation.
In some embodiments, computing device 1300 may include a communication chip 1307 (e.g., one or more communication chips). For example, the communication chip 1307 may be configured for managing wireless communications for the transfer of data to and from computing device 1300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a nonsolid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not.
Communication chip 1307 may implement any of a number of wireless standards or protocols, including but not limited to Institute for Electrical and Electronic Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 Amendment), Long-Term Evolution (LTE) project along with any amendments, updates, and/or revisions (e.g., advanced LTE project, ultramobile broadband (UMB) project (also referred to as “3GPP2”), etc.). IEEE 802.16 compatible Broadband Wireless Access (BWA) networks are generally referred to as WiMAX networks, an acronym that stands for Worldwide Interoperability for Microwave Access, which is a certification mark for products that pass conformity and interoperability tests for the IEEE 802.16 standards. Communication chip 1307 may operate in accordance with a Global System for Mobile Communication (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. Communication chip 1307 may operate in accordance with Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication chip 1307 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution-Data Optimized (EV-DO), and derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. Communication chip 1307 may operate in accordance with other wireless protocols in other embodiments. Computing device 1300 may include an antenna 1313 to facilitate wireless communications and/or to receive other wireless communications (such as AM or FM radio transmissions).
In some embodiments, communication chip 1307 may manage wired communications, such as electrical, optical, or any other suitable communication protocols (e.g., the Ethernet). As noted above, communication chip 1307 may include multiple communication chips. For instance, a first communication chip 1307 may be dedicated to shorter-range wireless communications such as Wi-Fi or Bluetooth, and a second communication chip 1307 may be dedicated to longer-range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, a first communication chip 1307 may be dedicated to wireless communications, and a second communication chip 1307 may be dedicated to wired communications.
Computing device 1300 may include battery/power circuitry 1308. Battery/power circuitry 1308 may include one or more energy storage devices (e.g., batteries or capacitors) and/or circuitry for coupling components of computing device 1300 to an energy source separate from computing device 1300 (e.g., AC line power).
Computing device 1300 may include a display device 1303 (or corresponding interface circuitry, as discussed above). Display device 1303 may include any visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display, for example.
Computing device 1300 may include an audio output device 1304 (or corresponding interface circuitry, as discussed above). Audio output device 1304 may include any device that generates an audible indicator, such as speakers, headsets, or earbuds, for example.
Computing device 1300 may include an audio input device 1310 (or corresponding interface circuitry, as discussed above). Audio input device 1310 may include any device that generates a signal representative of a sound, such as microphones, microphone arrays, or digital instruments (e.g., instruments having a musical instrument digital interface (MIDI) output).
Computing device 1300 may include a GPS device 1309 (or corresponding interface circuitry, as discussed above). GPS device 1309 may be in communication with a satellite-based system and may receive a location of computing device 1300, as known in the art.
Computing device 1300 may include other output device 1305 (or corresponding interface circuitry, as discussed above). Examples of the other output device 1305 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.
Computing device 1300 may include other input device 1311 (or corresponding interface circuitry, as discussed above). Examples of the other input device 1311 may include an accelerometer, a gyroscope, a compass, an image capture device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a bar code reader, a Quick Response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.
Computing device 1300 may include a security interface device 1312. Security interface device 1312 may include any device that provides security measures for computing device 1300 such as intrusion detection, biometric validation, security encode or decode, access list management, malware detection, or spyware detection.
Computing device 1300, or a subset of its components, may have any appropriate form factor, such as a hand-held or mobile computing device (e.g., a cell phone, a smart phone, a mobile internet device, a music player, a tablet computer, a laptop computer, a netbook computer, a personal digital assistant (PDA), an ultramobile personal computer, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device.
The subject matter of the present description is not necessarily limited to specific applications illustrated in
The following examples pertain to further embodiments, and specifics in the examples may be used anywhere in one or more embodiments.
In one or more first embodiments, an apparatus includes first and second metallization layers, and a transistor structure including a stack of nanoribbons between and coupling first and second impurity doped regions, and a gate electrode adjacent the nanoribbons, wherein the first metallization layer is over and coupled to the first impurity doped region, the second impurity doped region is over and coupled to the second metallization layer, and a first vertical pitch between a lowest of the nanoribbons and a lowest surface of the gate electrode is greater than one-and-a-half times a second vertical pitch between the lowest of the nanoribbons and a next lowest of the nanoribbons.
In one or more second embodiments, further to the first embodiments, the first vertical pitch is greater than twice the second vertical pitch.
In one or more third embodiments, further to the first or second embodiments, the first vertical pitch is greater than 20 nm.
In one or more fourth embodiments, further to the first through third embodiments, the apparatus also includes a first dielectric structure on the gate electrode and between the first metallization layer and the gate electrode, and a second dielectric structure on the gate electrode and between the gate electrode and the second metallization layer, wherein a first sidewall of the first dielectric structure is substantially vertically aligned over a second sidewall of the second dielectric structure, and a third sidewall of the first dielectric structure is substantially vertically aligned over a fourth sidewall of the second dielectric structure.
In one or more fifth embodiments, further to the first through fourth embodiments, the first sidewall is precisely vertically aligned over the second sidewall, and the third sidewall is precisely vertically aligned over the fourth sidewall.
In one or more sixth embodiments, further to the first through fifth embodiments, the apparatus also includes a third dielectric structure on the first impurity doped region and between the second metallization layer and the first impurity doped region, a first insulator layer between the gate electrode and the first impurity doped region and in contact with the gate electrode, the first dielectric structure, and the first impurity doped region, and a second insulator layer in contact with the second and third dielectric structures and the first insulator layer.
In one or more seventh embodiments, further to the first through sixth embodiments, a fifth sidewall of the third dielectric structure is substantially vertically aligned with a sixth sidewall of the first insulator layer between the first impurity doped region and the first metallization layer, and a seventh sidewall of the third dielectric structure is substantially vertically aligned over an eighth sidewall of a third insulator layer, the first impurity doped region on and between the first and third insulator layers.
In one or more eighth embodiments, further to the first through seventh embodiments, the fifth sidewall is precisely vertically aligned over the sixth sidewall, and the seventh sidewall is precisely vertically aligned over the eighth sidewall.
In one or more ninth embodiments, further to the first through eighth embodiments, the second metallization layer is coupled to a substrate and a power supply through the substrate.
In one or more tenth embodiments, an apparatus includes first and second metallization layers, and a transistor structure including a gate electrode between source and drain regions and between and in contact with first and second dielectric structures, the transistor structure between and coupled to the first and second metallization layers, wherein the first and second dielectric structures are between the first and second metallization layers, a third dielectric structure is between the second metallization layer and a first of the source and drain regions, a first insulator layer is between the gate electrode and the first of the source and drain regions and in contact with the gate electrode, the first dielectric structure, and the first of the source and drain regions, and a second insulator layer is in contact with the second and third dielectric structures and the first insulator layer.
In one or more eleventh embodiments, further to the tenth embodiments, the transistor structure includes a stack of nanoribbons between and coupling the source and drain regions, and a first vertical pitch between a lowest of the nanoribbons and a lowest surface of the gate electrode is greater than one-and-a-half times a second vertical pitch between the lowest of the nanoribbons and a next lowest of the nanoribbons.
In one or more twelfth embodiments, further to the tenth or eleventh embodiments, the first vertical pitch is greater than 20 nm.
In one or more thirteenth embodiments, further to the tenth through twelfth embodiments, a first sidewall of the first dielectric structure is substantially vertically aligned over a second sidewall of the second dielectric structure, and a third sidewall of the first dielectric structure is substantially vertically aligned over a fourth sidewall of the second dielectric structure.
In one or more fourteenth embodiments, further to the tenth through thirteenth embodiments, the first sidewall is precisely vertically aligned over the second sidewall, and the third sidewall is precisely vertically aligned over the fourth sidewall.
In one or more fifteenth embodiments, a method includes forming alternating first and second rows of first and second sacrificial materials on a first side of a substrate, wherein the substrate includes a plurality of transistor structures coupled to a metallization network on a second side opposite the first side, the plurality of transistor structures includes a plurality of gate electrodes between a plurality of source and drain regions, and the first rows are in contact with the plurality of gate electrodes, forming a plurality of gate insulators by replacing the first sacrificial material with a first dielectric material, depositing second dielectric layers on and between the gate insulators, forming a plurality of source and drain insulators by depositing a third dielectric material over the source and drain regions and between the second dielectric layers, and forming a plurality of contacts on the first side to at least some of the gate electrodes and the source and drain regions and through the gate insulators and the source and drain insulators.
In one or more sixteenth embodiments, further to the fifteenth embodiments, the method also includes forming the gate electrodes, wherein a first of the transistor structures includes a stack of nanoribbons extending through a first of the gate electrodes, and the forming the gate electrodes includes depositing a metal to a first thickness between a surface of the first of the gate electrodes and a nearest of the nanoribbons to the surface and to a second thickness between the nearest of the nanoribbons and a next nearest of the nanoribbons to the surface, the surface of the first of the gate electrodes is opposite the metallization network and the second side, and the first thickness is greater than one-and-a-half times the second thickness.
In one or more seventeenth embodiments, further to the fifteenth or sixteenth embodiments, the method also includes revealing the gate electrodes on the first side of the substrate, wherein the revealing the gate electrodes exposes the surface and retains a third thickness of the gate electrode between the surface and the nearest of the nanoribbons, and the third thickness is less than or equal to the first thickness.
In one or more eighteenth embodiments, further to the fifteenth through seventeenth embodiments, the first sacrificial material of the first rows and the second sacrificial material of the second rows include self-assembled monolayers of organic molecules, and the forming the alternating first and second rows includes directed self-assembly.
In one or more nineteenth embodiments, further to the fifteenth through eighteenth embodiments, the depositing the second dielectric layers contacts the second dielectric layers to fourth dielectric layers between the gate electrodes and the source and drain regions.
In one or more twentieth embodiments, further to the fifteenth through nineteenth embodiments, the metallization network on the second side of the substrate is a first metallization network, also including forming a second metallization network on the first side, the second metallization network coupled to the plurality of contacts on the first side and to the first metallization network on the second side.
The disclosure can be practiced with modification and alteration, and the scope of the appended claims is not limited to the embodiments so described. For example, the above embodiments may include specific combinations of features. However, the above embodiments are not limiting in this regard and, in various implementations, the above embodiments may include the undertaking only a subset of such features, undertaking a different order of such features, undertaking a different combination of such features, and/or undertaking additional features than those features explicitly listed. The scope of the patent rights should, therefore, be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.
