Disabling poorly testing RFID ICs

Abstract

Manufacturing methods, testing, and RFID integrated circuit wafers that have been so prepared. A function of an integrated circuit can be tested. If the test fails, a control function of the tested circuit is disabled.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of components of an RFID system.

FIG. 2 is a diagram showing components of a passive RFID tag, such as a tag that can be used in the system of FIG. 1.

FIG. 3 is a conceptual diagram for explaining a half-duplex mode of communication between the components of the RFID system of FIG. 1.

FIG. 4 is a block diagram of an implementation of an electrical circuit formed in an IC of the tag of FIG. 2.

FIG. 5 is a flowchart illustrating a testing method according to embodiments.

FIG. 6A is a diagram of a wafer formed with RFID ICs according to a first operation of the flowchart of FIG. 5 according to embodiments.

FIG. 6B is a diagram for visualizing grades from a testing operation of the flowchart of FIG. 5 according to embodiments.

FIG. 6C is a diagram of the wafer of FIG. 6A after the testing operation of FIG. 6B, and where some of the RFID ICs are intact, while others, according to another operation of the flowchart of FIG. 5, have had one of their control functions disabled depending on the result of the testing operation of FIG. 6B.

FIG. 6D is a conceptual diagram illustrating separation of the wafer of FIG. 6C into multiple integrated circuit (IC) chips according to another operation of the flowchart of FIG. 5.

FIG. 7 is a block diagram of one of the chips of FIG. 6D, whose IC has not been disabled.

FIG. 8 is a block diagram of one of the chips of FIG. 6D, whose IC has had one of its control functions disabled.

FIG. 9 is the block diagram of FIG. 4, modified to further show that a modulator can be changed to disable the control function of the IC of FIG. 8.

FIG. 10 is the block diagram of FIG. 4, modified to further show that a demodulator can be changed to disable the control function of the IC of FIG. 8.

FIG. 11 is the block diagram of FIG. 4, modified to further show that the whole circuit can be disabled.

FIG. 12 is the block diagram of FIG. 4, modified to further show that a circuit can be logically killed to disable the control function of the IC of FIG. 8.

FIG. 13 is a diagram showing an arrangement for sorting the IC chips generated at FIG. 6D.

Claims

1. A method comprising: forming a plurality of RFID integrated circuits on a wafer;performing a first test on a first operative function of one of the RFID circuits; andif the first operative function fails the first test, disabling at least a control function of the tested circuit; andthen separating from a remainder of the wafer a chip that includes the tested circuit.

2. The method of claim 1, further comprising: if the first operative function passes the first test, not disabling the tested circuit.

3. The method of claim 1, in which the wafer is physically probed to test the first operative function.

4. The method of claim 1, in which the tested circuit includes an on-chip antenna, andRF energy is directed at the antenna to test the first operative function.

5. The method of claim 1, in which the first test results in a grade, andthe first operative function fails the first test if the grade is less than a threshold.

6. The method of claim 1, in which the first test results in a grade, andthe first operative function fails the first test if the grade is more than a threshold.

7. The method of claim 1, further comprising: performing a second test on a second operative function of the tested circuit; andin which the control function is disabled if at least one of the first and the second operative functions fails its respective test.

8. The method of claim 1, in which the wafer is physically probed to disable the control function.

9. The method of claim 1, in which the tested circuit includes an on-chip antenna, andRF energy is directed at the antenna to disable the control function.

10. The method of claim 1, in which the tested circuit includes a component, anddisabling includes changing the component.

11. The method of claim 10, in which the component is a modulator.

12. The method of claim 10, in which the component is a demodulator.

13. The method of claim 10, in which the component includes a fuse that is normally closed, andchanging the component includes cutting the fuse.

14. The method of claim 10, in which the component includes an anti-fuse that is normally open, andchanging the component includes shorting the anti-fuse.

15. The method of claim 10, in which the component includes a power bus, andchanging the component includes opening the power bus.

16. The method of claim 1, in which if the first operative function fails the first test, the tested circuit is wholly disabled.

17. The method of claim 1, in which the tested circuit includes a mechanism for becoming logically killed, anddisabling is performed by actuating the mechanism to logically kill the tested circuit.

18. The method of claim 17, in which the wafer is physically probed to actuate the mechanism.

19. The method of claim 17, in which the tested circuit includes an on-chip antenna, andRF energy is directed at the antenna to actuate the mechanism.

20. The method of claim 17, in which if the tested circuit were eventually completed as an RFID tag, the mechanism would be responsive to a wirelessly received KILL command for logically killing the tag.

21. A wafer comprising formed thereon a plurality of similar integrated RFID circuits, a first operative function of the RFID circuits having been tested by a first test, and in which a first subgroup of the circuits, whose first operative function has passed the first test, have not had one of their control functions disabled, anda second subgroup of the circuits, whose first operative function has failed the first test, have had one of their control functions disabled.

22. The wafer of claim 21, in which the wafer is a single piece.

23. The wafer of claim 21, which has been further separated into chips, some of which contain respective ones of the integrated RFID circuits.

24. The wafer of claim 21, in which the RFID circuits include a component, andthe RFID circuits of the second subgroup have been disabled by the component having been changed.

25. The wafer of claim 24, in which the component is a modulator.

26. The wafer of claim 24, in which the component is a demodulator.

27. The wafer of claim 24, in which the component includes a fuse that is normally closed, andthe fuse has been changed by being cut.

28. The wafer of claim 24, in which the component includes an anti-fuse that is normally open, andthe anti-fuse has been changed by being shorted.

29. The wafer of claim 24, in which the component includes a power bus.

30. The wafer of claim 21, in which

31. The wafer of claim 21, in which the circuits of the second subgroup have been wholly disabled.

32. The wafer of claim 21, in which the circuits include respective mechanisms for becoming logically killed, andthe circuits of the second subgroup have been disabled by actuating the mechanism to logically kill them.

33. The wafer of claim 32, in which if the circuits of the first subgroup were eventually completed as respective RFID tags, their mechanism would be responsive to a wirelessly received KILL command for logically killing the respective RFID tags.