Patent Grant
12243955
The present invention relates to micro semiconductor devices. More particularly embodiments of the present invention relate to a method of forming an array of micro devices such as light emitting diodes (LEDs) for transfer to a different substrate.
Light emitting diodes (LEDs) based upon gallium nitride (GaN) are expected to be used in future high-efficiency lighting applications, replacing incandescent and fluorescent lighting lamps. Current GaN-based LED devices are prepared by heteroepitaxial growth techniques on foreign substrate materials. A typical wafer level LED device structure may include a lower n-doped GaN layer formed over a sapphire growth substrate, a single quantum well (SQW) or multiple quantum well (MWQ), and an upper p-doped GaN layer.
In one implementation, the wafer level LED device structure is patterned into an array of mesas on the sapphire growth substrate by etching through the upper p-doped GaN layer, quantum well layer, and into the n-doped GaN layer. An upper p-electrode is formed on the top p-doped GaN surfaces of the array of mesas, and an n-electrode is formed on a portion of the n-doped GaN layer which is in contact with the array of mesas. The mesa LED devices remain on the sapphire growth substrate in the final product.
In another implementation, the wafer level LED device structure is transferred from the growth substrate to an acceptor substrate such as silicon, which has the advantage of being more easily diced to form individual chips than a GaN/sapphire composite structure. In this implementation, the wafer level LED device structure is permanently bonded to the acceptor (silicon) substrate with a permanent bonding layer. For example, the p-electrode formed on the p-doped GaN surfaces of the array of mesas can be bonded to the acceptor (silicon) substrate with a permanent bonding layer. The sapphire growth substrate is then removed to expose the inverted wafer level LED device structure, which is then thinned to expose the array of mesas. N-contacts are then made with the exposed n-doped GaN, and p-contacts are made on the silicon surface which is in electrical contact with the p-electrode. The mesa LED devices remain on the acceptor substrate in the final product. The GaN/silicon composite can also be diced to form individual chips.
A micro light emitting diode (LED) and a method of forming an array of micro LEDs for transfer to a receiving substrate are described. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or integrated circuits (ICs), or a substrate with metal redistribution lines. In an embodiment, a micro LED structure includes a micro p-n diode and a metallization layer, with the metallization layer between the micro p-n diode and a bonding layer formed on a substrate. The metallization layer may include one or more layers. For example, the metallization layer may include an electrode layer and a barrier layer between the electrode layer and the bonding layer. The micro p-n diode and metallization layer may each have a top surface, a bottom surface and sidewalls. In an embodiment, the bottom surface of the micro p-n diode is wider than the top surface of the micro p-n diode, and the sidewalls are tapered outwardly from top to bottom. The top surface of the micro p-n diode may also be wider than the bottom surface of the p-n diode, or approximately the same width. In an embodiment, the bottom surface of the micro p-n diode is wider than the top surface of the metallization layer. The bottom surface of the micro p-n diode may also be wider than the top surface of the metallization layer, or approximately the same width as the top surface of the metallization layer.
A conformal dielectric barrier layer may optionally be formed over the micro p-n diode and other exposed surfaces. The conformal dielectric barrier layer may be thinner than the micro p-n diode, metallization layer and optionally the bonding layer so that the conformal dielectric barrier layer forms an outline of the topography it is formed on. In an embodiment, the conformal dielectric barrier layer spans sidewalls of the micro p-n diode, and may cover a quantum well layer in the micro p-n diode. The conformal dielectric barrier layer may also partially span the bottom surface of the micro p-n diode, as well as span sidewalls of the metallization layer. In some embodiments, the conformal dielectric barrier layer also spans sidewalls of a patterned bonding layer. A contact opening may be formed in the conformal dielectric barrier layer exposing the top surface of the micro p-n diode. The contact opening can have a width which is greater than, less than, or approximately the same width as the top surface of the micro p-n diode. In one embodiment, the contact opening has a width which is less than the width of the top surface of the micro p-n diode, and the conformal dielectric barrier layer forms a lip around the edges of the top surface of the micro p-n diode.
In some embodiments the bonding layer may be formed of a material which has a liquidus temperature or melting temperature below approximately 350° C., or more specifically below approximately 200° C. For example, the bonding layer may include indium, tin or a thermoplastic polymer such as polyethylene or polypropylene. The bonding layer may be laterally continuous across the substrate, or may also be formed in laterally separate locations. For example, a laterally separate location of the bonding layer may have a width which is less than or approximately the same width as the bottom surface of the micro p-n diode or metallization layer.
In an embodiment, a micro LED array includes a plurality of locations of a bonding layer on a carrier substrate, and a corresponding plurality of micro LED structures on the plurality of locations of the bonding layer. Each micro LED structure includes a micro p-n diode and a metallization layer with the metallization layer between the micro p-n diode and a respective location of the bonding layer. A conformal dielectric barrier layer can be deposited on the micro LED array on the substrate, with the conformal dielectric barrier layer spanning sidewalls of each micro p-n diode. The conformal dielectric barrier layer may also partially span the bottom surface of each micro p-n diode, and sidewalls of each metallization layer. A plurality of contact openings may be formed in the conformal dielectric barrier layer exposing a top surface of each micro p-n diode in which each contact opening has a width which may be greater than, less than, or approximately the same width as the top surface of each corresponding micro p-n diode.
The plurality of locations of the bonding layer may or may not be laterally separate from one another. In some embodiments, the plurality of locations of the bonding layer are laterally separate and the conformal dielectric barrier layer spans sidewalls of each of the plurality of laterally separate locations of the bonding layer. In some embodiments, the substrate includes a respective plurality of pillars on which the plurality of locations of the bonding layer are formed. For example, each micro p-n diode may include a bottom surface which is either approximately the same width as a top surface of a respective pillar or wider than the top surface of f the respective pillar. The pillars may also have a height which is greater than a respective thickness of the locations of the bonding layer. In an embodiment, the respective height is at least twice the respective thickness.
A micro LED structure and micro LED array may be formed utilizing existing heterogeneous growth technologies. In an embodiment a p-n diode layer and metallization layer are transferred from a growth substrate to a carrier substrate. In accordance with embodiments of the invention, the p-n diode layer and the metallization layer may be patterned prior to or after transfer to the carrier substrate. Transferring the p-n diode layer and the metallization layer to the carrier substrate may include bonding the metallization layer to a bonding layer on the carrier substrate. For example, the bonding layer may have a liquidus temperature or melting temperature below approximately 350° C., or more specifically below 200° C. For example, the bonding layer may be formed of indium or an indium alloy. After patterning the p-n diode layer and the metallization layer to form a plurality of separate micro p-n diodes and a plurality of separate locations of the metallization layer a conformal dielectric barrier layer is formed spanning the sidewalls of the plurality of separate micro p-n diodes. The conformal dielectric barrier layer may form an outline of the topography onto which it is formed, and may be thinner than the micro p-n diodes and the metallization layer. For example, the conformal dielectric barrier layer may be formed by atomic layer deposition (ALD). The conformal dielectric barrier layer may also be formed on a portion of the bottom surface of each separate micro p-n diode.
In an embodiment, the p-n diode layer and a patterned metallization layer including a plurality of separate locations of the metallization layer on the p-n diode layer are transferred from the growth substrate to the carrier substrate. The p-n diode layer may be partially patterned prior to transferring from the growth substrate to the carrier substrate, to form micro mesas separated by trenches in the p-n diode layer. In an embodiment, a plurality of pillars are formed on the carrier substrate prior to transferring the p-n diode layer and patterned metallization layer to the carrier substrate. The bonding layer may be formed over the plurality of pillars on the carrier substrate prior to transferring the p-n diode layer and the patterned metallization layer to the carrier substrate.
In an embodiment, the metallization layer is patterned to form a plurality of separate locations of the metallization layer after transferring the metallization layer and the p-n diode layer from the growth substrate to the carrier substrate. In such an embodiment, the p-n diode layer is patterned to form a plurality of separate micro p-n diodes, followed by patterning the metallization layer. Patterning of the metallization layer may include etching the metallization layer until a maximum width of the plurality of separate locations of the metallization layer are less than a width of the bottom surface of each of the plurality of separate micro p-n diodes. In an embodiment, the bonding layer is patterned after transferring the p-n diode layer and the metallization layer form the growth substrate to the carrier substrate. For example, the bonding layer can be etched until a maximum width of the plurality of separate locations of the bonding layer are less than a width of a bottom surface of each of the plurality of separate micro p-n diodes. A plurality of pillars can also be formed on the carrier substrate prior to transferring the p-n diode layer and the metallization layer from the growth substrate to the carrier substrate. The bonding layer may be formed over the plurality of pillars on the carrier substrate prior to transferring the p-n diode layer and the patterned metallization layer to the carrier substrate.
Once formed, the micro LED structure and micro LED array can be picked up and transferred to a receiving substrate. A transfer head can be positioned over the carrier substrate having an array of micro LED structures disposed thereon, and an operation is performed to create a phase change in the bonding layer for at least one of the micro LED structures. For example, the operation may be heating the bonding layer above a liquidus temperature or melting temperature of the bonding layer, or altering a crystal phase of the bonding layer. The at least one micro LED structure including the micro p-n diode and the metallization layer, and optionally a portion of the bonding layer for the at least one of the micro LED structures may be picked up with a transfer head and placed on a receiving substrate. If a conformal dielectric barrier layer has already been formed, a portion of the conformal dielectric barrier layer may also be picked up with the micro p-n diode and the metallization layer. Alternatively, a conformal dielectric barrier layer can be formed over the micro LED structure, or plurality of micro LED structures, after being placed on the receiving substrate.
In an embodiment, the conformal dielectric barrier layer spans a portion of the bottom surface of the micro p-n diode, spans sidewalls of the metallization layer, and spans across a portion of the bonding layer adjacent the metallization layer. The conformal dielectric barrier layer may be cleaved after contacting the micro LED structure with the transfer head and/or creating the phase change in the bonding layer, which may be prior to picking up the micro p-n diode and the metallization layer with the transfer head. For example, cleaving the conformal dielectric barrier layer may include transferring a pressure from the transfer head to the conformal dielectric barrier layer and/or heating the bonding layer above a liquidus temperature of the bonding layer.
Embodiments of the present invention describe micro semiconductor devices and a method of forming an array of micro semiconductor devices such as micro light emitting diodes (LEDs) for transfer to a receiving substrate. For example, the receiving substrate may be, but is not limited to, a display substrate, a lighting substrate, a substrate with functional devices such as transistors or integrated circuits (ICs), or a substrate with metal redistribution lines. While embodiments of the present invention are described with specific regard to micro LEDs comprising p-n diodes, it is to be appreciated that embodiments of the invention are not so limited and that certain embodiments may also be applicable to other micro semiconductor devices which are designed in such a way so as to perform in a controlled fashion a predetermined electronic function (e.g. diode, transistor, integrated circuit) or photonic function (LED, laser).
In various embodiments, description is made with reference to figures. However, certain embodiments may be practiced without one or more of these specific details, or in combination with other known methods and configurations. In the following description, numerous specific details are set forth, such as specific configurations, dimensions and processes, etc., in order to provide a thorough understanding of the present invention. In other instances, well-known semiconductor processes and manufacturing techniques have not been described in particular detail in order to not unnecessarily obscure the present invention. Reference throughout this specification to “one embodiment,” “an embodiment” or the like means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Thus, the appearances of the phrase “in one embodiment,” “in an embodiment” or the like in various places throughout this specification are not necessarily referring to the same embodiment of the invention. Furthermore, the particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.
The terms “spanning,” “over,” “to,” “between” and “on” as used herein may refer to a relative position of one layer with respect to other layers. One layer “spanning,” “over” or “on” another layer or bonded “to” another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer “between” layers may be directly in contact with the layers or may have one or more intervening layers.
The terms “micro” device, “micro” p-n diode or “micro” LED structure as used herein may refer to the descriptive size of certain devices or structures in accordance with embodiments of the invention. As used herein, the terms “micro” devices or structures are meant to refer to the scale of 1 to 100 μm. However, it is to be appreciated that embodiments of the present invention are not necessarily so limited, and that certain aspects of the embodiments may be applicable to larger, and possibly smaller size scales.
In one aspect, embodiments of the invention describe a method of processing a bulk LED substrate into an array of micro LED structures which are poised for pick up and transfer to a receiving substrate. In this manner, it is possible to integrate and assemble micro LED structures into heterogeneously integrated systems. The micro LED structures can be picked up and transferred individually, in groups, or as the entire array. Thus, the micro LED structures in the array of micro LED structures are poised for pick up and transfer to a receiving substrate such as display substrate of any size ranging from micro displays to large area displays, and at high transfer rates. In some embodiments, arrays of micro LED structures which are poised for pick up are described as having a 10 μm by 10 μm pitch, or 5 μm by 5 μm pitch. At these densities a 6 inch substrate, for example, can accommodate approximately 165 million micro LED structures with a 10 μm by 10 μm pitch, or approximately 660 million micro LED structures with a 5 μm by 5 μm pitch. Thus, a high density of pre-fabricated micro devices with a specific functionality may be produced in a manner in which they are poised for pick up and transfer to a receiving substrate. The techniques described herein are not limited to micro LED structures, and may also be used in the manufacture of other micro devices.
In another aspect, embodiments of the invention describe a micro LED structure and micro LED array in which each micro p-n diode is formed over a respective location of a bonding layer. The respective locations of the bonding layer may or may not be laterally separate locations. An operation may be performed on a respective location of the bonding layer corresponding to a micro LED during the micro LED pick up process in which the respective location of the bonding layer undergoes a phase change which assists in the pick up process. For example, the respective location of the bonding layer may change from solid to liquid in response to a temperature cycle. In the liquid state the respective location of the bonding layer may retain the micro p-n diode in place on a carrier substrate through surface tension forces, while also providing a medium from which the micro p-n diode is readily releasable. In addition, the liquid state may act as a cushion or shock absorber to absorb forces exerted by a transfer head if a transfer head makes contact with the micro LED structure during the pick up process. In this manner, the liquid state may compensate for non-uniformities in the topography in the micro LED array or transfer head array by smoothing out over the underlying surface in response to compressive forces exerted by a transfer head. In other embodiments, the respective location of the bonding layer may not undergo a complete phase transformation. For example, the respective location of the bonding layer may become substantially more malleable in response to a temperature cycle while partially remaining in the solid state. In another embodiment, the respective location of the bonding layer may undergo a crystal phase transformation in response to an operation, such as a temperature cycle.
Referring now to
The p-n diode layer 110 may include a compound semiconductor having a bandgap corresponding to a specific region in the spectrum. For example, the p-n diode layer 110 may include one or more layers based on II-VI materials (e.g. ZnSe) or III-V nitride materials (e.g. GaN, AlN, InN, and their alloys). Growth substrate 101 may include any suitable substrate such as, but not limited to, silicon, SiC, GaAs, GaN and sapphire (Al2O3).
In a particular embodiment, growth substrate 101 is sapphire, and the p-n diode layer 110 is formed of GaN. Despite the fact that sapphire has a larger lattice constant and thermal expansion coefficient mismatch with respect to GaN, sapphire is reasonably low cost, widely available and its transparency is compatible with excimer laser-based lift-off (LLO) techniques. In another embodiment, another material such as SiC may be used as the growth substrate 101 for a GaN p-n diode layer 110. Like sapphire, SiC substrates may be transparent. Several growth techniques may be used for growth of p-n diode layer 110 such as metalorganic chemical vapor deposition (MOCVD). GaN, for example, can be grown by simultaneously introducing trimethylgallium (TMGa) and ammonia (NH3) precursors into a reaction chamber with the sapphire growth substrate 101 being heated to an elevated temperature such as 800° C. to 1,000° C. In the particular embodiment illustrated in
A metallization layer 120 may then be formed over the p-n diode layer 110. As illustrated in
In accordance with certain embodiments of the invention, p-n diode layer 110 and metallization layer 120 are grown on a growth substrate 101 and subsequently transferred to a carrier substrate 201, such as one illustrated in
Referring now to
Referring now to
In certain embodiments, the pitch of the micro mesas 130 may be 5 μm, 10 μm, or larger. For example, a micro mesa 130 array with a 5 μm pitch may be formed of 3 μm wide micro mesas separated by a 2 μm spacing. A micro mesa 130 array with a 10 μm pitch may be formed of 8 μm wide micro mesas separated by a 2 μm spacing. Though, these dimensions are meant to be exemplary and embodiments of the invention are not so limited.
As described above with regard to
Bonding layer 210 may be formed from a variety of suitable materials. Bonding layer may be formed from a material which is capable of adhering a micro LED structure to a carrier substrate. In an embodiment, bonding layer 210 may undergo a phase change in response to an operation such as change in temperature. In an embodiment, bonding layer may be removable as a result of the phase change. In an embodiment, bonding layer may be remeltable or reflowable. In an embodiment, the bonding layer may have a liquidus temperature or melting temperature below approximately 350° C., or more specifically below approximately 200° C. At such temperatures the bonding layer may undergo a phase change without substantially affecting the other components of the micro LED structure. For example, the bonding layer may be formed of a metal or metal alloy, or of a thermoplastic polymer which is removable. In an embodiment, the bonding layer may be conductive. For example, where the bonding layer undergoes a phase change from solid to liquid in response to a change in temperature a portion of the bonding layer may remain on the micro LED structure during the pick up operation as described in more detail the following description. In such an embodiment, it may be beneficial that the bonding layer is formed of a conductive material so that it does not adversely affect the micro LED structure when it is subsequently transferred to a receiving substrate. In this case, the portion of conductive bonding layer remaining on the micro LED structure during the transfer operation may aid in bonding the micro LED structure to a conductive pad on the receiving substrate.
Solders may be suitable materials for bonding layer 210 since many are generally ductile materials in their solid state and exhibit favorable wetting with semiconductor and metal surfaces. A typical alloy melts not a single temperature, but over a temperature range. Thus, solder alloys are often characterized by a liquidus temperature corresponding to the lowest temperature at which the alloy remains liquid, and a solidus temperature corresponding to the highest temperature at which the alloy remains solid. An exemplary list of low melting solder materials which may be utilized with embodiments of the invention are provided in Table 1.
An exemplary list thermoplastic polymers which may be utilized with embodiments of the invention are provided in Table 2.
In accordance with embodiments of the invention, bonding layer 210 is formed with a uniform thickness and may be deposited by a variety of suitable methods depending upon the particular composition. For example, solder compositions may be sputtered, deposited by electron beam (E-beam) evaporation, or plated with a seed layer to obtain a uniform thickness.
Posts 202 may be formed from a variety of materials and techniques. In an embodiment, posts 202 may be formed integrally with carrier substrate 201 by patterning the carrier substrate 201 by an etching or embossing process. For example, carrier substrate 201 may be a silicon substrate with integrally formed posts 202. In another embodiment, posts can be formed on top of carrier substrate 201. For example, posts 202 may be formed by a plate up and photoresist lift off technique. Posts can be formed from any suitable material including semiconductors, metals, polymers, dielectrics, etc.
Referring now to
As described above, the structures of many of the examples can also be created by forming the bonding layer 210 on the growth substrate, followed by bonding the growth substrate 101 to the carrier substrate 201. For example, example 4O, can also be created by patterning bonding layer 210 and metallization layer 210 on growth substrate 101, following by bonding the growth substrate 101 to carrier substrate 201.
Referring now to
Referring now to
If either of the growth substrate 101 or carrier substrate 201 structures were not pre-patterned or only partially pre-patterned prior to bonding, then additional patterning may be performed after the p-n diode layer 110 thinning illustrated in
In the particular embodiment illustrated in
Referring now to
Upon completion of etching processes for the micro p-n diodes, metallization layer or bonding layer, the mask layer 140 may be removed, for example by using a selective etching technique, resulting the micro LED array illustrated in
In some embodiments, the micro p-n diodes 150 (as well as micro p-n diodes 135) include a top surface 152 and a bottom surface 151, and the metallization layer 120 includes a top surface 121 and a bottom surface, and the bottom surface 151 of the micro p-n diode 150 (as well as micro p-n diodes 135) is wider than the top surface 121 of the metallization layer 120.
In some embodiments, the plurality of micro p-n diodes 135, 150 each include a bottom surface 151 which has approximately the same width as a top surface 203 of each of the respective plurality of pillars 202. In other embodiments, the plurality of micro p-n diodes 135, 150 each include a bottom surface 151 which is wider than a top surface 203 of each of the respective plurality of pillars 202. The relationship of the micro p-n diode 135, 150 bottom width and underlying pillar 202 top surface may affect the pick up process. For example, if the bonding layer 210 exhibits a phase change from solid to liquid during the pick up process then the micro p-n diode 135, 150 is essentially floating on a liquid layer. Surface tension forces in the liquid bonding layer 210 may retain the micro p-n diode 135, 150 in place on top of the pillar 202. In particular, surface tension forces associated with the edges of the top surface of the pillar 202 may further assist in maintaining the micro p-n diode 135, 150 in place where the pillar 202 top surface width is less than or approximately equal to the p-n diode 135, 150 bottom width.
In some embodiments, the plurality of micro p-n diodes 135, 150 are positioned over an unpatterned bonding layer 210. For example, as illustrated in Example 6I and Example 8N, the bonding layer 210 may be a uniform layer on the carrier substrate and the corresponding plurality of locations of the bonding layer 210 are not laterally separate from each other. In other embodiments, the plurality of micro p-n diodes 135, 150 are positioned over a pattered bonding layer 210. For example, as illustrated in Examples 8A-8M and Example 8O, the patterned bonding layer may include a plurality of laterally separate locations of the bonding layer 210. In an embodiment, the plurality of micro p-n diodes 135, 150 each include a bottom surface 151 which has approximately the same or greater width than a corresponding top surface 211 for a plurality of laterally separate locations of the bonding layer 210.
As previously described the bonding layer may absorb compression forces associated with contacting the micro LED structure with a transfer head during the pick up process. As a result, the bonding layer may absorb the compressive forces and bulge out laterally. Where each micro LED structure is patterned to have a small separation distance, of 2 μm for example, the amount of bonding layer laterally protruding from each micro LED structure should be minimized so as to not interfere with an adjacent micro LED structure during the pick up process. In certain embodiments where trenches 206 are present between posts 202, the trenches may act as bonding layer reservoirs into which molten bonding layer may flow without interfering with an adjacent micro LED structure.
In some embodiments, the micro LED structures or array of micro LED structures of
The thin conformal dielectric layer and contact openings can be formed using a mask layer lift off technique. Referring to
Referring to
Referring now to
An embodiment of a method of transferring a micro LED structure to a receiving substrate is described in
A general illustration of operation 1320 in accordance with an embodiment is provided in
Still referring to
A variety of suitable transfer heads can be utilized to aid in the pick up and placement operations 1320, 1330 in accordance with embodiments of the invention. For example, the transfer head 300 may exert a pick up pressure on the micro LED structure in accordance with vacuum, magnetic, adhesive, or electrostatic principles in order to pick up the micro LED structure.
Still referring to
In utilizing the various aspects of this invention, it would become apparent to one skilled in the art that combinations or variations of the above embodiments are possible for forming an array of micro LED structures which are poised for pick up and transfer to a receiving substrate. Although the present invention has been described in language specific to structural features and/or methodological acts, it is to be understood that the invention defined in the appended claims is not necessarily limited to the specific features or acts described. The specific features and acts disclosed are instead to be understood as particularly graceful implementations of the claimed invention useful for illustrating the present invention.
This application is a continuation application of co-pending U.S. patent application Ser. No. 14/312,554, filed Jun. 23, 2014 which is a continuation of U.S. patent application Ser. No. 13/372,258, filed Feb. 13, 2012, now U.S. Pat. No. 8,794,501, which claims the benefit of priority from U.S. Provisional Patent Application Ser. No. 61/561,706 filed on Nov. 18, 2011 and U.S. Provisional Patent Application Ser. No. 61/594,919 filed on Feb. 3, 2012, the full disclosures of which are incorporated herein by reference.
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