The present invention relates to a display apparatus, and in particular to a display apparatus having a plurality of electrochemical display elements arranged in a matrix state.
In recent years, owing to operation speed increase of personal computers, improvement of network infrastructure and increase of capacity as well as price reduction of data storage, there is expanding opportunities that information such as images and documents conventionally provided as printed matters printed on paper are obtained as more convenient electronic data and the electronic data is browsed.
To brows such electronic data, conventionally there have been mainly used liquid crystal displays, CRTs, and recently luminescent type display such as organic EL displays. However, in case the electronic data is document data in particular, the document data has to be gazed for relatively a long time. As shortcomings of the luminescent type display in general, there are known ocular fatigue due to flicker, inconvenience of portability, a restricted posture of reading and large consumption of electric power when reading long time.
As a display method to resolve the above shortcomings, an electrochemical display method is known. For example, an electro deposition method (hereinafter abbreviated to ED) using dissolution deposition of metal or metallic salt is known (for example, refer to Patent Documents 1 and 2).
The display element of the ED method can be driven by a low voltage of 3V or less which can be realized with a simple cell structure and it has a feature that the display quality is superior (paper-like bright white and tight black).
To drive the electrochemical display element of such as ED method a predetermined voltage exceeding a threshold value is applied at both ends of the electrochemical display element for a predetermined time. The display conditions can be controlled by the voltage and time.
However, in the display apparatus having the plurality of the electrochemical display elements arranged in the matrix state, a current to drive the display apparatus is large. In particular, in case of the ED method, since dissolution deposition of metal or metallic salt is utilized, a large current is drawn at an initial stage of applying the voltage and a peak voltage to drive the display apparatus becomes very large. To address the large current, a power source circuitry having large current capacity has to be prepared, which causes cost increase.
Also, since bus wiring common for the plurality of the electrochemical display elements and common electrodes such as transparent electrodes have resistance to some extent in general, the voltage decreases as the elements recede from the power applying source, thus there is a problem that unevenness of display occurs.
To solve the above problem, there is suggested a method to make erasing and writing of the image uniform across an entire screen by setting a magnitude and an application time of a selection voltage to be applied to the counter electrodes in accordance with the distances from the drive section of the transparent electrodes (refer to Patent Document 3).
PRIOR ART DOCUMENT
Patent Document
Patent Document 1: Patent No. 3428603
Patent Document 2: Unexamined Japanese Patent Application Publication No. 2003-241227
Patent Document 3: Unexamined Japanese Patent Application Publication No. 2005-257956
Problems to be Solved by the Invention
However, even in the method disclosed in the Patent document 3, the voltage is apply to each element at the same timing, and the peak current becomes very large, thus the problem that the power source circuitry having the large capacity of current is needed has not yet been solved.
The present invention has one aspect to solve the above problems and an object of the present invention is to provide a display apparatus, which can employ a power source circuitry having small capacity, capable of cost reduction.
Means to Solve the Problem
The present invention can be achieved by the following structures.
Structure 1. A display apparatus, provided with a plurality of electrochemical display elements arranged in a matrix state, to apply voltage with respect to each electrochemical display element in a period of frames of which number correspond a density of an image to be displayed, comprising:
an assigning section to assign at least two different starting frame numbers to each electrochemical display element;
a voltage application control section to start application of a voltage to the electrochemical display element to which the starting frame number is assigned, when the frame number having been assigned to each frame period and the starting frame number coincide; and
a frame administration section to administrate a number of the frame periods which have been elapsed from a start of application of the voltage by the voltage application control section for each electrochemical display element,
wherein the voltage application control section control to apply the voltage to each electrochemical display element in the period of desired number of times of the frame periods based on the administration of the frame administration section.
Structure 2. The display apparatus of structure 1, wherein the assigning section assigns the different starting frame number for each column of the plurality of the electrochemical display elements arranged in the matrix state.
Structure 3. The display apparatus of structure 1, wherein the assigning section assigns the different starting frame number for each column and each line of the plurality of the electrochemical display elements arranged in the matrix state.
Structure 4. The display apparatus of structure 1, further comprising:
an ON pixel calculation section to calculate a number of the pixels of the electrochemical display elements to which the voltage is to be applied based on image data of an image to be displayed and
a dividing number determination section to determine a dividing number to divide the plurality of the electrochemical display elements in accordance with the number of the pixels calculated by the ON pixel calculation section,
wherein the assigning section determines the starting frame number based on the dividing number.
Structure 5. The display apparatus of structure 1, wherein a maximum value of the starting frame number is smaller than a number of times of frame periods necessary for displaying a maximum density by each electrochemical display element.
According to the present invention, by dispersing the timings to generate the current to drive the plurality of the electrochemical display elements, the power source circuitry having the small capacity can be employed thus cost reduction is possible.
The embodiment of the present invention will be described with reference to the drawings as follow.
The display apparatus 100 is, for example, a tablet PC, an electronic book, or a PDA to display data such as images and characters stored in a memory 10 (refer to
Also, in
The electrochemical display element 1 of the ED method shown by
As
Numeral 35 denotes the disposed silver and since the disposed silver absorbs light, the density of the electrochemical display element 1 observed from the ITO electrode 32 side becomes high. Numeral 36 schematically shows dissolved silver and a phenomenon that the disposed silver dissolved into the electrolyte 31 occurs at the silver electrode 30 side.
As
The electrolyte 31 included in the electrochemical display element 1 can be, for example, prepared by phase inversion of the silver from an aqueous silver salt solution to a non-aqueous silver salt solution. Such aqueous silver salt solution can be prepared by dissolving a publicly known silver salt into water.
In
In
The symbols 5a, 5b and 5c are scanning lines which connects gates of the switching transistors 4 arrayed in a line direction and the gate drivers 12 each other. The symbols 8a, 8b and 8c denote signal lines to connect sources of the switching transistors for each pixel arrayed in the line direction and the source drivers 14 each other. The gate driver 12 selectively outputs output voltages G1, G2 and G3 on the scanning lines 5a, 5b and 5c based on control of the control section 11 so as to conduct on/off control of the switching transistors 4 and to select a line which applies a control voltage onto the drive transistor 2. A drain of the drive transistor 2 is connected to the silver electrode 30 of the electrochemical display element 1 of each pixel and the source is connected to the ground via GND bus line 6.
The source driver 14 having driver circuits for each of signal lines 8a, 8b and 8c outputs output voltages S1, S2 and S3 on the signal lines 8a, 8b and 8c based on control of the control section 11. Driver circuits of the source driver 14 are binary drivers for on/off and outputs a control voltage Vs inputted to the source driver 14 based on control of the control section 11 or 0V representing an off voltage.
The control voltage source 15 outputs the control voltage Vs based on control of the control section 11 and supplies to the source driver 14.
The bus lines 7a, 7b and 7c are connected with ITO electrodes 32 of the electrochemical display elements 1 of respective pixels for respective lines and an end of each bus line is connected with a common power source 13. The common power source 13 outputs a common voltage Vc representing a negative voltage or positive voltage with a command of the control section 11.
When the output voltages S1, S2 and S3 of the source driver 14 are Vs which represent an On voltage, if the switching transistors 4 are turned on, Vs is applied onto the gates of the transistors 2, the driving transistors 2 are turned on and the common voltage Vc is applied onto the electrochemical display elements 1. After that, the driving transistors 2 stay on via a storage capacity, even the switching transistors 4 are turned off.
When the output voltages S1, S2 and S3 of the source driver 14 are 0V representing the off voltage, if the switching transistors 4 are turned on, 0V is applied onto the gates of the driving transistors 2, then the driving transistors are tuned off
The memory 10 is configured with recording media such as a ROM (Read Only Memory) and a flash memory.
A fust frame memory 60 and a second frame memory 61 are frame memories for one screen respectively having a memory area corresponding to the number of the pixels of the display screen 50. The first frame memory 60 stores a value X of the display density as fust image data to be subsequently displayed on the display screen 50 by the electrochemical display elements 1. The second frame memory 61 stores a value Y of the display density as second image data currently being displayed on the display screen 50 by the electrochemical display elements 1. In the figures, the fust frame memory 60 and the second frame memory 61 are respectively denoted by FM1 and FM2.
A touch panel controller 41 drives the touch panel 40 with a command of the control section 11 and transmits input position information readout from the touch panel 40 to the control section 11.
The control section 11 is configured with a CPU and so forth to control the entire display apparatus 100 based on a program.
An internal configuration of the control section 11 will be described with reference to
The control section 11 is configured with a CPU 98 (Central Processing Unit), a RAM 97 (Random Access Memory), a ROM 98 (Read Only Memory) and so forth. The control section 11 reads out a program stored in the ROM 96 representing a non-volatile memory section and upload onto the RAM 97, then controls each section of the display apparatus 100 in accordance with the program.
In
The ON pixel calculation section 80 calculates number of the pixels of the electrochemical display elements lto which the erasing or writing voltage is applied in subsequent image displaying based on the fust image data stored in the first frame memory 60.
The dividing number determination section 81 judges that into how many groups the plurality of the electrochemical display elements 1 are divided in accordance with the number of the pixels calculated by the ON pixel calculation section 80 and determines the dividing number.
The assigning section 82 determines a starting frame number at which application of the erasing voltage or the writing voltage onto each electrochemical display element 1 starts, before erasing or writing. The assigning section 82 assigns at least two different starting frame numbers to each electrochemical display element 1. Whereby, as described later, timings to start applying the erasing or writing voltage can be delayed.
The voltage application control section 83 controls the driving transistors 2 via the gate driver 12 and the source driver 14 so that the erasing voltage or the writing voltage is applied onto each electrochemical display element 1 based on the starting frame number and the frame number to be described. The voltage application control section 83 starts application of the voltage onto the electrochemical display element 1 to which the starting frame number is assigned when the frame number assigned to each frame period and the starting frame number coincide, and controls application of the voltage so that the voltage is applied onto each electrochemical display element 1 during a desired number of times of frame periods.
The frame administration section 84 administrates an elapsed time from starting application of the erasing or the writing voltage via the driving transistors 2 based on control of the voltage application control section 83 by adding the frame numbers every time the frame period elapses. As described later, the administration by the frame administration section 84 is executed by renewing the display density Y of the second frame memory 61 every time the frame period elapses. The electrochemical display elements 1 are administrated respectively.
Next, control when an image is displayed on the display apparatus 100 of the present embodiment will be described with reference to
In the following description, there is described an example to write an image by changing the display density of the electrochemical display elements 1 from a state where the display density of the electrochemical display elements 1 is 0 (white) by erasing an image in advance. In the above case, when starting writing, the writing voltage has to be applied into the most of the electrochemical display elements 1, however in the present embodiment by dispersing the timings of applying the writing voltage, an excessive peak current is inhibited to flow.
The flow chart in
Incidentally, writing of the image is carried out in each frame period basis. The frame period is denoted by FwN (N denotes the frame number).
At the beginning of writing, the CPU 98 instructs the common power source 13 to make the common voltage Vc to be a negative voltage of −Vcb.
S101 is a step of frame number N=1.
The frame administration section 84 initializes N to be N=1.
S102 is step of n=1.
The CPU 98 initializes n as a line number n=1, and makes G1 to be “H” via the gate driver 12.
S103 is a step where the starting frame number FS is assigned to each column of the pixels.
The assigning section 82 calls a FS assigning routine (refer to
In the present example, 1 is assigned to the starting frame number FSn1 of the pixel in the fust column, 2 is assigned to the starting frame number FSn2 of the pixel in the second column, and 3 is assigned to the starting frame number FSn3 of the pixel in the third column by the FS assigning routine. The procedure to assign the starting frame numbers by the FS assigning routine and other examples will be described specifically afterward.
S104 is a step to compare the values of display density in the first frame memory 60 and the second frame memory 61.
The voltage application control section 83 respectively reads out and compares the value Xnm of display density stored in the fust frame memory 60 and the value Ynm of display density stored in the second frame memory 61, subsequently in a line direction of n th line, and when Xnm>Ynm, the result of judgment is “H” and when Xnm≦Ynm the result of judgment is L″ . The CPU 98 temporally stores the judgment results in the RAM 97.
For example, as for the pixel in the fust line and the first column, if X11 were 8 and Y11 were 0, the judgment result is “H”.
S105 is a step to output “H” only for the columns of N≧FSnm.
The voltage application control section 83 judges only the columns of N≧FSnm among the columns whose results of comparison in the step S104 temporally stored in the RAM 97 was “H”, as “H”, and others as “L”. Then the voltage application control section 83 turns on the drivers circuits of the source driver 14 which have been judged as “H” and turns off the driver circuits of the source driver 14 which have been judged as “L”.
In the present embodiment, since the starting frame number N11 of the first line and first column is 1, as
S106 is a step to renew the value Y of the display density inn th line in the second frame memory 61.
The CPU 98 rewrites the value Y of the display density corresponding to the pixel inn th line in the second frame memory 61. Namely, the value Y of the display density for the pixel to which the writing voltage is applied in a period of one frame period is incremented by one. For example, assuming that the value Y11 of the display density in the fust line and the first column was 0, the value Y11 is rewritten to be 1.
S107 is a step to compare n and nmax.
The CPU 98 compares n with maximum line nmax of the display apparatus. In the example in
In case of n≠nmax, (step S107; No) step S108 is executed.
S108 is a step to delay by ΔT.
The CPU 98 creates a delay of ΔT by an internal timer. During the period of the delay, the output Gn of the gate driver 12 is maintained.
S109 is a step of n=n+1.
The CPU 98 makes Gn to be “L” since comparison operation is not completed up to the maximum line nmax, and makes Gn+1 to be “H”, after that n is incremented by 1(n=n+1) and process returns to step S103.
In case of n=nmax, (step S107;Yes), step S110 is executed.
S110 is a step to compare N with Xmax+FSmax−1.
The CPU 98 compares the frame number N with the maximum value Xmax of the value X of the display density+maximum value FSmax of the maximum FSmax of the starting frame number −1. In the present example, the maximum value Xmax of the value X of the display density is 8, and the maximum value FS max of the starting frame number is 3. Therefore, in the present example, whether or not the frame number N is 10 is judged in the present step. Namely, in the present step whether or not a control of number of times of frame periods necessary to display the image of the one screen is executed is judged in the present embodiment
In case of N≠Xmax+FSmax−1(step S110; No.) , step S111 is executed.
S111 is a step of N=N+1.
The CPU 98 conducts N=N+1 since the maximum frame N max is not achieved and returns to step S102.
In case of N=Xmax+FSmax−1(step S110 ; Yes), the process is terminated since the maximum frame N max is achieved.
The description of the flow chart is completed.
Next, the voltages Vp11, Vp12, Vp13 to be applied to the electrochemical display elements P11, P12, and P13 as well as the currents i11, i12 and i13 flowing into the electrochemical display elements P11, P12, and P13 will be described with reference to the time chart in
Incidentally, to simplify the drawings, the time chart in
As described in the flow chart in
In frame Fw1, −Vcb is applied to P11 and the current i11 flows. In the example in
Also, while being not illustrated, at a timing where G2 becomes “H” the current i21 flows in P21 and a timing where G3 becomes “H” the current i31 flows in P31.
In the frame Fw2, −Vcb is applied to P12 and the current i12 flows. For example, the value X of the display density of P12 is 8, and −Vca is applied to P12 up to the frame Fw9 equivalent to a period of eight frames As
Also, while being not illustrated in
In the frame Fw3, −Vcb is applied to P13 and the current i13 flows in the same manner.
In the example in
As above, in the present embodiment when writing is started, since the start timing of the peak current to flow in each electrochemical display element 1 is dispersed, the peak value of the current supplied form the power source can be suppressed. Also, an effect to display due to voltage depression in the buss lines 7a, 7b and 7c to which the electrochemical display element 1 is connected can be suppressed.
Therefore, an image having less unevenness can be displayed using a power source of a simple configuration having a small capacity.
Next, the FS assigning routine will be described.
S201 is a step to judge whether or not the frame number N is 1.
In case of N≠1, (step S110; No), the process returns to the original routine.
In case N=1, (step S110; Yes), the process proceeds to step S202.
S202 is a step to calculate the number of the pixels to which the writing voltage is applied from the value X of the display density.
The ON pixel calculation section 80 calculates the number of the pixels GON to be written from the value X of the display density stored in the fust frame memory 60. Specifically, the number of the pixels GON having the display density value X≠0.
S203 is a step to determined a dividing number Z.
The dividing number determination section 81 determines the dividing number Z from the pixel number GON calculated in step S202 in accordance with a table stored in the ROM 96 in advance.
Next, a specific example that the dividing number determination section 81 determines the dividing number Z using a table 1 shown below will be explained.
Table 1 is an example of the display apparatus 100 having display screen 50 with the number of the pixels (1024×768) of XGA and the total number of the pixels is 786432.The left column in
Table 1 shows the range of GON and the right column shows the dividing number Z corresponding to the range thereof As Table 1 shows, when 629146<GON≦786432. the dividing number Z is 3, when 393216<GON≦629146 the dividing number Z is 2 and when 0<GON≦393216, the dividing number is 1.
As above, when the number of the pixels GON to be written is large, the dividing number Z is increased to disperse the timing to start writing so as to reduce the peak current to flow at starting. On the other hand, when the number of the pixels GON to be written is small, the dividing number Z is decreased since the current to flow at starting is small so as to make a total writing time short.
S204 is a step to determine the starting frame number FSnm.
The assigning section 82 determines the starting frame number FSnm of each pixel based on the dividing number Z and column number m
The assigning section 82 determines the starting frame number FSnm by, for example, the formula (1) below.
FS
nm=mod((m+2)/Z)+1 (1)
Z denotes the dividing number, n denotes the line number, m denotes the column number and mod (A/B) is a function to obtain remainder of A/B.
As above, the process of the FS assigning routine is completed and the process returns to the original routine.
In the present embodiment, as
Not only for the present embodiment, it is preferable that the application timing of the voltage applied onto the electrochemical display elements 1 is dispersed by determining the starting frame numbers FSnm in accordance with wiring of the power source (common power source 13) of the electrochemical display elements 1. For example, in case the bus line 7 is disposed for each column, by setting the different starting frame numbernm for each column, the application timings of the voltages applied onto the electrochemical display elements 1 are dispersed. Also, for example, in case the bus line 7 is disposed for each predetermined area, by setting the starting frame numbers FSnm so that the starting frame numbers FS disperse for each predetermined area in the area, and the application timings of the voltages applied onto electrochemical display elements 1 are dispersed.
Next, a specific example of the starting frame number FSnm assigned to each pixel in the FS assigning routine and examples of a peak currents with reference to
As the difference of the starting frame number FSnm of each column is increased, an effect to disperse the timings at which the peak currents flow is enhanced thus the peak value of the power source current of the common power source can be suppressed.
In the example of
FS nm=mod((m+2)/Z)+2 (2)
a) shows that writing in the first frame has been completed, and the display density of the pixels in the fust column and the fourth column are 1.
c) shows that writing in the third frame has been completed, and the display density of the pixels in the first column and the fourth column are 3, that in the second column and fifth column are 2, and that in the third column is 1.
d) shows that writing in the seventh frame has been completed, and the display density of the pixels in the first column and the fourth column are 7, that in the second column and fifth column are 6, and that in the third column is 5.
e) shows that writing in the eighth frame has been completed, and the display density of the pixels in the first column and the fourth column is 8, that in the second column and fifth column are 7, and that in the third column are 6. By writing in the eighth frame, the writing of fust column and the fourth column from the first frame is completed.
f) shows that writing in the ninth frame has been completed, and the display density of the pixels in the second column and the fifth column are 8, that in the third column is 7. By writing in the ninth frame, the writing of the second column and the fifth column from the second frame is completed.
g) shows that writing in the tenth frame has been completed, and the display density of the pixels in the third column is 8. By writing in the tenth frame, the writing of the third column from the third frame is completed, thus writing of all pixels has been completed. Namely, as the starting frame number FSnm, values from one to three have been used, thus a period of ten times of the frame periods is used, wherein ten times of the frame period means a necessary number (eight times) to indicate the maximum display density plus a shifting amount (two times) of the starting frame.
On the other hand, as
Next a method to make the difference of density between the columns inconspicuous will be described.
Next,
In the example in
In case n is an odd number
FS
nm=mod(((m+n)+2)/z)+1 (3)
In case n is an even number
FS
nm=mod((1027-m−n)/z)+1 (4)
Z denotes the dividing number, n denotes the line number, m denotes the column number and mod (A/B) is a function to obtain remainder of A/B. The numeral 1027 is a maximum pixel number in the line direction in
In the above way, the difference of the density can be made inconspicuous compare to the case where starting frame number FSnm is shifted only for the columns
Incidentally, the present invention is not limited to the example in
Next, control to erase the image on the display apparatus 100 of the present embodiment will be described with reference to
Using the time chart in
Incidentally, in the time chart in
The procedure described with reference to the flow chart in
In the frame Fw1, Vca is applied to Pll and the current i11 flows. As
In the frame Fw2, Vca is applied to P12 and the current i12 flows. As
In the frame Fw3, Vca is applied to P13 and time the current i13 flows in the same manner.
Thereafter, in the frame Fw4, and the frame Fw5 current flows in all the electrochemical display elements 1.
As above, also when the image is erased, by dispersing the timings of start to flow the current in the electrochemical display elements 1, the peak value of the current supplied from the power source can be suppressed. Therefore, the image can be unfailingly erased even by a power source circuit having a simple configuration with a small capacity, since fluctuations of the erasing voltage are suppressed.
As above, according to the present embodiments, a reflection type display apparatus capable of displaying the image having less unevenness can be provided using the power source circuit having the simple configuration with the small capacity.
1 Electrochemical display element
2 Driving transistor
4 Switching transistor
5
a, 5b, 5c Scanning line
7
a, 7b, 7c Bus line
8
a, 8b, 8c Signal line
10 Memory
11 Control section
12 Gate driver
13 Common power source
14 Source driver
30 Silver electrode
31 Electrolyte
32 ITO electrode
34 Power source
80 ON pixel number calculation section
81 Diving number determination section
82 Assigning section
83 Voltage application control section
84 Frame control section
Number | Date | Country | Kind |
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2008-270672 | Oct 2008 | JP | national |
Filing Document | Filing Date | Country | Kind | 371c Date |
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PCT/JP2009/066500 | 9/24/2009 | WO | 00 | 4/13/2011 |