Patent Application
20240258465
This application claims the priority of Korean Patent Application No. 10-2023-0013592 filed on Feb. 1, 2023, which is hereby incorporated by reference its entirety.
The present disclosure relates to a display device including a light-emitting element, for example, a micro light-emitting element such as nanorod light-emitting element, and a method for manufacturing the same.
A display device is applied to various electronic devices such as TVs, mobile phones, laptops and tablets. To this end, research to develop thinning, lightening, and low power consumption of the display device is continuing.
Among display devices, a light-emitting display device has a light-emitting element or a light source built therein and displays information using light generated from the built-in light-emitting element or light source. A display device including a self-light-emitting element may be implemented to be thinner than a display device with the built-in light source, and may be implemented as a flexible display device that may be folded, bent, or rolled.
The display device having the self-light-emitting element may include, for example, an organic light-emitting display device (OLED) including a light-emitting layer made of an organic material, or a micro LED display device (micro light-emitting diode display device) including a light-emitting layer made of an inorganic material. In this regard, the organic light-emitting display device does not require a separate light source. However, due to material characteristics of the organic material that is vulnerable to moisture and oxygen, a defective pixel easily occurs in the organic light-emitting display device due to an external environment. On the contrary, the micro LED display device includes the light-emitting layer made of the inorganic material that is resistant to moisture and oxygen and thus is not affected by the external environment and thus has higher reliability and has a longer lifespan compared to the organic light-emitting display device.
The present disclosure is to provide a display device including a light-emitting element (for example, a micro light-emitting element such as a nanorod light-emitting element) having an electrode disposed only at one of both opposing ends. For example, the electrode may be made of a magnetic material.
The present disclosure is also to provide a display device in which at least one light-emitting element (for example, a micro light-emitting element such a nanorod light-emitting element) having only one electrode at one of both opposing ends is aligned with and received in a debossing groove, thereby improving luminance of the display device. For example, the electrode may be made of a magnetic material.
The present disclosure is not limited to the above-mentioned features and other features and advantages according to the present disclosure that are not mentioned may be understood based on following descriptions, and may be more clearly understood based on aspects according to the present disclosure. Further, it will be easily understood that the purposes and advantages according to the present disclosure may be realized using means shown in the claims or combinations thereof.
In an aspect of the present disclosure, a display device includes a base substrate including a display area and a circuit area: a planarization layer disposed on the base substrate: a plurality of debossing grooves defined in the planarization layer and disposed on the display area of the base substrate: at least one light-emitting element aligned with and received in the plurality of debossing grooves, respectively, wherein the light-emitting element includes a first semiconductor layer, an active layer, a second semiconductor layer, and a first electrode contacting the first semiconductor layer: a second electrode line electrically connected to the second semiconductor layer of the light-emitting element; and a first electrode line electrically connected to the first electrode of the light-emitting element.
In one implementation, an insulating layer disposed between the first electrode line and the second electrode line may be further comprised.
In one implementation, the second electrode line covers a top surface of the planarization layer between the adjacent debossing grooves and a part of a side surface of at least one of the debossing grooves while contacting the second semiconductor layer.
In one implementation, the first electrode line covers the planarization layer while being contact to the first electrode of the light-emitting element.
In one implementation, the first electrode of the light-emitting element aligned with and received in the debossing groove includes a magnetic material.
In one implementation, a multi-layer insulating structure is disposed under the plurality of debossing grooves and is disposed on the display area.
In one implementation, the light-emitting element disposed in the debossing grooves includes a nanorod shape.
In one implementation, the debossing groove includes a flat bottom surface and an inclined side surface inclined relative to the bottom surface.
In one implementation, the debossing groove includes a flat bottom surface, a protrusion protruding from the bottom surface, and an inclined side surface inclined relative to the bottom surface.
In one implementation, the protrusion has an outer surface area smaller than a cross-sectional area of the light-emitting element in a diameter direction, wherein the protrusion has an inclined side surface.
In one implementation, a length of the inclined side surface of the protrusion is smaller than or equal to a length of the light-emitting element.
In one implementation, the first electrode of each of a plurality of light-emitting elements is in contact with the bottom surface of a corresponding debossing groove.
In one implementation, a driving transistor and a storage capacitor for driving the light-emitting element are disposed in the circuit area.
In one implementation, at least one of the first electrode line and the second electrode line includes a transparent metal oxide including indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
In another aspect of the present disclosure, a display device includes a base substrate including a display area and a circuit area: a planarization layer disposed on the base substrate: a plurality of debossing grooves defined in the planarization layer and disposed on the display area of the base substrate: at least one light-emitting element aligned with and received in each of the debossing grooves, wherein the light-emitting element includes a first semiconductor layer, an active layer, a second semiconductor layer, and a first electrode contacting the first semiconductor layer: a second electrode line disposed on a portion of the planarization layer disposed between adjacent ones of the plurality of debossing grooves, wherein the second electrode line contacts the second semiconductor layer of the light-emitting element; and a first electrode line covering an insulating layer covering the second electrode line and the light-emitting elements, wherein the first electrode line is electrically connected to the first electrode.
In yet another aspect of the present disclosure, a method for manufacturing a display device includes forming a planarization layer on a base substrate including a display area and a circuit area: forming a plurality of debossing grooves in a portion of the planarization layer disposed on the display area: supplying fluid including a plurality of light-emitting elements on the planarization layer, wherein each of the plurality light-emitting elements includes a first semiconductor layer, an active layer, a second semiconductor layer, and a first electrode contacting the first semiconductor layer and being made of magnetic material: aligning the plurality light-emitting elements with the plurality of debossing grooves, respectively, through a magnetic field, such that the plurality light-emitting elements are received in the plurality of debossing grooves, respectively: forming a second electrode line on a portion of the planarization layer in which the plurality of debossing grooves are defined, the second electrode line electrically connected to the second semiconductor layer; and forming a first electrode line on the second electrode line, the first electrode line electrically connected to the first electrode.
According to one aspect of the present disclosure, the debossing groove may be introduced into the display device, thereby easily aligning the light-emitting element, for example, a micro light-emitting element such as nanorod-shaped light-emitting element.
Further, the debossing groove structure including the protrusion on the bottom surface thereof may be formed such that the plurality of light-emitting elements may be received in the debossing groove structure, thereby further improving luminance of the display device and thus driving the display device at a low power level and thus reducing the power consumption.
Further, for example, a light-emitting element (for example, a micro light-emitting element such as a nanorod light-emitting element) has an electrode disposed only at one of both opposing ends and made of a magnetic material. For example, the light-emitting element is oriented such that the electrode made of the magnetic material contacts the bottom surface of the debossing groove structure. Thus, the defect that light emission does not occur due to the alignment of the electrode of the light-emitting element and the pad electrode having opposite polarities with each other may be prevented.
Effects of the present disclosure are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the descriptions below.
The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of the disclosure, illustrate aspects of the disclosure and together with the description serve to explain the principle of the disclosure.
In the drawings:
Advantages and features of the present disclosure, and a method of achieving the advantages and features will become apparent with reference to aspects described later in detail together with the accompanying drawings. However, the present disclosure is not limited to the aspects as disclosed below, but may be implemented in various different forms. Thus, these aspects are set forth only to make the present disclosure complete, and to completely inform the scope of the present disclosure to those of ordinary skill in the technical field to which the present disclosure belongs.
A shape, a size, a ratio, an angle, a number, etc. disclosed in the drawings for describing the aspects of the present disclosure are exemplary, and the present disclosure is not limited thereto. The same reference numerals refer to the same elements herein. Further, descriptions and details of well-known steps and elements are omitted for simplicity of the description. Furthermore, in the following detailed description of the present disclosure, numerous specific details are set forth to provide a thorough understanding of the present disclosure. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present disclosure.
The terminology used herein is directed to the purpose of describing particular aspects only and is not intended to be limiting of the present disclosure. As used herein, the singular constitutes “a” and “an” are intended to include the plural constitutes as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprise”, “including”, “include”, and “including” when used in this specification, specify the presence of the stated features, integers, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, operations, elements, components, and/or portions thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. Expression such as “at least one of” when preceding a list of elements may modify the entire list of elements and may not modify the individual elements of the list. In interpretation of numerical values, an error or tolerance therein may occur even when there is no explicit description thereof.
In addition, it will also be understood that when a first element or layer is referred to as being present “on” a second element or layer, the first element or layer may be disposed directly on the second element or layer or may be disposed indirectly on the second element or layer with a third element or layer being disposed between the first and second elements or layers. It will be understood that when an element or layer is referred to as being “connected to”, or “coupled to” another element or layer, it may be directly connected to, or coupled to the other element or layer, or one or more intervening elements or layers may be present. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it may be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.
Further, as used herein, when a layer, film, region, plate, or the like may be disposed “on” or “on a top” of another layer, film, region, plate, or the like, the former may directly contact the latter or still another layer, film, region, plate, or the like may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, or the like is directly disposed “on” or “on a top” of another layer, film, region, plate, or the like, the former directly contacts the latter and still another layer, film, region, plate, or the like is not disposed between the former and the latter. Further, as used herein, when a layer, film, region, plate, or the like may be disposed “below” or “under” another layer, film, region, plate, or the like, the former may directly contact the latter or still another layer, film, region, plate, or the like may be disposed between the former and the latter. As used herein, when a layer, film, region, plate, or the like is directly disposed “below” or “under” another layer, film, region, plate, or the like, the former directly contacts the latter and still another layer, film, region, plate, or the like is not disposed between the former and the latter.
In descriptions of temporal relationships, for example, temporal precedent relationships between two events such as “after”, “subsequent to”, “before”, etc., another event may occur therebetween unless “directly after”, “directly subsequent” or “directly before” is indicated.
It will be understood that, although the terms “first”, “second”, “third”, and so on may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present disclosure.
The features of the various aspects of the present disclosure may be partially or entirely combined with each other, and may be technically associated with each other or operate with each other. The aspects may be implemented independently of each other and may be implemented together in an association relationship.
Unless otherwise defined, all terms including technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Hereinafter, a display device according to each aspect of the present disclosure will be described with reference to the accompanying drawings.
Referring to
The first semiconductor layer NS1 may be a layer for supplying electrons to the active layer EL, and may include a nitride-based semiconductor containing first conductivity type impurities. For example, the first conductivity-type impurity may include an N-type impurity. The active layer EL may be a layer for emitting light, and may include a multi-quantum well (MQW) having a well layer and a barrier layer having a higher band gap than that of the well layer.
The second semiconductor layer NS2 may be a layer for injecting holes into the active layer EL. The second semiconductor layer NS2 may include a nitride-based semiconductor containing second conductivity type impurities. For example, the second conductivity type impurity may include a P type impurity. The active layer EL may emit light based on a combination of electrons and holes respectively supplied from the first semiconductor layer NS1 and the second semiconductor layer NS2.
The nanorod-shaped light-emitting element includes electrodes having different polarities at both opposing ends, respectively, wherein the electrodes contact the first semiconductor layer and the second semiconductor layer, respectively. In a process of connecting the nanorod-shaped light-emitting element having the electrodes having different polarities to a pad electrode of a substrate, when the electrode of the nanorod-shaped light-emitting element is aligned with the pad electrode having a polarity opposite to the polarity of the electrode of the nanorod-shaped light-emitting element, light emission may not occur.
In this regard, in the light-emitting element ED according to one aspect of the present disclosure, the first electrode E1 is disposed to be in contact with one end face of the first semiconductor layer NS1, while the second semiconductor layer NS2 does not contact an electrode. The first electrode E1 may include a magnetic material. Due to the first electrode E1 including the magnetic material, the alignment of light-emitting elements may be improved. This will be described later with reference to
The light-emitting element ED according to
Referring to
A data line Vdata to which a data voltage is applied and a common voltage line Vcom to which a common voltage is applied may be spaced apart from each other and may be disposed respectively on both opposing sides of one pixel PX. The data line Vdata and the common voltage line Vcom may extend in a first direction (e.g., a vertical direction). A high-potential voltage line VDD and a scan line Vscan may be spaced from each other and extend in a second direction to intersect the data line Vdata and the common voltage line Vcom.
A plurality of light-emitting elements, a driving transistor T1, a switching transistor T2, a storage capacitor Cst and various lines may be arranged in an area defined by the data line Vdata and the common voltage line Vcom spaced apart from each other and extending in the first direction and the scan line Vscan and the high-potential voltage line VDD spaced from each other and extending in the second direction to intersect the data line Vdata and the common voltage line Vcom. The driving transistor T1 and the switching transistor T2 may drive the light-emitting element ED, and the storage capacitor Cst may store a voltage therein so that the light-emitting element ED continues to maintain the same state during one frame.
Referring to
The driving transistor T1 is disposed on the buffer layer 105. The driving transistor T1 may include a semiconductor layer ACT, a gate electrode GE, and a first interlayer insulating layer 110 located between the semiconductor layer ACT and the gate electrode GE and serving as a gate insulating layer. The semiconductor layer ACT may include an active area overlapping with the gate electrode GE to constitute a channel, and a source area and a drain area located respectively on both opposing sides of the active area, while the active area is disposed therebetween. The first interlayer insulating layer 110 may be disposed on an entire surface of the base substrate 102. A second interlayer insulating layer 115 may be disposed on the gate electrode GE.
The driving transistor T1 may include a source contact-hole SH and a drain contact-hole DH that extend through the second interlayer insulating layer 115 and the first interlayer insulating layer 110 to respectively expose portions of surfaces of the source area and the drain area located respectively on both opposing sides of the semiconductor layer ACT. A source electrode SE and a drain electrode DE may be respectively disposed on the source contact-hole SH and the drain contact-hole DH to be electrically connected to the source area and the drain area of the semiconductor layer ACT via the source contact-hole SH and the drain contact-hole DH, respectively.
The switching transistor T2 is spaced apart from the driving transistor T1. The switching transistor T2 may include a semiconductor layer ACT, a gate electrode GE, and the first interlayer insulating layer 110 located between the semiconductor layer ACT and the gate electrode GE and serving as a gate insulating layer. The semiconductor layer ACT may include an active area overlapping with the gate electrode GE to constitute a channel, and a source area and a drain area respectively located on both opposing sides of the active area while the active area is disposed therebetween. The switching transistor T2 may include a source electrode SE and a drain electrode DE extending through the second interlayer insulating layer 115 and the first interlayer insulating layer 110 to be electrically connected to the source area and the drain area of the semiconductor layer ACT.
The storage capacitor Cst may include a first capacitor electrode SC1 and a second capacitor electrode SC2. The first capacitor electrode SC1 may be disposed on the first interlayer insulating layer 110. The first capacitor electrode SC1 may be made of the same material as that of the gate electrode GE. The second interlayer insulating layer 115 may be disposed on the first capacitor electrode SC1 and may act as a dielectric layer. The second capacitor electrode SC2 may be disposed on the second interlayer insulating layer 115.
A signal line 120 may be coplanar with the source electrode SE and the drain electrode DE and may be disposed on the second interlayer insulating layer 115. The signal line 120 may include a plurality of signal lines. For example, the plurality of signal lines may include a plurality of scan lines Vscan, a plurality of high-potential voltage lines VDD, a plurality of data lines Vdata, and the common voltage line Vcom.
A planarization layer 130 covering the plurality of signal lines 120 and the source electrode SE and the drain electrode DE may be disposed. The planarization layer 130 may have a plurality of first debossing grooves 142 and a plurality of openings 135 and 136 defined therein. The first debossing groove 142 may include an inclined side surface 140 and a bottom surface 141. The bottom surface 141 of the first debossing groove 142 may be a flat surface, and the inclined side surface 140 may be inclined at a predetermined angle relative to the bottom surface. The first debossing groove 142 may have a circular shape in a top view, but not limited thereto. A length of the inclined side surface 140 of the first debossing groove 142 may be smaller than or equal to a length of the light-emitting element ED. The light-emitting element ED may be disposed on and in contact with the inclined side surface 140 of the first debossing groove 142.
The light-emitting element ED may have a nanorod structure in which the first semiconductor layer NS1, the active layer EL, and the second semiconductor layer NS2 are stacked. The first electrode E1 of the light-emitting element ED may include the magnetic material and may be disposed on and in contact with the bottom surface 141 of the first debossing groove 142.
In a portion of the display area AA in which the plurality of first debossing grooves 142 are disposed, not a line but a multi-layered insulating layer structure is disposed under the plurality of first debossing grooves.
In a portion of the display area AA in which the plurality of first debossing grooves 142 are disposed, the second electrode line 150 may be disposed on a portion of the planarization layer 130 having the plurality of first debossing grooves 142 defined therein. The second electrode line 150 may be disposed in an entirety of the display area AA, and may be formed to surround an outer circumferential surface of an upper portion of a portion of the planarization layer 130 between adjacent first debossing grooves 142 having a circular shape in the top view: The second electrode line 150 may be formed to extend along the inclined side surface 140 of the first debossing groove 142. The second electrode line 150 may extend along and on a top face of the portion of the planarization layer 130 between adjacent first debossing grooves 142. Accordingly, the second electrode line 150 may contact the second semiconductor layer NS2 of the light-emitting element ED. Further, the second electrode line 150 may contact a top face of the signal line 120 as exposed through the opening 136. The second electrode line 150 may include a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
An insulating layer 155 may be disposed on the planarization layer 130 on which the second electrode line 150 has been disposed. The insulating layer 155 may have a plurality of contact-holes 159a and 159b defined therein. The plurality of contact-holes 159a and 159b may include a first contact-hole 159a extending through the insulating layer 155 to expose the first electrode E1 of the light-emitting element ED received in the first debossing groove 142, and a second contact-hole 159b extending through the insulating layer 155 to expose a portion of the top surface of the drain electrode DE.
A first electrode line 160 may fill each of the plurality of contact-holes 159a and 159b. The first electrode line 160 may contact and be electrically connected to the first electrode E1 of the light-emitting element ED exposed through the first contact-hole 159a. Further, the first electrode line 160 may contact and be electrically connected to the portion of the drain electrode DE exposed through the second contact-hole 159a.
Referring back to
According to one aspect of the present disclosure, each of the plurality of light-emitting elements may be oriented such that the first electrode including the magnetic material may be positioned at the bottom surface of each of the plurality of first debossing grooves disposed on the display area of the base substrate. Accordingly, the defect that light emission does not occur due to the alignment of the electrode of the light-emitting element and the pad electrode having opposite polarities with each other may be prevented. Further, the debossing groove may have a protrusion on the bottom surface thereof, such that at last two light-emitting elements may be received in one debossing groove, thereby improving luminance of the display device, and thus driving the display device at a low power level and thus reducing power consumption.
Referring to
At least two light-emitting elements ED may be disposed on and in contact with the inclined side surface 143a of the second debossing groove 145. At least two light-emitting elements ED may not overlap with each other due to the protrusion 144.
Each of at least two light-emitting elements ED disposed in the second debossing groove 145 may be oriented such that the first electrode E1 of each of the light-emitting elements ED made of the magnetic material contacts the bottom surface 143b. The light-emitting element ED may have, for example, a nanorod structure in which the first semiconductor layer NS1, the active layer EL, and the second semiconductor layer NS2 are stacked.
The second electrode line 150 may be disposed on a portion of the planarization layer 130 having the plurality of second debossing grooves 145 defined therein in the display area AA. The second electrode line 150 may be disposed in an entirety of the display area AA and may be formed to surround an outer circumferential surface of an upper portion of a portion of the planarization layer 130 disposed between adjacent second debossing grooves 145. The second electrode line 150 may be formed to extend along and on the inclined side surface 143a. Accordingly, the second electrode line 150 may contact the second semiconductor layer NS2 of the light-emitting element ED. Further, the second electrode line 150 may contact the top face of the signal line 120 exposed through the opening 136. The second electrode line 150 may include a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
The insulating layer 155 may be disposed on the planarization layer 130 on which the second electrode line 150 has been disposed. The insulating layer 155 may have the plurality of contact-holes 159a and 159b defined therein. The plurality of contact-holes 159a and 159b may include the first contact-hole 159a extending through the insulating layer 155 to expose the first electrode E1 of the light-emitting element ED received in the second debossing groove 145, and a second contact-hole 159b extending through the insulating layer 155 to expose a portion of the top surface of the drain electrode DE.
The first electrode line 160 may fill each of the plurality of contact-holes 159a and 159b. The first electrode line 160 may contact and be electrically connected to the first electrode E1 of the light-emitting element ED exposed through the first contact-hole 159a. Further, the first electrode line 160 may contact and be electrically connected to the portion of the drain electrode DE exposed through the second contact-hole 159b.
According to another aspect of the present disclosure, at least two light-emitting elements may be received in one second debossing groove, thereby improving luminance of the display device.
Hereinafter, a method for manufacturing a display device according to aspects of the present disclosure will be described with reference to the drawings.
The buffer layer 105 is disposed on the base substrate 102 including the display area AA and the circuit area CA. The buffer layer 105 may block impurities or moisture through the base substrate 102. The buffer layer 105 may include, for example, an insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The driving transistor T1 is disposed on the buffer layer 105. The driving transistor T1 may include the semiconductor layer ACT, the gate electrode GE, and the first interlayer insulating layer 110 located between the semiconductor layer ACT and the gate electrode GE and serving as a gate insulating layer. The semiconductor layer ACT may include an active area overlapping with the gate electrode GE to constitute a channel, and a source area and a drain area located respectively on both opposing sides of the active area, while the active area is disposed therebetween. The first interlayer insulating layer 110 may be disposed on an entire surface of the base substrate 102. The second interlayer insulating layer 115 may be disposed on the gate electrode GE.
The driving transistor T1 may include the source contact-hole SH and the drain contact-hole DH that extend through the second interlayer insulating layer 115 and the first interlayer insulating layer 110 to respectively expose portions of surfaces of the source area and the drain area located respectively on both opposing sides of the semiconductor layer ACT. The source electrode SE and the drain electrode DE of the driving transistor T1 may be respectively disposed on the source contact-hole SH and the drain contact-hole DH to be electrically connected to the source area and the drain area of the semiconductor layer ACT via the source contact-hole SH and the drain contact-hole DH, respectively.
The switching transistor T2 may be disposed to be spaced apart from the driving transistor T1. The switching transistor T2 may include the semiconductor layer ACT, the gate electrode GE, and the first interlayer insulating layer 110 located between the semiconductor layer ACT and the gate electrode GE and serving as a gate insulating layer. The semiconductor layer ACT may include an active area overlapping with the gate electrode GE to constitute a channel, and a source area and a drain area respectively located on both opposing sides of the active area while the active area is disposed therebetween. The switching transistor T2 may include a source electrode SE and a drain electrode DE extending through the second interlayer insulating layer 115 and the first interlayer insulating layer 110 to be electrically connected to the source area and the drain area of the semiconductor layer ACT.
The storage capacitor Cst may include the first capacitor electrode SC1 and the second capacitor electrode SC2. The first capacitor electrode SC1 may be disposed on the first interlayer insulating layer 110. The first capacitor electrode SC1 may be made of the same material as that of the gate electrode GE. The second interlayer insulating layer 115 may be disposed on the first capacitor electrode SC1 and may act as a dielectric layer. The second capacitor electrode SC2 may be disposed on the second interlayer insulating layer 115.
The signal line 120 may be coplanar with the source electrode SE and the drain electrode DE and may be disposed on the second interlayer insulating layer 115. The signal line 120 may include a plurality of signal lines. For example, the plurality of signal lines may include a plurality of scan lines Vscan, a plurality of high-potential voltage lines VDD, a plurality of data lines Vdata, and the common voltage line Vcom.
The planarization layer 130 covering the plurality of signal lines 120 and the source electrode SE and the drain electrode DE may be disposed. The planarization layer 130 serves to remove a surface step caused by an underlying structure such as the driving transistor T1. The planarization layer 130 may include a photoactive compound (PAC). However, the present disclosure is not limited thereto.
Referring to
The first debossing groove 142 may provide a space in which the light-emitting element is received later. The length of the inclined side surface 140 of the first debossing groove 142 may be smaller than or equal to the length of the light-emitting element ED. A length of the bottom surface 141 of the first debossing groove 142 may be sized such that both when the light-emitting element is in contact with the inclined side surface 140 and when the light-emitting element is spaced away from the inclined side surface 140, the light-emitting element is not displaced by a size of a diameter of a top of the light-emitting element or greater. For example, the length of the bottom surface 141 of the first debossing groove 142 may be larger than the diameter of the light-emitting element and may be smaller than two times of the diameter of the light-emitting element.
Accordingly, the first debossing groove 142 may have a cone-shaped cross-sectional shape in which a width thereof gradually decreases as the groove 142 extends downwardly to the bottom surface 141.
In a portion of the display area AA in which the plurality of first debossing grooves 142 are disposed, not a line but a multi-layered insulating layer structure is disposed under the plurality of first debossing grooves. A magnetic field may be used in a self-assembly process for aligning the light-emitting elements with the plurality of first debossing grooves 142. Accordingly, to prevent the line from being affected or damaged by the magnetic field, in the portion of the display area AA in which the plurality of first debossing grooves 142 are disposed, the line is not disposed under the plurality of first debossing grooves.
The plurality of openings 135 and 136 defined in the planarization layer 130 may include the first opening 135 exposing a portion of the surface of the drain electrode DE and the second opening 136 exposing a portion of the surface of the signal line 120.
Referring to
A first alignment magnet M1 having a first magnetic flux density is placed on the other surface opposite to one surface of the planarization layer 130 in which the plurality of first debossing grooves 142 are defined. Using a translational motion of the first alignment magnet M1, each of the plurality of light-emitting elements ED dispersed in the fluid F is aligned with and received in the debossing groove 142, as shown in
In one example, as shown in
In this case, a second alignment magnet M2 which has a relatively lower magnetic flux density than that of the first alignment magnet M1 which has the first flux density moves from a position above the planarization layer 130 toward the planarization layer 130 while the second alignment magnet M2 is opposite to the first alignment magnet M1 in the gravitational direction. When the second alignment magnet M2 moves in the upper and lower directions, the light-emitting element ED is turned upside down such that the first electrode E1 of the light-emitting element ED made of the magnetic material may contact the bottom surface 141 of the first debossing groove 142, as shown in
Referring to
Referring to
Referring to
Next, the first electrode line 160 is formed on the insulating layer 155. The first electrode line 160 may fill each of the plurality of contact-holes 159a and 159b. The first electrode line 160 may contact and be electrically connected to the first electrode E1 of the light-emitting element ED exposed through the first contact-hole 159a. Further, the first electrode line 160 may contact and be electrically connected to the portion of the drain electrode DE exposed through the second contact-hole 159b and thus may be electrically connected to the driving transistor T1. The first electrode line 160 may include a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
According to one aspect of the present disclosure, the cone-shaped first debossing groove 142 is defined on the display area of the base substrate 102. Then, the magnetic field is generated in a vertical upwardly direction from a position under the bottom surface of the first debossing groove 142 toward the light-emitting element having the first electrode E1 disposed at one end thereof and made of the magnetic material. Thus, the light-emitting element may be easily aligned with and received in the first debossing groove 142. Further, the light-emitting efficiency of the light-emitting element may be improved due to the inclined side surface of the first debossing groove 142.
In one example, the light-emitting efficiency may be further improved by modifying the structure of the debossing groove. This will be described with reference to the drawings below.
Referring to
The planarization layer 130 having the plurality of second debossing grooves 145 defined therein may be disposed on the second interlayer insulating layer 115. The second debossing groove 145 may include the inclined side surface 143a, the bottom surface 143b, and the protrusion 144 protruding from the bottom surface 143b. The second debossing groove 145 may have a cone-shaped cross-sectional shape in which a width thereof gradually decreases as the groove 145 extends downwardly to the bottom surface 143b. The second debossing groove 145 may have a circular shape as shown in
The protrusion 144 may have an outer surface area smaller than a cross-sectional area of the light-emitting element ED in a diameter direction, and may have the inclined side surface so that the light-emitting element ED does not contact the protrusion 144.
Referring to
Each of at least two light-emitting elements ED disposed in the second debossing groove 145 may be oriented such that the first electrode E1 of each of the light-emitting elements ED made of the magnetic material contacts the bottom surface 143b. A position of the nanorod-shaped light-emitting element ED placed in the second debossing groove 145 may be irregular per the second debossing groove 145. In one example, referring to
Referring to
Referring to
Next, the first electrode line 160 is formed on the insulating layer 155. The first electrode line 160 may fill each of the plurality of contact-holes 159a and 159b. The first electrode line 160 may contact and be electrically connected to the first electrode E1 of the light-emitting element ED exposed through the first contact-hole 159a. Further, the first electrode line 160 may contact and be electrically connected to the portion of the drain electrode DE exposed through the second contact-hole 159b and thus may be electrically connected to the driving transistor T1. The first electrode line 160 may include a transparent metal oxide such as indium-tin-oxide (ITO) or indium-zinc-oxide (IZO).
According to another aspect of the present disclosure, the second debossing groove 145 having the cone shape may be defined on the display area of the base substrate 102 and may include the protrusion 144 disposed on the bottom surface 143b thereof. Then, the magnetic field is generated in a vertical upwardly direction from a position under the bottom surface of the second debossing groove 145 toward the light-emitting element having the first electrode E1 disposed at one end thereof and made of the magnetic material. Thus, the light-emitting element ED may be easily aligned with and received in the second debossing groove 145. Further, due to the structure in which the protrusion 144 is disposed on the bottom surface 143b, at least two or more light-emitting elements ED may be placed in one second debossing groove 145 so as not to overlap with each other. Accordingly, the light-emitting efficiency of the light-emitting element may be improved.
It will be apparent to those skilled in the art that various modifications and variations can be made in the display device and the method for manufacturing the same of the present disclosure without departing from the spirit or scope of the aspects. Thus, it is intended that the present disclosure covers the modifications and variations of the aspects provided they come within the scope of the appended claims and their equivalents.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0013592 | Feb 2023 | KR | national |
