Patent Application
20250046240
The disclosure relates to an electronic device, and in particular to a display device and a Mura compensation method thereof.
The Mura phenomenon on an organic light-emitting diode (OLED) panel is mainly due to the deviation of the OLED current caused by the uneven material properties of a thin-film transistor (TFT). Generally speaking, the Mura uneven phenomenon near the panel boundary is relatively serious. In the Mura compensation of the prior art, the Mura of the panel is mainly captured to quantify the information of the Mura into a value, and then the grayscale of the pixel is compensated according to the value. Such a method is defined as De-Mura (elimination of Mura). De-Mura needs to store a large amount of pixel data for compensation. Generally speaking, Mura may have different changes with different usage scenarios. For example, different frame refresh rates (frame rates) may have different Mura. The prior art needs to store different Mura compensation lookup tables corresponding to different frame refresh rates. Storing a large amount of compensation information for pixel compensation means increasing the manufacturing cost.
The disclosure provides a display device and a Mura compensation method thereof to improve the Mura uniformity.
In an embodiment of the disclosure, the above-mentioned display device includes a display panel and a Mura compensation circuit. The Mura compensation circuit is coupled to the display panel. The Mura compensation circuit defines a first compensation area in the display panel based on a first curve equation corresponding to a current frame rate of the display panel. The Mura compensation circuit calculates at least one first compensation weight in the first compensation area based on the current frame rate and the first curve equation. The Mura compensation circuit uses the at least one first compensation weight to compensate at least one pixel data in the first compensation area, so as to generate a compensated pixel data frame. The Mura compensation circuit provides the compensated pixel data frame to the display panel for displaying images.
In an embodiment of the disclosure, the above-mentioned Mura compensation method includes: a first compensation area in a display panel is defined based on a first curve equation corresponding to a current frame rate of the display panel; at least one first compensation weight in the first compensation area is calculated based on the current frame rate and the first curve equation; at least one pixel data in the first compensation area is compensated by using the at least one first compensation weight, so as to generate a compensated pixel data frame; and the compensated pixel data frame is provided to the display panel for displaying images.
In an embodiment of the disclosure, the above-mentioned display device includes a display panel and a Mura compensation circuit. The Mura compensation circuit is coupled to the display panel. The Mura compensation circuit obtains a coefficient and an index value corresponding to a current frame rate of the display panel from a lookup table. The Mura compensation circuit calculates at least one compensation weight based on the coefficient and the index value. The Mura compensation circuit uses the at least one compensation weight to compensate at least one pixel data, so as to generate a compensated pixel data frame. The Mura compensation circuit provides the compensated pixel data frame to the display panel for displaying images.
In an embodiment of the disclosure, the above-mentioned Mura compensation method includes: a coefficient and an index value corresponding to a current frame rate of a display panel is obtained from a lookup table; at least one compensation weight is calculated based on the coefficient and the index value; at least one pixel data is compensated by using the at least one compensation weight, so as to generate a compensated pixel data frame; and the compensated pixel data frame is provided to the display panel for displaying images.
In an embodiment of the disclosure, the above-mentioned display device includes a display panel, a voltage supply circuit and a Mura compensation circuit. The voltage supply circuit is coupled to the display panel to provide an initialization voltage. The Mura compensation circuit is coupled to the display panel and the voltage supply circuit. In response to a current frame rate of the display panel changing from an original frame rate to a new frame rate, the Mura compensation circuit obtains a new voltage setting value corresponding to the new frame rate from a lookup table. The Mura compensation circuit controls the voltage supply circuit based on the new voltage setting value. The voltage supply circuit dynamically adjusts the initialization voltage based on the control of the Mura compensation circuit.
In an embodiment of the disclosure, the above-mentioned Mura compensation method includes: in response to a current frame rate of a display panel changing from an original frame rate to a new frame rate, a new voltage setting value corresponding to the new frame rate is obtained from a lookup table; and a voltage supply circuit is controlled based on the new voltage setting value, so as to dynamically adjust an initialization voltage to the display panel.
Based on the above, in some embodiments, the Mura compensation circuit may dynamically define the compensation area in the display panel based on the curve equation corresponding to the current frame rate, and then calculate the compensation weight in the compensation area based on the current frame rate and the curve equation. The Mura compensation circuit uses the compensation weight to compensate the pixel data in the compensation area, so as to generate a compensated pixel data frame to improve the Mura uniformity. In some other embodiments, the Mura compensation circuit obtains the coefficient and the index value from a lookup table based on the current frame rate, and then calculates the compensation weight based on the coefficient and the index value. The Mura compensation circuit uses the compensation weight to compensate the pixel data, so as to generate a compensated pixel data frame to improve the Mura uniformity. In yet some other embodiments, in response to the current frame rate of the display panel changing from the original frame rate to a new frame rate, the Mura compensation circuit obtains a new voltage setting value corresponding to the new frame rate from a lookup table. The Mura compensation circuit controls the voltage supply circuit based on the new voltage setting value and dynamically adjusts the initialization voltage of the pixel array of the display panel, so as to improve the Mura uniformity.
In order to make the aforementioned features and advantages of the disclosure comprehensible, embodiments accompanied with drawings are described in detail as follows.
The term “coupled (or connected)” used in the specification (including the claims) may refer to any direct or indirect means of connection. For example, if that a first device is coupled (or connected) to a second device is described in the specification, the description should be construed that the first device may be directly connected to the second device, or the first device may be indirectly connected to the second device through other devices or some kind of connection means. The terms “first,” “second” and the like mentioned in the specification (including the claims) are used to name the elements or to distinguish different embodiments or scopes and are not intended to limit the upper or lower limit of the number of the elements, nor are the terms intended to limit the order of the elements. In addition, wherever possible, elements/components/steps with the same reference numerals in the drawings and embodiments represent the same or similar parts. Elements/components/steps with the same reference numerals or with the same terminology in different embodiments may refer to relative descriptions of each other.
The Mura compensation circuit 110 may compensate at least one pixel data in the compensation area of a pixel data frame D_in, so as to generate a compensated pixel data frame D_out. The Mura compensation circuit 110 may provide the compensated pixel data frame D_out to the display panel 130 for displaying images. According to different design, in some embodiments, the implementation manner of the Mura compensation circuit 110 may be a hardware circuit. In some other embodiments, the implementation manner of the Mura compensation circuit 110 may be firmware, software (i.e., a program), or a combination thereof. In yet some other embodiments, the implementation manner of the Mura compensation circuit 110 may be a combination of hardware, firmware and software.
In terms of hardware, the above-mentioned Mura compensation circuit 110 may be implemented as a logic circuit in an integrated circuit. For example, the related functions of the Mura compensation circuit 110 may be implemented in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), central processing units (CPUs) and/or various logic blocks, modules and circuits in other processing units. The related functions of the Mura compensation circuit 110 may be implemented as hardware circuits by using hardware description languages (such as Verilog HDL or VHDL) or other suitable programming languages, such as various logic blocks, modules and circuits in integrated circuits.
In terms of software and/or firmware, the above-mentioned related functions of the Mura compensation circuit 110 may be implemented as programming codes. For example, the Mura compensation circuit 110 is realized by using general programming languages (such as C, C++, or an assembly language) or other suitable programming languages. The programming code may be recorded/stored in a “non-transitory machine-readable storage medium”. In some embodiments, the non-transitory machine-readable storage medium includes, for example, a semiconductor memory and/or a storage device. The semiconductor memory includes a memory card, a read only memory (ROM), a FLASH memory, a programmable logic circuit or other semiconductor memories. The storage device includes a tape, a disk, a hard disk drive (HDD), a solid-state drive (SSD), or other storage devices. An electronic device (such as a computer, a CPU, a controller, a microcontroller, or a microprocessor) may read and execute the programming code from the non-transitory machine-readable storage medium, thereby realizing the related functions of the Mura compensation circuit 110.
The test machine may capture the Mura of the display panel 130. The Mura compensation circuit 110 may distinguish the areas where the Mura uneven phenomenon are relatively serious (the compensation areas Rmura31 and Rmura32) from the entire display area of the display panel 130 based on the grayscale threshold (index value), thereby determining the curve equation x{circumflex over ( )}2−C_L*(y+V)=0 and the curve equation (x−H){circumflex over ( )}2−C_R*(y+V)=0 according to the areas where the Mura uneven phenomenon are relatively serious. The grayscale threshold (index value) may be any real number determined according to actual design. The Mura compensation circuit 110 may calculate the coefficients C_L and C_R of the curve equations based on a compensation data frame and an index value I corresponding to the current frame rate, and record the current frame rate, the coefficient C_L and the coefficient C_R in a lookup table. Table 1 below is one of many examples of lookup tables.
A calculation example of the coefficients C_L and C_R is described here. When the display panel 130 is at a certain reference frame rate (for example, 120 Hz or other frame rates), the test machine may capture the display panel 130 to calculate a compensation data frame applicable to the reference frame rate. The calculation of the compensation data frame may be any De-Mura (elimination of Mura) algorithm, such as the known De-Mura algorithm or other De-Mura algorithms. Similarly, when the display panel 130 is at any frame rate (such as 30 Hz, 45 Hz, 75 Hz, 90 Hz, or other frame rates), the test machine may capture the display panel 130 to calculate the compensation data frames applicable to different frame rates.
The current frame rate is assumed to be 30 Hz, the index value I corresponding to the current frame rate of 30 Hz is assumed to be 130, a pixel compensation data in a compensation data frame C1 corresponding to the current frame rate of 30 Hz is assumed to be C1[x,y] (the coordinates in the compensation data frame C1 are [x,y]), and a corresponding pixel compensation data in a compensation data frame C2 corresponding to the reference frame rate (such as 120 Hz or other frame rates) is assumed to be C2[x,y] (the coordinates in the compensation data frame C2 are [x,y]). The Mura compensation circuit 110 calculates a ratio R1[x,y] of C1[x,y] to C2[x,y], so as to generate the ratio frame R1 corresponding to the current frame rate of 30 Hz. The Mura compensation circuit 110 compares the index value 130 with all ratios in the ratio frame R1 and determines geometric parameters of the compensation areas Rmura31 and Rmura32. The Mura compensation circuit 110 calculates the coefficients C_L and C_R of the curve equations based on the geometric parameters and the index value 130. Suppose the coefficients C_L and C_R corresponding to the current frame rate of 30 Hz are L30 and R30 respectively, the Mura compensation circuit 110 may record the current frame rate of 30 Hz, the coefficient L30, the coefficient R30 and the index value 130 in the above Table 1 (lookup table).
Taking the compensation area Rmura31 as an example, the curve equation is x{circumflex over ( )}2−C_L*(y+V)=0. The Mura compensation circuit 110 may calculate C_L=(a{circumflex over ( )}2)/V, where C_L is the coefficient of the curve equation x{circumflex over ( )}2−C_L*(y+V)=0, a is the geometric parameter of the compensation area Rmura31 (a is the upper boundary length of the compensation area Rmura31) and V is the vertical resolution of the display panel 130. Taking the compensation area Rmura32 as an example, the curve equation is (x−H){circumflex over ( )}2−C_R*(y+V)=0. The Mura compensation circuit 110 may calculate C_R=(b{circumflex over ( )}2)/V, where C_R is the coefficient of the curve equation (x−H){circumflex over ( )}2−C_R*(y+V)=0, b is the geometric parameter of the compensation area Rmura32 (b is the upper boundary length of the compensation area Rmura32), V is the vertical resolution of the display panel 130 and H is the horizontal resolution of the display panel 130.
For other frame rates (such as 45 Hz, 75 Hz, 90 Hz, or other frame rates), reference may be made to the relevant description of the frame rate of 30 Hz and analogies may further be made, and thus details are not repeated here. The Mura compensation circuit 110 may record the frame rate of 45 Hz, coefficient L45, coefficient R45 and index value 145 in the above Table 1, record the frame rate of 75 Hz, coefficient L75, coefficient R75 and index value 175 in the above Table 1 and record the frame rate of 90 Hz, coefficient L90, coefficient R90 and index value I90 in the above Table 1.
Referring to
In step S220, based on the current frame rate, the curve equation x{circumflex over ( )}2−C_L*(y+V)=0 and the curve equation (x−H){circumflex over ( )}2−C_R*(y+V)=0, the Mura compensation circuit 110 may calculate the compensation weight in the compensation area Rmura31 and the compensation weight in the compensation area Rmura32. In step S230, the Mura compensation circuit 110 may use the compensation weight of the compensation area Rmura31 to compensate at least one pixel data in the compensation area Rmura31 of the pixel data frame D_in, and use the compensation weight of the compensation area Rmura32 to compensate at least one pixel data in the compensation area Rmura32, so as to generate the compensated pixel data frame D_out. In step S240, the Mura compensation circuit 110 may provide the compensated pixel data frame D_out to the display panel 130 for displaying images.
In response to the current frame rate changing from the original frame rate to a new frame rate, the Mura compensation circuit 110 may obtain a new coefficient C_L, a new coefficient C_R and a new index value I corresponding to the new frame rate from a lookup table (such as the above Table 1). The Mura compensation circuit 110 may update the curve equation x{circumflex over ( )}2−C_L*(y+V)=0 and the curve equation (x−H){circumflex over ( )}2−C_R*(y+V)=0 based on the new coefficients C_L and C_R. The Mura compensation circuit 110 may use the new index value I and the new curve equations to calculate the compensation weight in the compensation area Rmura31 and the compensation weight in the compensation area Rmura32. The Mura compensation circuit 110 may use the compensation weight of the compensation area Rmura31 to compensate the pixel data in the compensation area Rmura31, and use the compensation weight of the compensation area Rmura32 to compensate the pixel data in the compensation area Rmura32.
For example, the curve equation of the compensation area Rmura31 is x{circumflex over ( )}2−C_L*(y+V)=0, and the Mura compensation circuit 110 may calculate W=1+(x{circumflex over ( )}2−C_L*(y+V))*I/C_V, where W is the compensation weight of the compensation area Rmura31, C_L is the new coefficient of the curve equation of the compensation area Rmura31, V is the vertical resolution of the display panel 130, I is the new index value and C_V is a real coefficient related to the vertical resolution V. The curve equation of the compensation area Rmura32 is (x−H){circumflex over ( )}2−C_R*(y+V)=0, and the Mura compensation circuit 110 may calculate W=1+((x−H){circumflex over ( )}2−C_R*(y+V))*I/C_V, where W is the compensation weight of the compensation area Rmura32, H is the horizontal resolution of the display panel 130, C_R is the new coefficient of the curve equation of the compensation area Rmura32, V is the vertical resolution of the display panel 130, I is the new index value and C_V is a real coefficient related to the vertical resolution V.
In the embodiment shown in
To sum up, the Mura compensation circuit 110 may obtain the coefficients C_L and C_R from a lookup table (such as the above Table 1) based on the current frame rate. The Mura compensation circuit 110 may dynamically define the compensation area Rmura31 of the display panel 130 based on the curve equation x{circumflex over ( )}2−C_L*(y+V)=0 corresponding to the current frame rate, and dynamically define the compensation area Rmura32 of the display panel 130 based on the curve equation (x−H){circumflex over ( )}2−C_R*(y+V)=0 corresponding to the current frame rate. The Mura compensation circuit 110 may calculate the compensation weight in the compensation area Rmura31 based on the current frame rate and the curve equation x{circumflex over ( )}2−C_L*(y+V)=0, and calculate the compensation weight in compensation area Rmura32 based on the current frame rate and the curve equation (x−H){circumflex over ( )}2−C_R*(y+V)=0. The Mura compensation circuit 110 may use the compensation weight of the compensation area Rmura31 to compensate the pixel data in the compensation area Rmura31, and use the compensation weight of the compensation area Rmura32 to compensate the pixel data in the compensation area Rmura32, so as to generate the compensated pixel data frame D_out to improve the Mura uniformity.
For example, the curve equation of the compensation area Rmura31 is x{circumflex over ( )}2−C_L*(y+V)=0. Please refer to
To sum up, the Mura compensation circuit 110 may obtain the coefficient C_L, the coefficient C_R and the index value from a lookup table (such as the above Table 1) based on the current frame rate, and then calculate the compensation weight in the compensation area Rmura31 and the compensation weight in the compensation area Rmura32 based on the coefficients and the index value. The Mura compensation circuit 110 may use the compensation weight of the compensation area Rmura31 to compensate the pixel data in the compensation area Rmura31, and use the compensation weight of the compensation area Rmura32 to compensate the pixel data in the compensation area Rmura32, so as to generate the compensated pixel data frame D_out to improve the Mura uniformity.
To sum up, in response to the current frame rate of the display panel 130 changing from the original frame rate to a new frame rate, the Mura compensation circuit 110 may obtain a new voltage setting value corresponding to the new frame rate from a lookup table (such as the above Table 1). The Mura compensation circuit 110 may control the voltage supply circuit 120 based on the new voltage setting value to dynamically adjust the initialization voltage Vini of the pixel array of the display panel 130, thereby improving the Mura uniformity.
Although the disclosure has been described with reference to the above embodiments, the described embodiments are not intended to limit the disclosure. People of ordinary skill in the art may make some changes and modifications without departing from the spirit and the scope of the disclosure. Thus, the scope of the disclosure shall be subject to those defined by the attached claims.
