Patent Application
20250224432
This application claims priority to Chinese Patent Application No. 202411686634.7 filed Nov. 22, 2024, the disclosure of which is incorporated herein by reference in its entirety.
The present disclosure relates to the field of display technology and, in particular, to a display device and a test method therefor.
A display panel needs to be bonded to a driver chip (for example, an integrated circuit (IC)) that provides drive signals for a display region. Generally, the IC is bonded in two manners. The first manner is chip on film (COF), where the IC is fixed to a flexible circuit board (for example, a flexible printed circuit (FPC)), and the FPC is bonded to a substrate of the display panel. The second manner is chip on glass (COG), where the IC is bonded to a glass substrate of the display panel, and the FPC is bonded to a substrate of the display panel to be electrically connected to the IC. After the IC is bonded, the flexible circuit board (for example, the FPC) is connected to a control circuit board (for example, a printed circuit board (PCB)).
During bonding, a bonding resistance value between a terminal (for example, a pad) of the display panel and an IC pad and a bonding resistance value between a terminal (for example, a pad) of the display panel and an FPC pad affect the connection effect between the display panel and the control circuit board. Therefore, the bonding resistance value after bonding needs to be detected.
In the related art, an IC bonding resistance value of an in-vehicle display device cannot be directly measured and is calculated according to theoretical values. A total resistance value of an entire test loop may be tested through test terminals disposed on the PCB, and other resistance values such as the bonding resistance value of the FPC pad, a bonding resistance value of a PCB pad, and a resistance value of an in-plane wire in the test loop are subtracted from the total resistance value so that the IC bonding resistance value is obtained. The bonding resistance value of the FPC pad can be directly measured at an FPC impedance test terminal, but the resistance value of the in-plane wire needs to be actually measured through pad pricks, which waste a lot of time and energy and are inconvenient to operate.
Embodiments of the present disclosure provide a display device and a test method therefor, so as to accurately measure an IC bonding resistance value in a simpler manner.
In a first aspect, embodiments of the present disclosure provide a display device. The display device includes a substrate and a metal layer disposed on the substrate, where the metal layer includes a first panel pad, a second panel pad, and a third panel pad.
The display device is bonded to a driver chip and a flexible circuit board; a first chip pad of the driver chip is bonded to the first panel pad; a first circuit board pad of the flexible circuit board is bonded to the second panel pad; a second circuit board pad of the flexible circuit board is bonded to the third panel pad; a third circuit board pad of the flexible circuit board is bonded to a first control board pad of a control circuit board; and a fourth circuit board pad of the flexible circuit board is bonded to a second control board pad of the control circuit board.
The first chip pad, the first panel pad, a first metal wire of the metal layer, the second panel pad, the first circuit board pad, a first internal wire of the flexible circuit board, the third circuit board pad, and the first control board pad are connected in sequence to form a first branch; a second metal wire of the metal layer, the third panel pad, the second circuit board pad, a second internal wire of the flexible circuit board, the fourth circuit board pad, and the second control board pad are connected in sequence to form a second branch; first chip pads of two first branches are electrically connected through a third metal wire of the metal layer to form a first test loop; and second metal wires of two second branches are electrically connected through a fourth metal wire of the metal layer to form a second test loop; where the length of the first metal wire is substantially the same as the length of the second metal wire.
The control circuit board includes a first test terminal, a second test terminal, a third test terminal, and a fourth test terminal; the first test terminal is electrically connected to the first control board pad at a first end of the first test loop; the second test terminal is electrically connected to the first control board pad at a second end of the first test loop; the third test terminal is electrically connected to the second control board pad at a first end of the second test loop; and the fourth test terminal is electrically connected to the second control board pad at a second end of the second test loop.
In a second aspect, embodiments of the present disclosure provide a test method for a display device. The test method is applicable to the display device of any embodiment of the present disclosure and includes the steps below.
A first resistance value R1 of the first test loop in the display device is measured through the first test terminal and the second test terminal.
A second resistance value R2 of the second test loop in the display device is measured through the third test terminal and the fourth test terminal.
A bonding resistance value R of the first chip pad of the driver chip of the display device is acquired according to the first resistance value R1 and the second resistance value R2, where R=(R1−R2)/2.
The present disclosure is further described in detail below in conjunction with drawings and embodiments. It is to be understood that the embodiments described herein are intended to illustrate the present disclosure and not to limit the present disclosure. Additionally, it is to be noted that for ease of description, only part, not all, of structures related to the present disclosure are illustrated in the drawings.
To solve the preceding problems, embodiments of the present disclosure provide a display device.
The display device is bonded to a driver chip 13 and a flexible circuit board 14; a first chip pad 131 of the driver chip 13 is bonded to the first panel pad 121; a first circuit board pad 141 of the flexible circuit board 14 is bonded to the second panel pad 122; a second circuit board pad 142 of the flexible circuit board 14 is bonded to the third panel pad 123; a third circuit board pad 143 of the flexible circuit board 14 is bonded to a first control board pad 151 of a control circuit board 15; and a fourth circuit board pad 144 of the flexible circuit board 14 is bonded to a second control board pad 152 of the control circuit board 15.
The first chip pad 131, the first panel pad 121, a first metal wire 12a of the metal layer 12, the second panel pad 122, the first circuit board pad 141, a first internal wire 14a of the flexible circuit board 14, the third circuit board pad 143, and the first control board pad 151 are connected in sequence to form a first branch 21; a second metal wire 12b of the metal layer 12, the third panel pad 123, the second circuit board pad 142, a second internal wire 14b of the flexible circuit board 14, the fourth circuit board pad 144, and the second control board pad 152 are connected in sequence to form a second branch 22; first chip pads 131 of two first branches 21 are electrically connected through a third metal wire 12c of the metal layer 12 to form a first test loop 31; and second metal wires 12b of two second branches 22 are electrically connected through a fourth metal wire 12d of the metal layer 12 to form a second test loop 32; where the length of the first metal wire 12a is substantially the same as the length of the second metal wire 12b.
The control circuit board 15 includes a first test terminal 15a, a second test terminal 15b, a third test terminal 15c, and a fourth test terminal 15d; the first test terminal 15a is electrically connected to the first control board pad 151 at a first end of the first test loop 31; the second test terminal 15b is electrically connected to the first control board pad 151 at a second end of the first test loop 31; the third test terminal 15c is electrically connected to the second control board pad 152 at a first end of the second test loop 32; and the fourth test terminal 15d is electrically connected to the second control board pad 152 at a second end of the second test loop 32.
In the embodiments of the present disclosure, a display panel includes the substrate and the metal layer formed on the substrate, and the display device includes the display panel and the driver chip and the flexible circuit board bonded to the display panel. The metal layer forms panel pads, the driver chip includes the first chip pad, and the flexible circuit board includes circuit board pads. The first chip pad, the first panel pad, the first metal wire of the metal layer, the second panel pad, the first circuit board pad, the first internal wire of the flexible circuit board, the third circuit board pad, and the first control board pad are connected in sequence to form the first branch; the second metal wire of the metal layer, the third panel pad, the second circuit board pad, the second internal wire of the flexible circuit board, the fourth circuit board pad, and the second control board pad are connected in sequence to form the second branch; and the two first branches form the first test loop, and the two second branches form the second test loop. In the embodiments of the present disclosure, test terminals may be disposed so that a resistance value of the first test loop and a resistance value of the second test loop are tested, and a bonding resistance value of the first chip pad is acquired according to a difference between the resistance values of the two loops, avoiding a need for pricks with probes to estimate the bonding resistance value of the first chip pad according to a resistance value of the metal wire in the metal layer, omitting actual measurement inconvenient to operate, and avoiding the consumption of a lot of time and energy. Additionally, in the embodiments of the present disclosure, the bonding resistance value of the first chip pad is measured through the first test loop and the second test loop, effectively reducing an error caused by the actual measurement and improving the accuracy of the bonding resistance value of the chip pad.
Technical solutions in the embodiments of the present disclosure are described clearly and completely hereinafter in conjunction with drawings in the embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without any creative efforts are within the scope of the present disclosure.
In one or more embodiments, the display device in the embodiments of the present disclosure includes the display panel and the driver chip 13 and the flexible circuit board (for example, an FPC) 14 that are bonded to the display panel. The flexible circuit board 14 may be a good flexible printed circuit board with high reliability and made of a base material such as a polyimide or polyester film. The flexible circuit board has the characteristics of high wiring density, light weight, thin thickness, and good bendability. In the embodiments of the present disclosure, the flexible circuit board 14 may be bent to a back surface of the display panel and bonded to the control circuit board (for example, a PCB) 15 of the display device. The control circuit board 15 may be an aluminum oxide ceramic circuit board or an aluminum nitride ceramic circuit board. The circuit board enables circuits to be mini and visualized and plays an important role in the batch production of fixed circuits and the optimization of electrical device layout. For ease of illustration,
Referring to
It is to be noted that the bonding resistance value R between the panel pad and the chip pad forms a voltage drop in a signal transmission path, reducing a signal transmission effect and degrading an image display effect of the display panel. Therefore, the measurement of the bonding resistance value R is of great significance for the optimization of IC bonding. However, the bonding resistance value R cannot be measured directly, and when the bonding resistance value R is calculated through the metal wire in the metal layer 12, poor measurement accuracy and a waste of manpower are caused. In the embodiments of the present disclosure, in addition to the signal transmission path formed between the display panel, the driver chip 13, and the flexible circuit board 14, other branches are disposed to form the first test loop 31 and the second test loop 32, the bonding resistance value R between the first panel pad 121 and the first chip pad 131 is provided in the first test loop 31, the bonding resistance value R between the first panel pad 121 and the first chip pad 131 is omitted in the second test loop 32, and a difference between measured resistance values of the two test loops is obtained so that the bonding resistance value R between the first panel pad 121 and the first chip pad 131 can be acquired separately, saving a labor cost and achieving relatively high measurement accuracy since resistance values formed by other components in the test loops tend to be the same.
In one or more embodiments, as shown in
The second metal wire 12b of the metal layer 12, the third panel pad 123, the second circuit board pad 142, the second internal wire 14b of the flexible circuit board 14, the fourth circuit board pad 144, and the second control board pad 152 are connected in sequence to form the second branch 22. A resistance value of the second metal wire 12b is R22, a bonding resistance value R23 is formed between the third panel pad 123 and the second circuit board pad 142, a resistance value of the second internal wire 14b can be ignored, a bonding resistance value R24 is formed between the fourth circuit board pad 144 and the second control board pad 152, the two second branches 22 may form the second test loop 32 through the fourth metal wire 12d of the metal layer 12, the fourth metal wire 12d forms a resistance value R25, the control circuit board 15 is provided with the third test terminal 15c and the fourth test terminal 15d, the third test terminal 15c is connected through a second auxiliary connection line 155 to the second control board pad 152 in one second branch 22 in the second test loop 32, the fourth test terminal 15d is connected through the second auxiliary connection line 155 to the second control board pad 152 in the other second branch 22 in the second test loop 32, and the control circuit board 15 includes the copper wires so that resistance values of the third test terminal 15c, the fourth test terminal 15d, and the second auxiliary connection line 155 are almost zero and can be ignored. Therefore, a resistance value of the second test loop 32 is (2R22+2R23+2R24+R25).
In a panel manufacturing technique, the length of the first metal wire 12a may be substantially the same as the length of the second metal wire 12b. In the embodiments of the present disclosure, “substantially the same” has two meanings: (1) the length of the first metal wire 12a may be completely the same as the length of the second metal wire 12b, and (2) a difference between the length of the first metal wire 12a and the length of the second metal wire 12b is less than a set range, where the set range may be set by a user as required. Thus, the resistance value R12 of the first metal wire 12a tends to be the same as the resistance value R22 of the second metal wire 12b so that a difference between the resistance value of the second test loop 32 and the resistance value of the first test loop 31 does not affect the calculation of the bonding resistance value R11 between the first chip pad 131 and the first panel pad 121. Additionally, in the embodiments of the present disclosure, a pad manufacturing technique is controlled so that the bonding resistance value R13 between the second panel pad 122 and the first circuit board pad 141 can be controlled to be substantially the same as the bonding resistance value R23 between the third panel pad 123 and the second circuit board pad 142, and the bonding resistance value R14 between the third circuit board pad 143 and the first control board pad 151 can be controlled to be substantially the same as the bonding resistance value R24 between the fourth circuit board pad 144 and the second control board pad 152. Then, the bonding resistance value R11 between the first chip pad 131 and the first panel pad 121 is ((2R11+2R12+2R13+2R14+R15)−(2R22+2R23+2R24+R25))/2. That is, since the other components forming the test loops are in one-to-one correspondence and have the same resistance values, the difference between the resistance value of the first test loop 31 and the resistance value of the second test loop 32 is only the bonding resistance value R11 of the first chip pad 131. In the embodiments of the present disclosure, it is unnecessary to acquire the resistance values of the first metal wire 12a and the second metal wire 12b through manual pricks with probes so that the labor cost can be reduced, and an error caused by manual detection can be avoided, thereby improving the measurement accuracy of R11.
In one or more embodiments, the control circuit board 15 may be further configured to measure a first resistance value R1 between the first test terminal 15a and the second test terminal 15b and measure a second resistance value R2 between the third test terminal 15c and the fourth test terminal 15d; and the control circuit board 15 is further configured to acquire the bonding resistance value R11 of the first chip pad 131 according to the first resistance value R1 and the second resistance value R2.
In the embodiments of the present disclosure, the resistance value measured between the first test terminal 15a and the second test terminal 15b is referred to as the first resistance value R1, and the resistance value measured between the third test terminal 15c and the fourth test terminal 15d is referred to as the second resistance value R2, where the first resistance value R1 is (2R11+2R12+2R13+2R14+R15), and the second resistance value R2 is (2R22+2R23+2R24+R25). The bonding resistance value R11 of the first chip pad 131 is (R1−R2)/2. In the embodiments of the present disclosure, the first test terminal 15a, the second test terminal 15b, the third test terminal 15c, and the fourth test terminal 15d are additionally disposed on the control circuit board 15 so that the resistance values of the two test loops are measured, and the bonding resistance value R11 between the first chip pad 131 and the first panel pad 121 is acquired according to the difference between the measured resistance values of the two test loops, avoiding a need for calculation through the measurement of the first metal wire 12a in the test loop through probes, providing a simpler measurement manner convenient to operate, and achieving a relatively small error.
In one or more embodiments, the first metal wire 12a and the second metal wire 12b may have the same width. Since it is required in the embodiments of the present disclosure that the resistance value R12 of the first metal wire 12a be the same as or tend to be consistent with the resistance value R22 of the second metal wire 12b, to further ensure that R12 and R22 are the same, it is required in the embodiments of the present disclosure that when the length of the first metal wire 12a is substantially the same as the length of the second metal wire 12b, the first metal wire 12a and the second metal wire 12b be configured to have the same width. The metal wires of the metal layer have the same width and length so that the resistance values of the metal wires tend to be consistent. In the embodiments of the present disclosure, when the bonding resistance value R11 of the first chip pad 131 is acquired according to the difference between the first resistance value R1 and the second resistance value R2, since R12 and R22 are completely the same or tend to be consistent, the measurement accuracy of the bonding resistance value R11 of the first chip pad 131 is improved.
In one or more embodiments, the first metal wire 12a and the second metal wire 12b may be disposed in the same layer. The display panel may include the substrate 11 and the metal layer 12 on the substrate 11. The substrate 11 may be made of a rigid material such as glass or made of a polymer material such as polyimide (PI) or polyethylene terephthalate (PET). Multiple metal layers 12 may be included on the substrate 11, and an insulating layer is disposed between two adjacent metal layers 12. The multiple metal layers 12 may form the driver circuit layer. In a plane parallel to the substrate 11, the driver circuit layer includes the pixel driving circuits arranged in the array. The light-emitting device layer may be further disposed on a side of the driver circuit layer facing away from the substrate 11, and the light-emitting devices correspondingly connected to the pixel driving circuits are disposed in the light-emitting device layer and can emit light of corresponding colors under the control of the pixel driving circuits. In the embodiments of the present disclosure, the first metal wire 12a and the second metal wire 12b may be formed in the same metal layer 12 so that the first metal wire 12a and the second metal wire 12b are made of the same material and have the same film thickness, making it convenient to directly control the resistance values through the lengths of the first metal wire 12a and the second metal wire 12b to make R12 and R22 the same. In one or more embodiments, in the embodiments of the present disclosure, the first metal wire 12a and the second metal wire 12b disposed in the same layer have the same length and width to further make R12 and R22 the same, improving the measurement accuracy of the bonding resistance value R11 of the first chip pad 131.
Based on the preceding embodiments, in one or more embodiments, a difference between the length of the third metal wire 12c and the length of the fourth metal wire 12d may be less than or equal to a first set threshold. In addition to the first metal wire 12a and the second metal wire 12b, the third metal wire 12c in the first test loop 31 and the fourth metal wire 12d in the second test loop 32 are also metal wires of the metal layer 12, and their resistance values cannot be ignored. In the embodiments of the present disclosure, the resistance value R15 of the third metal wire 12c is substantially the same as the resistance value R25 of the fourth metal wire 12d. That is, the resistance value R15 of the third metal wire 12c is the same as the resistance value R25 of the fourth metal wire 12d, or a difference between the resistance value R15 of the third metal wire 12c and the resistance value R25 of the fourth metal wire 12d is less than a certain set resistance value. In the embodiments of the present disclosure, the third metal wire 12c and the fourth metal wire 12d may be controlled to be disposed in the same layer, and the difference between the length of the third metal wire 12c and the length of the fourth metal wire 12d may be less than or equal to the first set threshold to control R15 and R25 to be substantially the same, improving the measurement accuracy of the bonding resistance value R11 of the first chip pad 131. In one or more embodiments, the first set threshold may be 1% of the length of the first metal wire 12a; or the first set threshold is 5% of the length of the third metal wire 12c. In a process of calculating R11, to improve the calculation accuracy of R11, the difference between the length of the third mental wire 12c and the length of the fourth mental wire 12d is less than or equal to 1% of the length of the first metal wire 12a or 5% of the length of the third metal wire 12c. Since the resistance of a metal wire is proportional to the length of a metal wire, the resistance difference between R15 and R25 is less than 1% of the resistance value R12 of the first metal wiring 12a, or less than or equal to 5% of the resistance value R15 of the third metal wiring 12c, reducing measurement errors of the first resistance value R1 and the second resistance value R2 and further reducing the measurement error of the bonding resistance value R11 of the first chip pad 131.
In one or more embodiments, the length of the third metal wire 12c may be the same as the length of the fourth metal wire 12d. In the embodiments of the present disclosure, the length of the third metal wire 12c and the length of the fourth metal wire 12d may be accurately controlled to be the same so that R15 and R25 are completely the same, further improving the measurement accuracy of the bonding resistance value R11 of the first chip pad 131.
In one or more embodiments, the first circuit board pad 141 and the second circuit board pad 142 may have the same size; and the third circuit board pad 143 and the fourth circuit board pad 144 have the same size. The first circuit board pad 141 in the first test loop 31 and the second circuit board pad 142 in the second test loop 32 may have the same shape and area. After the flexible circuit board 14 is successfully aligned with and bonded to the display panel, the bonding resistance value R13 formed between the first circuit board pad 141 and the second panel pad 122 of the display panel is the same as the bonding resistance value R23 formed between the second circuit board pad 142 and the third panel pad 123 of the display panel. In the embodiments of the present disclosure, two adjacent circuit board pads of the flexible circuit board 14 have the same interval, and two adjacent panel pads in the metal layer 12 also have the same interval. After the flexible circuit board 14 is successfully aligned with the display panel, an overlapping area between the first circuit board pad 141 and the second panel pad 122 is the same as an overlapping area between the second circuit board pad 142 and the third panel pad 123 so that the bonding resistance value R13 is the same as the bonding resistance value R23.
In the display process of the display device, the control circuit board 15 is required to output the control signal to the flexible circuit board 14, the flexible circuit board 14 controls the driver chip 13, and the driver chip 13 sends the signals to the display panel to control the pixel driving circuits of the display panel to implement the image display. In addition to the first branch 21 and the second branch 22, the third branch 23 may be further included. The first branch 21 and the second branch 22 are configured to form the test loops for testing the bonding resistance value R11, and the third branch 23 is configured to transmit the signal output from the control circuit board 15. In one or more embodiments, the third branch 23 includes the second chip pad 132 of the driver chip 13, the fourth panel pad 124 of the display panel, the seventh metal wire 12g of the metal layer 12, the fifth panel pad 125 of the display panel, the fifth circuit board pad 145 of the flexible circuit board 14, the third internal wire 14c of the flexible circuit board 14, the sixth circuit board pad 146 of the flexible circuit board 14, and the third control board pad 153 of the control circuit board 15, which are connected in sequence. The second chip pad 132 is bonded to the fourth panel pad 124, the fifth panel pad 125 is bonded to the fifth circuit board pad 145, and the sixth circuit board pad 146 is bonded to the third control board pad 153. In one or more embodiments, the first chip pad 131 and the second chip pad 132 have the same size so that a bonding resistance value between the second chip pad 132 and the fourth panel pad 124 is substantially the same as R11; the first circuit board pad 141, the second circuit board pad 142, and the fifth circuit board pad 145 have the same size so that a bonding resistance value between the fifth panel pad 125 and the fifth circuit board pad 145 is substantially the same as R13 or R23; and the third circuit board pad 143, the fourth circuit board pad 144, and the sixth circuit board pad 146 have the same size so that a bonding resistance value between the sixth circuit board pad 146 and the third control board pad 153 is substantially the same as R14 or R24. Additionally, a resistance value of the seventh metal wire 12g of the metal layer 12 is substantially the same as the resistance value of the first metal wire 12a or the second metal wire 12b. Therefore, in the embodiments of the present disclosure, an overall resistance value of the third branch 23 is substantially the same as the overall resistance value of the first branch 21. When the bonding resistance value of the driver chip 13 is measured according to the difference between the resistance value of the first test loop and the resistance value of the second test loop, the measurement accuracy is relatively high and the measurement manner is simple and convenient to operate.
In one or more embodiments, the flexible circuit board 14 may include a first edge L1 and a second edge L2 opposite to each other, the first edge L1 and the second edge L2 extend along a first direction X, and the first direction X is parallel to a plane where the substrate 11 is located; the first circuit board pad 141, the second circuit board pad 142, and multiple fifth circuit board pads 145 are arranged along the first edge L1; and along the first direction X, the first circuit board pad 141 and the second circuit board pad 142 are disposed on at least one side of the multiple fifth circuit board pads 145.
The flexible circuit board 14 includes the first edge L1 close to the display panel and the second edge L2 away from the display panel. The first edge L1 and the second edge L2 may extend along the first direction X, and the first direction X is a direction of a straight line parallel to the plane of the substrate. The first circuit board pad 141, the second circuit board pad 142, and the multiple fifth circuit board pads 145 are arranged along the first edge L1, and the first circuit board pad 141 and the second circuit board pad 142 are disposed on at least one side of the multiple fifth circuit board pads 145. As shown in
Referring to
In addition to the structure shown in
In the embodiments of the present disclosure, the second test loop 32 may be embedded in the first test loop 31. In one or more embodiments, the following arrangement sequence is formed along the first direction X: the first branch 21, the second branch 22, the second branch 22, and the first branch 21, where the two first branches 21 are connected through the fifth metal wire 12e to form the first test loop 31, and the two second branches 22 are connected through the sixth metal wire 12f to form the second test loop 32. Similarly, the length of the fifth metal wire 12e is substantially the same as the length of the sixth metal wire 12f, so as to ensure that the difference between the first test loop 31 and the second test loop 32 lies in only the bonding resistance values R11 between the two first chip pads 131 and first panel pads 121. In the embodiments of the present disclosure, the operator does not need to measure the metal wire of the display panel through probes, improving the measurement convenience of the bonding resistance value R11.
Still referring to
The display panel includes the display region AA and the non-display region NA surrounding the display region AA. The non-display region NA in the embodiments of the present disclosure may include the first non-display region NA1 and the second non-display region NA2 opposite to each other along the second direction Y, where the second direction Y is parallel to the plane where the substrate 11 is located, and the second direction Y intersects the first direction X. In one or more embodiments, the first direction X and the second direction Y may be perpendicular to each other. The first non-display region NA1 is bonded to the driver chip 13 and the flexible circuit board 14. In the embodiments of the present disclosure, the driver chip 13 is the source driving chip and configured to receive control signals input from the flexible circuit board 14 and generate signals for driving the display panel. In the embodiments of the present disclosure, the first metal wire 12a and the second metal wire 12b between the driver chip 13 and the flexible circuit board 14 are linear. In the embodiments of the present disclosure, the test loops are disposed on the source driving chip so that the bonding resistance value of the source driving chip is accurately acquired. In one or more embodiments, the first metal wire 12a and the second metal wire 12b may be disposed in parallel so that the first metal wire 12a and the second metal wire 12b have the same length and are located in the same environment, thereby reducing a difference between the resistance values of the first metal wire 12a and the second metal wire 12b in the display panel.
In the embodiments of the present disclosure, in addition to the first non-display region NA1 and the second non-display region NA2 opposite to each other along the second direction Y, the non-display region NA of the display panel includes the third non-display region NA3 and the fourth non-display region NA4 opposite to each other along the first direction X. The first non-display region NA1 is adjacent to the third non-display region NA3, the third non-display region NA3 is bonded to the driver chip 13 (a gate driving chip 61), the first non-display region NA1 is bonded to a source driving chip 62 and the flexible circuit board 14, and the first test loop and the second test loop disposed for the driver chip 13 and the flexible circuit board 14 are required to be provided with a relatively long first metal wire 12a and a relatively long second metal wire 12b, respectively. The first metal wire 12a and the second metal wire 12b may extend in the zigzag shape along edges of the display region AA. In the embodiments of the present disclosure, the test loops are disposed on the gate driving chip 61 so that the bonding resistance value of the source driving chip 62 is accurately acquired. In one or more embodiments, polyline segments of the first metal wire 12a and the second metal wire 12b may be disposed in parallel so that the first metal wire 12a and the second metal wire 12b have the same length and are located in the same environments, thereby reducing the difference between the resistance values of the first metal wire 12a and the second metal wire 12b in the display panel.
Still referring to
In the embodiments of the present disclosure, the driver circuit layer includes the multiple metal layers. When the first metal wire 12a and the second metal wire 12b are relatively long in length, as shown in
In the embodiments of the present disclosure, the first sub-metal wire 1211 and the fourth sub-metal wire 1214 are located in the same metal layer and are the same in material and thickness, making it convenient to control the first sub-metal wire 1211 and the fourth sub-metal wire 1214 to have the same resistance value; the second sub-metal wire 1212 and the fifth sub-metal wire 1215 are both located in the second metal layer 52 and are the same in material and thickness, making it convenient to control the second sub-metal wire 1212 and the fifth sub-metal wire 1215 to have the same resistance value; and similarly, the third sub-metal wire 1213 and the sixth sub-metal wire 1216 are disposed in the same layer to facilitate the same resistance value. In one or more embodiments, the first sub-metal wire 1211 and the fourth sub-metal wire 1214 may have the same wire width; the second sub-metal wire 1212 and the fifth sub-metal wire 1215 have the same wire width; and the third sub-metal wire 1213 and the sixth sub-metal wire 1216 have the same wire width. For example, if the first sub-metal wire 1211 and the fourth sub-metal wire 1214 are the same in the wire width, material, and film thickness, in the embodiments of the present disclosure, the first sub-metal wire 1211 and the fourth sub-metal wire 1214 may be controlled to have the same length to achieve the same resistance value of the first sub-metal wire 1211 and the fourth sub-metal wire 1214. Similarly, the second sub-metal wire 1212 and the fifth sub-metal wire 1215 have the same wire width, and the third sub-metal wire 1213 and the sixth sub-metal wire 1216 have the same wire width. In the embodiments of the present disclosure, although the first metal wire 12a and the second metal wire 12b are disposed in two metal layers, the sub-metal wires of the first metal wire 12a and the second metal wire 12b are disposed in one-to-one correspondence to ensure that the corresponding sub-metal wires have the same impedance so that when the bonding resistance value of the gate driving chip is tested through the test loops, the single variable can be effectively controlled, improving the measurement accuracy of the bonding resistance value.
Still referring to
To conclude, a design for detection of the IC bonding resistance value of the display device may be optimized in the embodiments of the present disclosure so that the actual bonding resistance value of a source IC (the source driving chip) or a gate IC (the gate driving chip) can be directly calculated according to the actually measured values, achieving a convenient and quick detection manner. Moreover, the occupation of the wiring space can be avoided as much as possible through vias or in a manner of wire wrapping, achieving the narrow bezel design of the display panel and improving user experience.
Based on the same concept, embodiments of the present disclosure further provide a test method for a display device.
In step S101, a first resistance value R1 of a first test loop in the display device is measured through a first test terminal and a second test terminal.
In step S102, a second resistance value R2 of a second test loop in the display device is measured through a third test terminal and a fourth test terminal.
In step S103, a bonding resistance value R11 of a first chip pad of a driver chip of the display device is acquired according to the first resistance value R1 and the second resistance value R2, where R11=(R1−R2)/2.
In the embodiments of the present disclosure, a display panel includes a substrate and a metal layer formed on the substrate, and the display device includes the display panel and the driver chip and a flexible circuit board bonded to the display panel. The metal layer forms panel pads, the driver chip includes the first chip pad, and the flexible circuit board includes circuit board pads. The first chip pad, a first panel pad, a first metal wire of the metal layer, a second panel pad, a first circuit board pad, a first internal wire of the flexible circuit board, a third circuit board pad, and a first control board pad are connected in sequence to form a first branch; a second metal wire of the metal layer, a third panel pad, a second circuit board pad, a second internal wire of the flexible circuit board, a fourth circuit board pad, and a second control board pad are connected in sequence to form a second branch; and two first branches form the first test loop, and two second branches form the second test loop. In the embodiments of the present disclosure, test terminals may be disposed so that the resistance value of the first test loop and the resistance value of the second test loop are tested, and the bonding resistance value of the first chip pad is acquired according to a difference between the resistance values of the two loops, avoiding a need for pricks with probes to estimate the bonding resistance value of the first chip pad according to a resistance value of the metal wire in the metal layer, omitting actual measurement inconvenient to operate, and avoiding the consumption of a lot of time and energy. Additionally, in the embodiments of the present disclosure, the bonding resistance value of the first chip pad is measured through the first test loop and the second test loop, effectively reducing an error caused by the actual measurement and improving the accuracy of the bonding resistance value of the chip pad.
Based on the preceding embodiment, that the first resistance value R1 of the first test loop in the display device is measured through the first test terminal and the second test terminal may include connecting a multimeter to the first test terminal and the second test terminal separately to acquire the first resistance value R1; and that the second resistance value R2 of the second test loop in the display device is measured through the third test terminal and the fourth test terminal includes connecting the multimeter to the third test terminal and the fourth test terminal separately to acquire the second resistance value R2. In the embodiments of the present disclosure, only the first test terminal, the second test terminal, the third test terminal, and the fourth test terminal are pricked through the multimeter so that the bonding resistance value of the chip pad can be directly acquired, avoiding a need to separately measure the metal wire in the display panel, saving a labor cost, improving the measurement convenience, preventing an error caused by the measurement of the metal wire by an operator through pricks with probes, and improving the measurement accuracy.
It is to be noted that the preceding are preferred embodiments of the present disclosure and technical principles used therein. It is to be understood by those skilled in the art that the present disclosure is not limited to the embodiments described herein. Those skilled in the art can make various apparent modifications, adaptations, and substitutions without departing from the scope of the present disclosure. Therefore, although the present disclosure has been described in detail through the preceding embodiments, the present disclosure is not limited to the preceding embodiments and may include other equivalent embodiments without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202411686634.7 | Nov 2024 | CN | national |
