Patent Application
20240127728
This application claims priority to Korean Patent Application No. 10-2022-0133987, filed on Oct. 18, 2022, and all the benefits accruing therefrom under 35 U.S.C. § 119, the content of which in its entirety is herein incorporated by reference.
Embodiments of the present invention relate to a display device, and more particularly to a display device including a test pixel.
In a display device, such as an organic light emitting diode (“OLED”) display device, each pixel includes a scan transistor that transfers a data voltage, a storage capacitor that stores the data voltage transferred by the scan transistor, a driving transistor that generates a driving current based on the data voltage stored in the storage capacitor, and a light emitting element that emits light based on the driving current generated by the driving transistor.
Even if pixels of the display device are manufactured by the same process, driving transistors of the pixels may have different threshold voltages. To compensate for the threshold voltage of the driving transistor, each pixel may perform an internal compensation operation that stores the threshold voltage of the driving transistor in the storage capacitor. However, even if each pixel performs the internal compensation operation, a change in a mobility characteristic of the driving transistor of each pixel may not be compensated.
Some embodiments provide a display device capable of sensing a mobility characteristic of a driving transistor by using a test pixel.
According to embodiments, there is provided a display device including a display panel including a normal pixel in a display region and a test pixel in a peripheral region, a sensing line coupled to the test pixel, and a sensing circuit configured to sense a mobility characteristic of the test pixel by measuring a current at a source node of the test pixel through the sensing line. The source node of the test pixel is electrically separated from the sensing line in a data writing period of a frame period, and is electrically coupled to the sensing line in an emission period of the frame period.
In embodiments, the normal pixel may include a light emitting element, and the test circuit may include a diode connection transistor instead of the light emitting element.
In embodiments, the normal pixel may include its own source node different from the source node of the test pixel, and each of the normal pixel and the test pixel may include a first transistor including a top gate coupled to a gate node, a drain, a source coupled to the source node, and a bottom gate, a second transistor configured to apply a data voltage to the gate node in response to a writing signal, a third transistor configured to apply a reference voltage to the gate node in response to a reference signal, a fourth transistor configured to apply an initialization voltage to the source node in response to an initialization signal, a fifth transistor configured to couple a first power supply voltage line to the drain of the first transistor in response to an emission signal, a storage capacitor including a first electrode coupled to the gate node, and a second electrode coupled to the source node, and a holding capacitor including a first electrode coupled to the first power supply voltage line, and a second electrode coupled to the source node and the bottom gate of the first transistor. The normal pixel may further include a light emitting element including an anode coupled to the source node, and a cathode coupled to a second power supply voltage line. The test pixel may further include at least one diode connection transistor coupled between the source node and a third power supply voltage line, and a sixth transistor configured to couple the source node to the sensing line in response to a sensing signal.
In embodiments, a third power supply voltage of the third power supply voltage line may have a voltage level substantially the same as a voltage level of a second power supply voltage of the second power supply voltage line in a non-emission period including the data writing period, and may have a voltage level substantially the same as a voltage level of a first power supply voltage of the first power supply voltage line in the emission period.
In embodiments, the at least one diode connection transistor may include a top gate coupled to the source node, a drain coupled to the source node, and a source coupled to the third power supply voltage line.
In embodiments, the at least one diode connection transistor may further include a bottom gate for receiving a bottom gate voltage.
In embodiments, the sixth transistor may include a gate for receiving the sensing signal, a drain coupled to the source node, and a source coupled to the sensing line.
In embodiments, the first through sixth transistors may be implemented with n-type metal oxide semiconductor (“NMOS”) transistors.
In embodiments, the frame period may include an initialization period in which the gate node and the source node are initialized, a compensation period in which a threshold voltage of the first transistor is compensated, the data writing period in which the data voltage is written to the gate node, and the emission period in which the light emitting element of the normal pixel emits light, and the mobility characteristic of the first transistor of the test pixel is sensed.
In embodiments, in the initialization period, the emission signal, the writing signal and the sensing signal may have a low level, the initialization signal and the reference signal may have a high level, the third transistor may be turned on in response to the reference signal having the high level to apply the reference voltage to the gate node, and the fourth transistor may be turned on in response to the initialization signal having the high level to apply the initialization voltage to the source node.
In embodiments, in the compensation period, the initialization signal, the writing signal and the sensing signal may have a low level, the emission signal and the reference signal may have a high level, the third transistor may be turned on in response to the reference signal having the high level to apply the reference voltage to the gate node, the fifth transistor may be turned on in response to the emission signal having the high level, and a voltage of the source node may be saturated to a voltage corresponding to a value obtained by subtracting the threshold voltage from the reference voltage.
In embodiments, in the data writing period, the emission signal, the initialization signal, the reference signal and the sensing signal may have a low level, the writing signal may have a high level, the second transistor may be turned on in response to the writing signal having the high level to apply the data voltage to the gate node, and the sixth transistor of the test pixel may be turned off in response to the sensing signal having the low level to electrically separate the source node of the test pixel from the sensing line.
In embodiments, in the emission period, the initialization signal, the reference signal and the writing signal may have a low level, the emission signal and the sensing signal may have a high level, in the normal pixel, the light emitting element may emit light based on a current generated by the first transistor, and, in the test pixel, the sixth transistor may be turned on in response to the sensing signal having the high level to electrically couple the source node to the sensing line such that a current generated by the first transistor is transferred to the sensing line through the source node and the sixth transistor.
In embodiments, the normal pixel may include its own source node different from the source node of the test pixel, and each of the normal pixel and the test pixel may include a first transistor including a top gate coupled to a gate node, a drain, a source coupled to the source node, and a bottom gate, a second transistor configured to apply a data voltage to the gate node in response to a writing signal, a third transistor configured to apply a reference voltage to the gate node in response to a reference signal, a fourth transistor including a gate for receiving an initialization signal, a drain coupled to the source node, and a source for receiving an initialization voltage, a fifth transistor configured to couple a first power supply voltage line to the drain of the first transistor in response to an emission signal, a storage capacitor including a first electrode coupled to the gate node, and a second electrode coupled to the source node, and a holding capacitor including a first electrode coupled to the first power supply voltage line, and a second electrode coupled to the source node and the bottom gate of the first transistor. The normal pixel may further include a light emitting element including an anode coupled to the source node, and a cathode coupled to a second power supply voltage line. The test pixel may further include at least one diode connection transistor coupled between the source node and a third power supply voltage line. The sensing line may be coupled to the source of the fourth transistor of the test pixel.
In embodiments, in the data writing period, the emission signal, the initialization signal and the reference signal may have a low level, the writing signal may have a high level, the second transistor may be turned on in response to the writing signal having the high level to apply the data voltage to the gate node, and the fourth transistor of the test pixel may be turned off in response to the initialization signal having the low level to electrically separate the source node of the test pixel from the sensing line.
In embodiments, in the emission period, the reference signal and the writing signal may have a low level, the emission signal may have a high level, the initialization signal for the normal pixel may have the low level, the initialization signal for the test pixel may have the high level, in the normal pixel, the light emitting element may emit light based on a current generated by the first transistor, and, in the test pixel, the fourth transistor may be turned on in response to the initialization signal having the high level to electrically couple the source node to the sensing line such that a current generated by the first transistor is transferred to the sensing line through the source node and the fourth transistor.
In embodiments, the sensing circuit may include an integrator configured to generate an output voltage by integrating a current transferred through the sensing line, and an analog-to-digital converter configured to generate sensing data by performing an analog-to-digital conversion operation on the output voltage of the integrator.
In embodiments, the integrator may include an amplifier including a first input terminal, a second input terminal, and an output terminal for outputting the output voltage, a first switch configured to couple the sensing line to the first input terminal of the amplifier in response to a sensing signal, a second switch configured to couple the first input terminal of the amplifier to the output terminal of the amplifier in response to a reset signal, and a capacitor coupled between the first input terminal of the amplifier and the output terminal of the amplifier.
In embodiments, the display device may further include a data driver configured to provide data voltages to the normal pixel and the test pixel, a scan driver configured to provide scan signals to the normal pixel and the test pixel, an emission driver configured to provide emission signals to the normal pixel and the test pixel, and a controller configured to control the data driver, the scan driver and the emission driver. The controller may receive sensing data representing the mobility characteristic of the test pixel from the sensing circuit, and may correct image data for the normal pixel based on the sensing data.
According to embodiments, there is provided a display device including a display panel including a normal pixel in a display region and a test pixel in a peripheral region, a sensing line coupled to the test pixel, and a sensing circuit configured to sense a mobility characteristic of the test pixel through the sensing line. Each of the normal pixel and the test pixel includes a first transistor including a top gate coupled to a gate node, a drain, a source coupled to a source node, and a bottom gate, a second transistor configured to apply a data voltage to the gate node in response to a writing signal, a third transistor configured to apply a reference voltage to the gate node in response to a reference signal, a fourth transistor configured to apply an initialization voltage to the source node in response to an initialization signal, a fifth transistor configured to couple a first power supply voltage line to the drain of the first transistor in response to an emission signal, a storage capacitor including a first electrode coupled to the gate node, and a second electrode coupled to the source node, and a holding capacitor including a first electrode coupled to the first power supply voltage line, and a second electrode coupled to the source node and the bottom gate of the first transistor. The normal pixel further includes a light emitting element including an anode coupled to the source node, and a cathode coupled to a second power supply voltage line. The test pixel further includes at least one diode connection transistor coupled between the source node and a third power supply voltage line, and a sixth transistor configured to couple the source node to the sensing line in response to a sensing signal.
In embodiments, in a data writing period of a frame period, the sixth transistor of the test pixel may be turned off in response to the sensing signal having a low level to electrically separate the source node of the test pixel from the sensing line. In an emission period of the frame period, the sixth transistor of the test pixel may be turned on in response to the sensing signal having a high level to electrically couple the source node to the sensing line such that a current generated by the first transistor of the test pixel is transferred to the sensing line through the source node of the test pixel and the sixth transistor of the test pixel.
According to embodiments, there is provided a display device including a display panel including a normal pixel in a display region and a test pixel in a peripheral region, a sensing line coupled to the test pixel, and a sensing circuit configured to sense a mobility characteristic of the test pixel through the sensing line. Each of the normal pixel and the test pixel includes a first transistor including a top gate coupled to a gate node, a drain, a source coupled to a source node, and a bottom gate, a second transistor configured to apply a data voltage to the gate node in response to a writing signal, a third transistor configured to apply a reference voltage to the gate node in response to a reference signal, a fourth transistor including a gate for receiving an initialization signal, a drain coupled to the source node, and a source for receiving an initialization voltage, a fifth transistor configured to couple a first power supply voltage line to the drain of the first transistor in response to an emission signal, a storage capacitor including a first electrode coupled to the gate node, and a second electrode coupled to the source node, and a holding capacitor including a first electrode coupled to the first power supply voltage line, and a second electrode coupled to the source node and the bottom gate of the first transistor. The normal pixel further includes a light emitting element including an anode coupled to the source node, and a cathode coupled to a second power supply voltage line. The test pixel further includes at least one diode connection transistor coupled between the source node and a third power supply voltage line. The sensing line is coupled to the source of the fourth transistor of the test pixel.
In embodiments, in a data writing period of a frame period, the fourth transistor of the test pixel may be turned off in response to the initialization signal having a low level to electrically separate the source node of the test pixel from the sensing line. In an emission period of the frame period, the fourth transistor of the test pixel may be turned on in response to the initialization signal having a high level to electrically couple the source node to the sensing line such that a current generated by the first transistor of the test pixel is transferred to the sensing line through the source node of the test pixel and the fourth transistor of the test pixel.
As described above, in a display device according to embodiments, a display panel may include a test pixel coupled to a sensing line in a peripheral region, and a sensing circuit may sense a mobility characteristic of the test pixel by measuring a current at a source node of the test pixel through the sensing line. Accordingly, image data for a normal pixel may be corrected based on the mobility characteristic sensed using the test pixel, and thus a change in the mobility characteristic may be compensated.
Further, in the display device according to embodiments, the source node of the test pixel may be electrically separated from the sensing line in a data writing period, and may be electrically coupled to the sensing line in an emission period. Accordingly, a sensing data voltage of the test pixel may not be distorted by a parasitic capacitor of the sensing line.
Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.
It will be understood that, although the terms “first,” “second,” “third” etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, “a first element,” “component,” “region,” “layer” or “section” discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, “a”, “an,” “the,” and “at least one” do not denote a limitation of quantity, and are intended to include both the singular and plural, unless the context clearly indicates otherwise. For example, “an element” has the same meaning as “at least one element,” unless the context clearly indicates otherwise. “At least one” is not to be construed as limiting “a” or “an.” “Or” means “and/or.” As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms “comprises” and/or “comprising,” or “includes” and/or “including” when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and/or groups thereof.
“Substantially the same as”, “About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10% or 5% of the stated value. Hereinafter, embodiments of the present invention will be explained in detail with reference to the accompanying drawings.
Referring to
The display panel 110 may have a display region DR at which an image is displayed, and a peripheral region PR adjacent to the display region DR. The display panel 110 may include a plurality of normal pixels NPX arranged in a matrix form having a plurality of rows and a plurality of columns in the display region DR, and may further include at least one test pixel TPX in the peripheral region PR. For example, the display panel 110 may include, but not limited to, one, two, four, eight, twelve or sixteen test pixels TPX in the peripheral region.
In some embodiments, as illustrated in
The display panel 110 may include one or more sensing lines SL coupled to one or more test pixels TPX, respectively. For example, when the display panel 110 includes sixteen test pixels TPX, the display panel 110 may include sixteen sensing lines SL coupled to the sixteen test pixels TPX, respectively. Further, as illustrated in
The sensing circuit 170 may sense the mobility characteristic of the test pixel TPX by measuring a current IDR2 at a source node NS of the test pixel TPX through the sensing line SL. For example, the sensing circuit 170 may sense the mobility characteristic of a first transistor T1 (or a driving transistor) of the test pixel TPX by measuring the current IDR2 generated by the first transistor T1 of the test pixel TPX through the sensing line SL. In some embodiments, the sensing circuit 170 may be implemented as an integrated circuit, and the integrated circuit of the sensing circuit 170 may be mounted on the source board 180. For example, this integrated circuit of the sensing circuit 170 may be referred to as a read-out integrated circuit (“ROIC”). In other embodiments, the sensing circuit 170 may be implemented as a single integrated circuit together with the data driver 130 and/or the controller 160.
The data driver 130 may generate data voltages DV based on output image data ODAT and a data control signal DCTRL received from the controller 160, and may provide the data voltages DV to the normal pixels NPX through first data lines. Further, the data driver 130 may provide, as the data voltage DV, a sensing data voltage SDV corresponding to a sensing gray level to the test pixel TPX through a second data line DL2. In some embodiments, the sensing gray level may be a predetermined constant gray level, or a variable gray level that is changed at regular intervals. For example, the sensing gray level may be, but not be limited to, a 0-gray level, a 57-gray level, a 255-gray level, etc. Further, in some embodiments, the second data line for the test pixel TPX may be different from the first data lines for the normal pixels NPX. In other embodiments, the second data line may be a portion of the first data lines. In some embodiments, the data driver 130 may be implemented as one or more integrated circuits. Further, in some embodiments, as illustrated in
The scan driver 150 may generate the scan signals SC based on a scan control signal SCTRL received from the controller 160, and may provide the scan signals SC to the normal pixels NPX and the one or more test pixels TPX. In some embodiments, the scan driver 150 may sequentially provide the scan signals SC to the normal pixels NPX and the one or more test pixels TPX on a pixel row basis through a plurality of scan lines. For example, the display panel 110 may include the normal pixels NPX in N rows and the one or more test pixels TPX in one row, where N is an integer greater than 1, and may further include first through N-th scan lines (or first through N-th scan line sets) coupled to the N rows of the normal pixels NPX, respectively, and an (N+1)-th scan line (or an (N+1)-th scan line set) coupled to the one row of the test pixels TPX. In this case, the scan driver 150 may sequentially provide the scan signals SS to the N rows of the normal pixels NPX on the pixel row basis through the first through N-th scan lines, and then (e.g., after one horizontal time from a time point at which the scan signal SS is output to the N-th scan line) may provide the scan signal SS to the test pixels TPX through the (N+1)-th scan line. However, the order in which the scan signal SS is applied to the test pixels TPX is not limited to the above example. Further, in some embodiments, the scan signal SS may include, but not limited to, a reference signal GR, an initialization signal GI and a writing signal GW. In some embodiments, the scan control signal SCTRL may include, but not limited to, a scan start signal and a scan clock signal. In some embodiments, as illustrated in
The emission driver 140 may generate the emission signals EM based on an emission control signal EMCTRL received from the controller 160, and may provide the emission signals EM to the normal pixels NPX and the one or more test pixels TPX. In some embodiments, the emission driver 140 may sequentially provide the emission signals EM to the normal pixels NPX and the one or more test pixels TPX on a pixel row basis through a plurality of emission lines. For example, the display panel 110 may include the normal pixels NPX in N rows and the one or more test pixels TPX in one row, and may further include first through N-th emission lines coupled to the N rows of the normal pixels NPX, respectively, and an (N+1)-th emission line coupled to the one row of the test pixels TPX. In this case, the emission driver 140 may sequentially provide the emission signals EM to the N rows of the normal pixels NPX on the pixel row basis through the first through N-th emission lines, and then (e.g., after one horizontal time from a time point at which the emission signal EM is output to the N-th emission line) may provide the emission signal EM to the test pixels TPX through the (N+1)-th emission line. However, the order in which the emission signal EM is applied to the test pixels TPX is not limited to the above example. Further, in some embodiments, the emission control signal EMCTRL may include, but not limited to, an emission start signal and an emission clock signal. In some embodiments, as illustrated in
The controller 160 (e.g., a timing controller (“TCON”)) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (“GPU”), an application processor (“AP”) or a graphics card). In some embodiments, the control signal CTRL may include, but not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. Further, in some embodiments, the controller 160 may receive sensing data SD representing the mobility characteristic of the test pixel TPX from the sensing circuit 170, and may generate the output image data ODAT by correcting the input image data IDAT for the normal pixels NPX based on the sensing data SD. Thus, by using the mobility characteristic of the first transistor T1 (or the driving transistor) of the test pixel TPX, the data voltage DV where the mobility characteristic of the first transistor T1 (or the driving transistor) is compensated may be provided to the normal pixel NPX. Further, the controller 160 may generate the data control signal DCTRL, the scan control signal SCTRL and the emission control signal EMCTRL based on the control signal CTRL. The controller 160 may control an operation of the data driver 130 by providing the output image data ODAT and the data control signal DCTRL to the data driver 130, may control an operation of the scan driver 150 by providing the scan control signal SCTRL to the scan driver 150, and may control an operation of the emission driver 140 by providing the emission control signal EMCTRL to the emission driver 140.
In the display device 100 according to embodiments, each normal pixel NPX may perform a compensation operation or an internal compensation operation that stores a threshold voltage of the first transistor T1 (or the driving transistor) in a storage capacitor CST (See
To compensate for this change in the mobility characteristic of the first transistor T1, in the display device 100 according to embodiments, the sensing circuit 170 may generate the sensing data SD representing the mobility characteristic of the first transistor T1 by measuring the current IDR2 at the source node NS of the test pixel TPX, or the current IDR2 of the first transistor T1 of the test pixel TPX through the sensing line SL, the controller 160 may generate the output image data ODAT by correcting the input image data IDAT based on the sensing data SD, and the data driver 130 may provide the data voltages DV corresponding to the output image data ODAT to the normal pixels NPX. That is, the data voltage DV where the mobility characteristic of the first transistor T1 (or the driving transistor) is compensated may be provided to the normal pixel NPX, and the normal pixel NPX may emit light with the desired luminance. However, when the sensing data voltage SDV is written to the test pixel TPX, the sensing data voltage SDV may be distorted by the parasitic capacitor CP of the sensing line SL, the current IDR2 of the first transistor T1 of the test pixel TPX may be distorted based on the distorted sensing data voltage SDV, and thus the sensing data SD may be inaccurate.
In order to prevent the distortion of the sensing data voltage SDV of the test pixel TPX caused by the parasitic capacitor CP of the sensing line SL, in the display device 100 according to embodiments, the source node NS of the test pixel TPX may be electrically separated or spaced apart from the sensing line SL in a data writing period of a frame period. In some embodiment, a sixth transistor T6 of the test pixel TPX may electrically separate the source node NS from the sensing line SL in the data writing period in response to a sensing signal. In other embodiments, a fourth transistor T4 (or an initialization transistor) of the test pixel TPX may electrically separate the source node NS from the sensing line SL in the data writing period in response to an initialization signal. Further, in an emission period of the frame period, the light emitting element EL of the normal pixel NPX may emit light based on the current IDR1 of the first transistor T1, the current IDR2 generated by the first transistor T1 of the test pixel TPX may be transferred to the sensing line SL through the source node NS and the fourth or sixth transistor T4/T6, and the sensing circuit 170 may generate the sensing data SD by measuring the current IDR2 of the first transistor T1 of the test pixel TPX through the sensing line SL. Since the source node NS of the test pixel TPX is electrically separated from the sensing line SL in the data writing period, the sensing data voltage SDV may not be distorted, the current IDR2 of the first transistor of the test pixel TPX may not be distorted, accurate sensing data SD may be generated, and the mobility characteristic change of the first transistor T1 may be accurately compensated.
As described above, in the display device 100 according to embodiments, the display panel 110 may include the test pixel TPX coupled to the sensing line SL in the peripheral region PR, and the sensing circuit 170 may sense the mobility characteristic of the test pixel TPX by measuring the current IDR2 at the source node NS of the test pixel TPX through the sensing line SL. Accordingly, image data (or the input image data IDAT) for the normal pixel NPX may be corrected based on the mobility characteristic sensed using the test pixel TPX, and thus the mobility characteristic change may be compensated. Further, the source node NS of the test pixel TPX may be electrically separated from the sensing line SL in the data writing period, and may be electrically coupled to the sensing line SL in the emission period. Accordingly, the sensing data voltage SDV of the test pixel TPX may not be distorted by the parasitic capacitor CP of the sensing line SL, and the mobility characteristic change of the first transistor T1 may be accurately compensated.
Referring to
The first transistor T1 may generate a current (e.g., a driving current) based on a voltage between a gate node NG and a source node NS, or a voltage stored in the storage capacitor CST. The first transistor T1 may be referred to as a driving transistor for generating the driving current. In some embodiments, the first transistor T1 may include a top gate coupled to the gate node NG, a drain coupled to the fifth transistor T5, a source coupled to the source node NS, and a bottom gate coupled to the holding capacitor CHOLD and the source node NS. Thus, the first transistor T1 may have a dual gate structure including the top gate and the bottom gate. In some embodiments, the bottom gate of the first transistor T1 may be referred to as a bottom metal layer. Since the first transistor T1 includes the bottom gate, and the bottom gate may be maintained to have a substantially constant voltage by the holding capacitor CHOLD, a driving characteristic of the first transistor T1 may be improved. For example, a current of the first transistor T1 according to a drain-source voltage of the first transistor T1 may be substantially flat or uniform.
The second transistor T2 may apply a data voltage of a data line DL1 and DL2 to the gate node NG in response to a writing signal GW. For example, the second transistor T2 of the normal pixel NPX may apply the data voltage of a first data line DL1 to the gate node NG in response to the writing signal GW, and the second transistor T2 of the test pixel TPXa may apply the data voltage of a second data line DL2 to the gate node NG in response to the writing signal GW. The second transistor T2 may be referred to as a scan transistor for transferring the data voltage of the data line DL1 and DL2. In some embodiments, the second transistor T2 may include a gate for receiving the writing signal GW, a drain coupled to the data line DL1 and DL2, and a source coupled to the gate node NG.
The third transistor T3 may apply a reference voltage VREF to the gate node NG in response to a reference signal GR. The third transistor T3 may be referred to as a reference transistor or a reset transistor for applying the reference voltage VREF to the gate node NG. In some embodiments, the third transistor T3 may include a gate for receiving the reference signal GR, a drain coupled to a line of the reference voltage VREF, and a source coupled to the gate node NG.
The fourth transistor T4 may apply an initialization voltage VINT to the source node NS in response to an initialization signal GI. The fourth transistor T4 may be referred to as an initialization transistor for initializing the source node NS. In some embodiments, the fourth transistor T4 may include a gate for receiving the initialization signal GI, a drain coupled to the source node NS, and a source coupled to a line of the initialization voltage VINT.
The fifth transistor T5 may couple a first power supply voltage line ELVDDL to the drain of the first transistor T1 in response to an emission signal EM. In some embodiments, the first power supply voltage line ELVDDL may be a high power supply voltage line, and a first power supply voltage ELVDD transferred through the first power supply voltage line ELVDDL may be a high power supply voltage. Further, the fifth transistor T5 may be referred to as an emission transistor for generating a path of the current of the first transistor T1 from the first power supply voltage line ELVDDL. In some embodiments, the fifth transistor T5 may include a gate for receiving the emission signal EM, a drain coupled to the first power supply voltage line ELVDDL, and a source coupled to the drain of the first transistor T1.
The storage capacitor CST may store the data voltage transferred through the second transistor T2 from the data line DL1 and DL2. The storage capacitor CST may be coupled between the gate node NG and the source node NS. In some embodiments, the storage capacitor CST may include a first electrode coupled to the gate node NG, and a second electrode coupled to the source node NS.
The holding capacitor CHOLD may be a capacitor for holding a voltage of the source node NS. The holding capacitor CHOLD may be coupled between the first power supply voltage line ELVDDL and the source node NS (and the bottom gate of the first transistor T1). In some embodiments, the holding capacitor CHOLD may include a first electrode coupled to the first power supply voltage line ELVDDL, and a second electrode coupled to the source node NS and the bottom gate of the first transistor T1.
The light emitting element EL of the normal pixel NPX may emit light based on the current generated by the first transistor T1. In some embodiments, the light emitting element EL may be, but not be limited to, an organic light emitting diode (OLED). In other embodiments, the light emitting element EL may be a nano light emitting diode (NED), a quantum dot (QD) light emitting diode, a micro light emitting diode, an inorganic light emitting diode, or any other suitable light emitting element. In some embodiments, the light emitting element EL may include an anode coupled to the source node NS, and a cathode coupled to a second power supply voltage line ELVSSL1. In some embodiments, the second power supply voltage line ELVSSL1 may be a low power supply voltage line, and a second power supply voltage ELVSS1 transferred through the second power supply voltage line ELVSSL1 may be a low power supply voltage.
The diode connection transistor DCT of the test pixel TPXa may be coupled between the source node NS and a third power supply voltage line ELVSSL2. The diode connection transistor DCT may simulate or mimic the light emitting element EL. For example, the diode connection transistor DCT may have a threshold voltage corresponding to a threshold voltage of the light emitting element EL. In some embodiments, the diode connection transistor DCT may include a top gate coupled to the source node NS, a drain coupled to the source node NS, and a source coupled to the third power supply voltage line ELVSSL2. Further, in some embodiments, the diode connection transistor DCT may have a dual gate structure, and may further include a bottom gate for receiving a bottom gate voltage VBML. Further, a voltage level of the bottom gate voltage VBML may be set such that the diode connection transistor DCT may have the threshold voltage corresponding to the threshold voltage of the light emitting element EL. In some embodiments, a third power supply voltage ELVSS2 of the third power supply voltage line ELVSSL2 may have a voltage level substantially the same as a voltage level of the second power supply voltage ELVSS1 of the second power supply voltage line ELVSSL1 in a non-emission period including a data writing period, and may have a voltage level substantially the same as a voltage level of the first power supply voltage ELVDD of the first power supply voltage line ELVDDL in an emission period. Accordingly, in the emission period, a current at the source node NS of the test pixel TPXa, or the current of the first transistor T1 of the test pixel TPXa may not flow through the diode connection transistor DCT to the third power supply voltage line ELVSSL2.
In some embodiments, as illustrated in
The sixth transistor T6 of the test pixel TPXa may couple the source node NS to the sensing line SL in response to a sensing signal SENSE. In some embodiments, the sensing signal SENSE may be generated by, but not limited to, the sensing circuit 170. In some embodiments, the sixth transistor T6 may be turned off in response to the sensing signal SENSE having a low level to electrically separate the source node NS from the sensing line SL, and may be turned on in response to the sensing signal SENSE having a high level to electrically couple the source node NS to the sensing line SL. Further, in some embodiments, the sixth transistor T6 may include a gate for receiving the sensing signal SENSE, a drain coupled to the source node NS, and a source coupled to the sensing line SL.
In some embodiments, as illustrated in
The integrator of the sensing circuit 170 may generate an output voltage by integrating a current transferred through the sensing line SL, and the analog-to-digital converter ADC of the sensing circuit 170 may generate sensing data SD by performing an analog-to-digital conversion operation on the output voltage of the integrator. In some embodiments, the integrator may include an amplifier AMP, a first switch SW1, a second switch SW2 and a capacitor C.
For example, the amplifier AMP may include a first input terminal (e.g., a negative input terminal), a second input terminal (e.g., a positive input terminal), and an output terminal for outputting the output voltage. In some embodiments, the second input terminal of the amplifier AMP may receive, but not limited to, the initialization voltage VINT. The first switch SW1 may couple the sensing line SL to the first input terminal of the amplifier AMP in response to the sensing signal SENSE. The second switch SW2 may couple the first input terminal of the amplifier AMP to the output terminal of the amplifier AMP in response to a reset signal RST. The capacitor C may be coupled between the first input terminal of the amplifier AMP and the output terminal of the amplifier AMP.
Hereinafter, an example of operations of the normal pixel NPX, the test pixel TPXa and the sensing circuit 170 will be described below with reference to
Referring to
In the initialization period IP, the gate node NG and the source node NS may be initialized. As illustrated in
In the compensation period CP, a threshold voltage of the first transistor T1 may be compensated. As illustrated in
In the data writing period WP, the data voltage DV of the data line DL1 and the sensing data voltage SDV of the data line DL2 may be written to the pixel NPX and the pixel TPXa, respectively. As illustrated in
In the emission period EP, the light emitting element EL of the normal pixel NPX may emit light, and a mobility characteristic of the first transistor T1 of the test pixel TPXa may be sensed. As illustrated in
As described above, the source node NS of the test pixel TPXa may be electrically separated by the sixth transistor T6 from the sensing line SL in the data writing period WP. Accordingly, the sensing data voltage SDV of the test pixel TPXa may not be distorted by the parasitic capacitor CP of the sensing line SL, and the mobility characteristic change of the first transistor T1 may be accurately compensated.
Referring to
The first transistor T1 may include a top gate coupled to a gate node NG, a drain, a source coupled to the source node NS, and a bottom gate. The second transistor T2 may apply a data voltage of a data line DL1 and DL2 to the gate node NG in response to a writing signal GW. The third transistor T3 may apply a reference voltage VREF to the gate node NG in response to a reference signal GR. The fourth transistor T4 may include a gate for receiving an initialization signal GI_NPX and GI_TPX, a drain coupled to the source node NS, and a source for receiving an initialization voltage VINT. The fifth transistor T5 may couple a first power supply voltage line ELVDDL to the drain of the first transistor T1 in response to an emission signal EM. The storage capacitor CST may include a first electrode coupled to the gate node NG, and a second electrode coupled to the source node NS. The holding capacitor CHOLD may include a first electrode coupled to the first power supply voltage line ELVDDL, and a second electrode coupled to the source node NS and the bottom gate of the first transistor T1. The light emitting element EL of the normal pixel NPX may include an anode coupled to the source node NS, and a cathode coupled to a second power supply voltage line ELVSSL1. The diode connection transistor DCT of the test pixel TPXb may be coupled between the source node NS and a third power supply voltage line ELVSSL2. In some embodiments, as illustrated in
The sensing line SL may be coupled to the source of the fourth transistor T4 of the test pixel TPXb. In some embodiments, similarly to an initialization signal GI illustrated in
Hereinafter, an example of operations of the normal pixel NPX, the test pixel TPXb and the sensing circuit 170 will be described below with reference to
Referring to
In the initialization period IP, the gate node NG and the source node NS may be initialized. In the compensation period CP, a threshold voltage of the first transistor T1 may be compensated.
In the data writing period WP, the data voltage DV of the data line DL1 may be written to the pixel NPX and the sensing data voltage SDV of the data line DL2 may be written to the pixel TPXb. As illustrated in
In the emission period EP, the light emitting element EL of the normal pixel NPX may emit light, and a mobility characteristic of the first transistor T1 of the test pixel TPXb may be sensed. As illustrated in
As described above, the source node NS of the test pixel TPXb may be electrically separated by the fourth transistor T4 from the sensing line SL in the data writing period WP. Accordingly, as the data voltage DV, the sensing data voltage SDV of the test pixel TPXb may not be distorted by the parasitic capacitor CP of the sensing line SL, and the mobility characteristic change of the first transistor T1 may be accurately compensated.
Referring to
The processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a micro processor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, in some embodiments, the processor 1110 may be further coupled to an extended bus such as a peripheral component interconnection (“PCI”) bus.
The memory device 1120 may store data for operations of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase change random access memory (“PRAM”) device, a resistance random access memory (“RRAM”) device, a nano floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc., and/or at least one volatile memory device such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile dynamic random access memory (mobile DRAM) device, etc.
The storage device 1130 may be a solid state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. The I/O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for operations of the electronic device 1100. The display device 1160 may be coupled to other components through the buses or other communication links.
In the display device 1160, a display panel may include a test pixel coupled to a sensing line in a peripheral region, and a sensing circuit may sense a mobility characteristic of the test pixel by measuring a current at a source node of the test pixel through the sensing line. Accordingly, image data for a normal pixel may be corrected based on the mobility characteristic sensed using the test pixel, and thus a change in the mobility characteristic may be compensated. Further, the source node of the test pixel may be electrically separated from the sensing line in a data writing period, and may be electrically coupled to the sensing line in an emission period. Accordingly, a data voltage (or a sensing data voltage) of the test pixel may not be distorted by a parasitic capacitor of the sensing line.
The inventions may be applied to any electronic device 1100 including the display device 1160. For example, the inventions may be applied to a television (“TV”), a digital TV, a 3D TV, a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a personal computer (“PC”), a home appliance, a laptop computer, a personal digital assistant (“PDA”), a portable multimedia player (“PMP”), a digital camera, a music player, a portable game console, a navigation device, etc.
The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the present invention. Accordingly, all such modifications are intended to be included within the scope of the present invention as defined in the claims. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2022-0133987 | Oct 2022 | KR | national |
