DISPLAY DEVICE, METHOD FOR DRIVING DISPLAY DEVICE, AND ELECTRONIC DEVICE

Abstract

A display device according to the present disclosure includes: a pixel array unit (30) in which pixel circuits (20A) are disposed in a matrix form, the pixel circuits each including a light emission unit (21), a write transistor (23) that writes a signal voltage (Vsig) of a video signal, a retention capacitor (24) that retains the signal voltage (Vsig) written by the write transistor (23), a drive transistor (22) that drives the light emission unit (21) on the basis of the signal voltage (Vsig) retained by the retention capacitor (24), and an auxiliary capacitor (25) of which one terminal is connected to a source node of the drive transistor (22); and a control unit (90) that provides a potential change to a source electrode of the drive transistor (22) by coupling through the auxiliary capacitor (25) to set an operation point of the drive transistor (22) as a cut-off region after the threshold value correction process.

Description

TECHNICAL FIELD

The present disclosure relates to a display device, a method for driving the display device, and an electronic device.

BACKGROUND ART

Recently, in the field of display devices, a flat panel type display device in which pixels (pixel circuits) including light emission units are 2-dimensionally disposed in a matrix form has become mainstream. In such a flat panel type display device, a characteristic of a transistor that drives a light emission unit may vary for each pixel due to a change in a process or the like. The characteristic variation of the transistor that drives the light emission unit affects light emitting luminance

Specifically, even if a video signal of the same level (signal voltage) is written into each pixel, the light emitting luminance varies between pixels. Thus, display unevenness occurs, and then uniformity of a display screen deteriorates. Accordingly, a function for correcting the display unevenness due to the characteristic variation of the driving transistor that drives the light emission unit or the like is provided in the display device. Further, the correction operation is performed during a period in which a write transistor that writes a video signal is in a conductive state. The correction period in which the correction operation is performed is determined by a capacitance value of a pixel capacitor (capacity pixel).

However, in display devices having the above-described correction function, there are cases in which it is necessary to shorten a correction period (correction time) as a source voltage of the drive transistor varies during the correction operation. The correction period is determined by a pulse width of a drive pulse that drives the write transistor. Accordingly, it is possible to shorten the correction period by shortening the pulse width of the drive pulse. Thus, in the related art, a pulse width adjustment circuit is formed on a display panel to generate a pulse signal of which a pulse width is shortened on the basis of a pulse signal input from the outside, and the pulse signal is used as the drive pulse (for example, see PTL 1).

CITATION LIST

Patent Literature

Patent Literature 1: JP 2012-255875A

SUMMARY OF INVENTION

Technical Problem

However, according to the related art technology disclosed in PTL 1, since it is necessary for the pulse width adjustment circuit that generates the drive pulse of which the pulse width is shortened to be formed on the display panel, a circuit size of peripheral circuits that drive the pixel circuit increases. As a result, since the area of a peripheral circuit region of a pixel array unit on the display panel on which the peripheral circuits are disposed, that is, a so-called frame region, is increased, which hinders miniaturization of the display panel.

The present disclosure aims to provide a display device in which a pulse width of a drive pulse does not need to be shortened and in which a circuit size of peripheral circuits of a pixel array is enabled to be reduced, a method for driving the display device, and an electronic device including the display device.

Solution to Problem

To achieve the above described aim, a display device according to the present disclosure includes:

a pixel array unit in which pixel circuits are disposed in a matrix form, the pixel circuits each including a light emission unit, a write transistor that writes a signal voltage of a video signal, a retention capacitor that retains the signal voltage written by the write transistor, a drive transistor that drives the light emission unit on the basis of the signal voltage retained by the retention capacitor, and an auxiliary capacitor of which one terminal is connected to a source node of the drive transistor, the pixel circuit having a function of a threshold value correction process of changing a source voltage of the drive transistor toward a voltage obtained by subtracting a threshold value voltage of the drive transistor from an initialization voltage of a gate voltage of the drive transistor with reference to the initialization voltage; and

a control unit that provides a potential change to a source electrode of the drive transistor by coupling through the auxiliary capacitor to set an operation point of the drive transistor as a cut-off region after the threshold value correction process.

In addition, to achieve the above described aim, an electronic device according to the present disclosure includes the display device having the above described configuration.

To achieve the above described aim, according to the present disclosure, a method for driving a display device including a pixel array unit in which pixel circuits are disposed in a matrix form, the pixel circuits each including a light emission unit, a write transistor that writes a signal voltage of a video signal, a retention capacitor that retains the signal voltage written by the write transistor, a drive transistor that drives the light emission unit on the basis of the signal voltage retained by the retention capacitor, and an auxiliary capacitor of which one terminal is connected to a source node of the drive transistor, the pixel circuit having a function of a threshold value correction process of changing a source voltage of the drive transistor toward a voltage obtained by subtracting a threshold value voltage of the drive transistor from an initialization voltage of a gate voltage of the drive transistor with reference to the initialization voltage, includes

providing a potential change to a source electrode of the drive transistor by coupling through the auxiliary capacitor to set an operation point of the drive transistor as a cut-off region after the threshold value correction process, when driving the display device.

In the display device, the method for driving the display device and the electronic device having the above-described configurations, when the signal voltage is written by the write transistor, since the operation point of the drive transistor is the cut-off region, it is natural for a current not to flow into the drive transistor. Thus, it is possible to remove a factor that causes the source voltage of the drive transistor to fluctuate other than the coupling associated with the writing of the signal voltage. Accordingly, it is not necessary to shorten a correction period (correction time), and thus it is not necessary to narrow a pulse width of the drive pulse.

ADVANTAGEOUS EFFECTS OF INVENTION

According to the present disclosure, it is not necessary to shorten a pulse width of a drive pulse, and thus it is possible to reduce a circuit size of peripheral circuits of a pixel array.

Note that the present disclosure is not limited to exhibiting the effect described herein at all and may exhibit any effect described in the present specification. In addition, the effects described in the present specification are not limiting but are merely examples, and there may be additional effects.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a system configuration diagram showing an overview of a basic configuration of an active-matrix organic EL display device which is a premise of the present disclosure.

FIG. 2 is a circuit diagram showing a circuit configuration of a 2Tr2C unit pixel (pixel circuit).

FIG. 3 is a timing waveform diagram for describing a basic circuit operation in an ideal state of the active-matrix organic EL display device which is the premise of the present disclosure.

FIG. 4 is a waveform diagram illustrating a mobility correction operation, in which FIG. 4A shows an operation example in a case in which current supply capability of a drive transistor is large and a capacitance value of a pixel capacitor is small, and FIG. 4B shows an operation example of a case in which a mobility correction time is shortened.

FIG. 5 is a circuit diagram illustrating a configuration example of a pulse width adjustment circuit in a peripheral circuit of a pixel array unit.

FIG. 6 is a timing waveform diagram illustrating waveforms of signals of respective units in FIG. 5.

FIG. 7 is a system configuration diagram illustrating an overview of a configuration of an organic EL display device including pixel circuits according to Example 1.

FIG. 8 is a timing waveform diagram for describing a circuit operation of the organic EL display device including the pixel circuits according to Example 1.

FIG. 9 is a system configuration diagram illustrating an overview of a configuration of an organic EL display device including pixel circuits according to Example 2.

FIG. 10 is a timing waveform diagram for illustrating a circuit operation of the organic EL display device including the pixel circuits according to Example 2.

FIG. 11 is an external view of a lens interchangeable single lens reflex type digital camera, in which FIG. 11A is a front view thereof and FIG. 11B is a back view thereof.

FIG. 12 is an external view of a head mounted display.

MODE(S) FOR CARRYING OUT THE INVENTION

Hereinafter, preferred embodiments for implementing the technology of the present disclosure (which will be described hereinafter as “embodiments”) will be described in detail with reference to the appended drawings. The technology of the present disclosure is not limited to the embodiments, and the various numeric values and materials shown in the embodiments are examples. In description provided below, structural elements that have substantially the same function and structure are denoted with the same reference numerals, and repeated explanation of these structural elements is omitted. Note that description will be provided in the following order.

1. Overall description of display device, method of driving display device, and electronic device of present disclosure2. Display device which is premise of present disclosure2-1. System configuration2-2. Pixel circuit

2-3. Basic circuit operation in ideal state

2-4. Shortening of mobility correction time2-5. Pulse width adjustment circuit3. Display device according to embodiments of present disclosure3-1. Example 1 (example in which pixel circuit is configured by N-channel type transistor)3-2. Example 2 (example in which pixel circuit is configured by P-channel type transistor)4. Electronic device4-1. Specific example 1 (example of digital camera)4-2. Specific example 2 (example of head mounted display)

Overall Description of Display Device, Method for Driving Display Device, and Electronic Device of Present Disclosure

In a display device, a method for driving the display device and an electronic device of the present disclosure, a configuration in which a control unit changes a potential of the source electrode of a drive transistor by providing a potential change to the other terminal of an auxiliary capacitor may be used. Further, when the other terminal of the auxiliary capacitor is connected to a control line, a configuration in which the control unit provides the potential change to the source electrode of the drive transistor by switching a control signal provided to the other terminal of the auxiliary capacitor through the control line from a non-active state to an active state may be used.

In the display device, the method for driving the display device and the electronic device of the present disclosure having the above-described preferable configurations, a configuration in which the source voltage of the drive transistor when the potential change is provided to the source electrode of the drive transistor is a voltage smaller than at least the sum of a cathode voltage of the light emission unit and a threshold value voltage of the light emission unit may be used. Further, a configuration in which the write transistor writes a signal voltage into the gate electrode of the drive transistor after the potential change is provided to the source electrode of the drive transistor may be used.

Further, in the display device, the method for driving the display device and the electronic device of the present disclosure having the above-described preferable configurations, a configuration including a write scanning unit that drives the write transistor through a scanning line in units of rows may be used. Here, it is preferable that the control unit and the write scanning unit be provided in a peripheral circuit region on the same side with respect to the pixel array unit. Further, it is preferable that the control line and the scanning line be formed of the same wire materials and to have the same thicknesses and widths.

Alternatively, in the display device, the method for driving the display device and the electronic device of the present disclosure having the above-described preferable configurations, a configuration in which, when entering an active state two times during the threshold value correction processing and the writing of the signal voltage, pulse widths of two pulses when the write scanning signal enters the active state two times are the same may be used. Further, a configuration in which the pixel circuit performs a mobility correction process in a period of the second pulse among the two pulses may be used. The mobility correction process is a process of correcting a mobility of the drive transistor by applying negative feedback to a potential difference between the gate electrode and the source electrode of the drive transistor by a correction amount corresponding to a current flowing in the drive transistor.

Display Device Which is Premise of Present Disclosure

System Configuration

FIG. 1 is a system configuration diagram showing an overview of a basic configuration of an active-matrix organic EL display device which is a premise of the present disclosure.

The active-matrix display device is a display device in which driving of a light emission unit (light emission element) is performed by an active element provided in the same pixel as the light emission unit, for example, an insulated gate field-effect transistor. Typically, a thin film transistor (TFT) can be used as the insulated gate field-effect transistor.

Here, a case in which an active-matrix organic EL display device uses an organic EL element as a light emission unit (light emission element) of a unit pixel (pixel circuit) will be described as an example. The organic El element is a current-driven electro-optical element of which light emission luminance changes in accordance with to a value of a current flowing through the device. Hereinafter, the “unit pixel/pixel circuit” is described simply as a “pixel” in some cases. The thin film transistor is used not only for control of a pixel but also for control of a peripheral circuit to be described below.

As shown in FIG. 1, an active-matrix organic EL display device 10 which is a premise of the present disclosure is configured to include a pixel array unit 30 constituted such that a plurality of unit pixels 20 are disposed 2-dimensionally in a matrix form (matrix state), and a driving unit (peripheral circuit) disposed in a peripheral region of the pixel array unit 30 and driving the pixels 20. The driving unit is constituted by, for example, a write scanning unit 40, a power supply scanning unit 50, and a signal output unit 60 and drives the pixels 20 of the pixel array unit 30.

In this example, the write scanning unit 40, the power supply scanning unit 50, and the signal output unit 60 are mounted on the same substrate as the pixel array unit 30, that is, on a display panel 70, as peripheral circuits of the pixel array unit 30. However, a configuration in which some or all of the write scanning unit 40, the power supply scanning unit 50, and the signal output unit 60 are provided outside the display panel 70 may be employed. Further, a configuration in which the write scanning unit 40 and the power supply scanning unit 50 are both disposed on one side of the pixel array unit 30 is used, or a configuration in which the write scanning unit 40 and the power supply scanning unit 50 are disposed with the pixel array unit 30 interposed therebetween may be used. As a substrate of the display panel 70, a transparent insulating substrate such as a glass substrate may be used, or a semiconductor substrate such as a silicon substrate may be used.

Here, when the organic EL display device 10 performs color display, one pixel (unit pixel) serving as a unit when forming a color image is constituted by sub pixels in a plurality of colors. In this case, each of the sub pixels corresponds to a pixel 20 of FIG. 1. To be more specific, in the display device that performs color display, one pixel is constituted by, for example, three sub pixels including a sub pixel emitting red (R) light, a sub pixel emitting green (G) light, and a sub pixel emitting blue (B) light.

One pixel, however, is not limited to a combination of sub pixels having three primary colors including RGB, and it is also possible to add sub pixels having one or more colors to the sub pixels having the three primary colors to form one pixel. To be more specific, it is possible to form one pixel by adding a sub pixel that emits white (W) light to increase luminance, or to form one pixel by adding at least one sub pixel which emits a complementary color of light to expand a color reproduction range.

In the pixel array unit 30, scanning lines 31 (31₁ to 31_m) and power supply lines 32 (32₁ to 32_m) are wired for each pixel row in the row direction (pixel array direction of pixel rows or horizontal direction) in the array of the pixels 20 in m rows and n columns. Furthermore, signal lines 33 (33₁ to 33_n) are wired for each pixel column in the column direction (pixel array direction of pixel columns or vertical direction) in the array of the pixels 20 in m rows and n columns.

The scanning lines 31₁ to 31_m are connected to respective output terminals of the corresponding rows of the write scanning unit 40. The power supply lines 32₁ to 32_m are connected to respective output terminals of the corresponding rows of the power supply scanning unit 50. The signal lines 33₁ to 33_n are connected to output terminals of the corresponding columns of the signal output unit 60.

The write scanning unit 40 is constituted by a shift register circuit, and the like. At the time of writing a signal voltage of a video signal onto each pixel 20 of the pixel array unit 30, the write scanning unit 40 performs so-called line sequential scanning in which each of the pixels 20 of the pixel array unit 30 is sequentially scanned in units of rows by sequentially supplying write scanning signals WS (WS₁ to WS_m) to the scanning lines 31 (31₁ to 31_m).

The power supply scanning unit 50 is constituted by a shift register circuit and the like, like the write scanning unit 40. The power supply scanning unit 50 supplies power supply voltages DS (DS₁ to DS_m) that can be switched between a first power supply voltage V_ccp and a second power supply voltage V_ini that is lower than the first power supply voltage V_ccp to the power supply lines 32 (32₁ to 32_m) in synchronization with the line sequential scanning performed by the write scanning unit 40. As will be described later, light emission and non-light emission (light-off) of the pixels 20 are controlled by the switching of the power supply voltages DS between V_ccp and V_ini.

The signal output unit 60 selectively outputs a signal voltage of a video signal (which may be described hereinafter simply as a “signal voltage”) V_sig that is based on luminance information supplied from a signal supply source (not shown) and a reference voltage V_ofs. Herein, the reference voltage V_ofs is a voltage serving as a reference of the signal voltage of the video signal V_sig (for example, a voltage equivalent to a black level of the video signal), and is used in a threshold value correction process to be described later.

The signal voltage V_sig and the reference voltage V_ofs output from the signal output unit 60 are written into each of the pixels 20 of the pixel array unit 30 via the signal lines 33 (33₁ to 33_n) in units of pixel rows selected through scanning performed by the write scanning unit 40. In other words, the signal output unit 60 employs a driving form of line sequential writing in which the signal voltage V_sig is written in units of rows (lines).

Pixel Circuit

FIG. 2 is a circuit diagram showing an example of a detailed circuit configuration of a unit pixel (pixel circuit) 20. The light emission unit of the pixel 20 is constituted by an organic EL element 21 that is an example of a current-driven electro-optical element of which light emission luminance changes in accordance with a value of a current flowing through the device.

As shown in FIG. 2, the pixel 20 includes the organic EL element 21 and a drive circuit that drives the organic EL element 21 by applying a current to the organic EL element 21. The cathode electrode of the organic EL element 21 is connected to a common power supply line 34 that is commonly wired for all of the pixels 20.

The drive circuit that drives the organic EL element 21 has a 2Tr2C circuit configuration including a drive transistor 22, a writing transistor 23, a retention capacitor 24, and an auxiliary capacitor 25, that is, two transistors (Tr) and two capacitative elements (C). Here, N-channel type thin film transistors (TFTs) are used as the drive transistor 22 and the writing transistor 23. Here, a conductive combination of the drive transistor 22 and the writing transistor 23 mentioned here is merely an example, but the present disclosure is not limited to this combination.

One electrode (the source or drain electrode) of the drive transistor 22 is connected to each of the power supply lines 32 (32₁ to 32_m) and the other electrode (the source or drain electrode) thereof is connected to the anode electrode of the organic EL element 21. One electrode (the source or drain electrode) of the writing transistor 23 is connected to each of the signal lines 33 (33₁ to 33_n) and the other electrode (the source or the drain electrode) thereof is connected to the gate electrode of the drive transistor 22. In addition, the gate electrode of the writing transistor 23 is connected to each of the scanning lines 31 (31₁ to 31_m).

With regard to the drive transistor 22 and the writing transistor 23, one electrode refers to a metal wire electrically connected to one source or drain region, and the other electrode refers to a metal wire electrically connected to the other source or drain region. In addition, one electrode may be a source electrode or a drain electrode, and the other electrode may be a drain electrode or a source electrode in accordance with the electric potential relation between the one electrode and the other electrode.

One electrode of the retention capacitor 24 is connected to the gate electrode of the drive transistor 22, and the other electrode thereof is connected to the other electrode of the drive transistor 22 and to the anode electrode of the organic EL element 21. One electrode of the auxiliary capacitor 25 is connected to the anode electrode of the organic EL element 21 and the other electrode thereof is connected to the cathode electrode of the organic EL element 21. That is, the auxiliary capacitor 25 is connected in parallel to the organic EL element 21.

In the configuration described above, the writing transistor 23 enters a conductive state in which a state of a high voltage applied to the gate electrode thereof through the scanning line 31 from the write scanning unit 40 becomes an active state in response to the write scanning signal WS. Accordingly, the writing transistor 23 performs sampling on the signal voltage of the video signal V_sig or the reference voltage V_ofs according to luminance information supplied from the signal output unit 60 through the signal line 33 at different time points and writes the voltages into the pixel 20. The signal voltage V_sig or the reference voltage V_ofs written by the writing transistor 23 are retained by the retention capacitor 24.

When the power supply voltage DS of the power supply lines 32 (32₁ to 32_m) becomes the first power supply voltage V_ccp, the drive transistor 22 operates in a saturation region as one electrode thereof serves as the drain electrode and the other electrode serves as the source electrode. Accordingly, the drive transistor 22 receives supply of a current from the power supply line 32 and then drives the organic EL element 21 to emit light through current driving. To be more specific, the drive transistor 22 supplies the driving current of a current value according to the voltage value of the signal voltage V_sig retained in the retention capacitor 24 to the organic EL element 21 to drive the organic EL element 21 to emit light using the current.

Further, when the power supply voltage DS is switched from the first power supply voltage V_ccp to the second power supply voltage V_ini, the drive transistor 22 operates as a switching transistor as one electrode thereof serves as the source electrode and the other electrode thereof serves as the drain electrode. Accordingly, the drive transistor 22 stops the supply of the driving current to the organic EL element 21 thereby setting the organic EL element 21 to be in a non-light-emission state. In other words, the drive transistor 22 also has the function as a transistor which controls light emission and non-light-emission of the organic EL element 21.

Through the switching operation of the drive transistor 22, it is possible to set a period in which the organic EL element 21 is in a non-light-emission state (non-light-emission period) and to control a ratio of a light emission period and a non-light-emission period (duty) of the organic EL element 21. With the control of the duty, it is possible to reduce after image and blur caused by light emission of the pixel over one display frame period, and particularly, to make a level of quality of a dynamic image more preferable.

Among the first and second power supply voltages V_ccp and V_ini which are selectively supplied from the power supply scanning unit 50 through the power supply line 32, the first power supply voltage V_ccp is a power supply voltage for supplying a drive current that drives the organic EL element 21 to emit light to the drive transistor 22. In addition, the second power supply voltage V_ini is a power supply voltage for applying an inverse bias to the organic EL element 21. The second power supply voltage V_ini is set to a voltage lower than the reference voltage V_ofs, and for example, when the threshold voltage of the drive transistor 22 is set to V_th, the second power supply voltage V_ini is set to a voltage lower than V_ofs−V_th, and preferably to a voltage sufficiently lower than V_ofs−V_th.

Each pixel 20 of the pixel array unit 30 has the function of correcting variation of a drive current resulting from variation of characteristics of the drive transistor 22. Here, as the characteristics of the drive transistor 22, for example, the threshold voltage V_th of the drive transistor 22, and a mobility u of a semiconductor thin film constituting a channel of the drive transistor 22 (which will be described hereinafter simply as “mobility u of the drive transistor 22”) are exemplified.

Correction of a variation of a drive current caused due to the variation of the threshold voltage V_th (which will be described hereinafter as “threshold correction”) is performed by initializing a gate voltage V_g of the drive transistor 22 to the reference voltage V_ofs. To be specific, an operation of setting an initialization voltage (reference voltage V_ofs) of the gate voltage V_g of the drive transistor 22 as a reference and changing a source voltage V_s of the drive transistor 22 toward a potential obtained by reducing the threshold voltage Vth of the drive transistor 22 from the initialization voltage (reference voltage V_ofs) is performed. When this operation progresses, a gate-source voltage V_gs of the drive transistor 22 soon converges on the threshold voltage V_th of the drive transistor 22. A voltage equivalent to the threshold voltage V_th is retained in the retention capacitor 24. By retaining the voltage equivalent to the threshold voltage V_th in the retention capacitor 24, it is possible to suppress dependency of a drain-source current I_ds flowing through the drive transistor 22 on the threshold voltage Vth when the drive transistor 22 is driven at the signal voltage V_sig of a video signal.

Correction of a variation of a drive current caused due to a variation of the mobility u (which will be described hereinafter as “mobility correction”) is performed by flowing a current to the retention capacitor 24 via the drive transistor 22 in a state in which the writing transistor 23 enters a conductive state and the signal voltage V_sig of the video signal is written. In other words, the correction is performed by applying negative feedback to the retention capacitor 24 with a feedback amount (correction amount) according to the current I_ds flowing through the drive transistor 22. When a video signal is written through the correction of the threshold, the dependency of the drain-source current I_ds on the threshold voltage V_th disappears and the drain-source current I_ds depends on the mobility u of the drive transistor 22. Accordingly, by applying negative feedback to the drain-source voltage V_ds of the drive transistor 22 with the feedback amount according to the current I_ds flowing through the drive transistor 22, it is possible to suppress the dependency of the drain-source current I_ds flowing through the drive transistor 22 on the mobility u.

Basic Circuit Configuration in Ideal State

FIG. 3 is a timing waveform diagram for illustrating a basic circuit operation in an ideal state of the organic EL display device 10 having the above-described configuration. In the timing waveform diagram of FIG. 3, respective changes in the voltage (write scanning signals) WS of the scanning line 31, the voltage (power supply voltage) DS of the power supply line 32, the voltage (V_sig/V_ofs) of the signal line 33, and the gate voltage V_g and the source voltage V_s of the drive transistor 22 are shown.

Since the write transistor 23 is an N-channel type, the state of the high voltage of each write scanning signal WS is an active state, and the state of the low voltage thereof is a non-active state. Further, the write transistor 23 enters a conductive state in the active state of the write scanning signal WS, and enters a non-conductive state in the non-active state.

In the timing waveform diagram of FIG. 3, a period from time point t₁₁ to time point t₁₉ is a switching cycle of the voltages of the signal lines 33, that is, a switching cycle of the signal voltage V_sig and the reference voltage V_ofs of the video signal, and switching of the signal voltage V_sig and the reference voltage V_ofs is performed within 1 horizontal period (1 H).

A time prior to time point t₁₂ corresponds to a light emission period of the organic EL element 21 in a previous display frame. When the time reaches time point t₁₂, a non-light-emission period of a new display frame (current display frame) in the line sequential scanning is started. Further, a period from time point t₁₃ to time point t₁₅ during which the write scanning signal WS enters the active state is a write period in which the write transistor 23 writes the reference voltage V_ofs into the pixels 20. In addition, a period from time point t₁₄ at which the voltage DS of each power supply line 32 is switched from the second power supply voltage V_ini to the first power supply voltage V_ccp to time point t₁₅ at which the write scanning signal WS transitions to the non-active state is a threshold value correction period for correcting the variation of the drive current caused by the variation of the threshold value Vth of the drive transistor 22.

Further, during a period from time point t₁₆ to time point t₁₉, the voltage of the signal line 33 becomes the signal voltage V_sig of the video signal. In addition, during a period from time point t₁₇ to time point t₁₈, the write scanning signal WS enters the active state again, and the write transistor 23 enters the conductive state. Thus, the signal voltage V_sig of the video signal is written into the pixel 20 by the write transistor 23, and a mobility correction process of correcting the variation of the drive current caused by the variation of the mobility u of the drive transistor 22 is performed. That is, the period from time point t₁₇ to time point t₁₈ is a write and mobility correction period of the signal voltage V_sig. Then, when the time reaches time point t₁₈, the light emission period of the current frame is started.

In the timing waveform diagram of FIG. 3, V_cath is a cathode voltage of the organic EL element 21. Further, V_thel is a threshold value voltage of the organic EL element 21.

Shortening of Mobility Correction Time

In the above-described organic EL display device 10, a change in the source voltage of the drive transistor 22 which is under a mobility correction operation is determined by a relationship between a current supply capability of the drive transistor 22 and a capacitance value of the pixel capacitor connected to the source electrode of the drive transistor 22. Specifically, a source voltage V of the drive transistor 22 after the mobility correction operation is given as the following Expression (1).

$\begin{array}{cc}V=V_{\mathrm{sig}}-V_{\mathrm{th}}-\frac{1}{\left(\frac{1}{V_{\mathrm{sig}}-V_{\mathrm{th}}-V_s}-\frac{\beta }{2C}t\right)}& \left(1\right)\end{array}$

Here, V_sig represents a signal voltage of a video signal, V_th represents a threshold value voltage of the drive transistor 22, V_s represents a source voltage of the drive transistor 22 before a mobility correction operation, t represents a mobility correction time, and β represents a current supply capability of the drive transistor 22. Further, C represents a capacitance value of a pixel capacitor. In addition, when a capacitance value of the retention capacitor 24 is C_s, a capacitance value of an equivalent capacitor of the organic EL element 21 is C_oled, and a capacitance value of the auxiliary capacitor 25 is C_sub, C=C_s+C_oled+C_sub. Furthermore, the current supply capability β of the drive transistor 22 is given as the expression β=u×C_ox×(W/L). Here, u represents a mobility of a semiconductor film that forms a channel of the drive transistor 22, C_ox represents a gate capacitance per unit area of the drive transistor 22, W represents a channel width, and L represents a channel length.

It can be understood from Expression (1) that as the current supply capability β of the drive transistor 22 increases and the capacitance value C of the pixel capacitor decreases, an increase (V_s→V) of the source voltage of the drive transistor 22 at the same mobility correction time t becomes large.

That is, in a case in which the current supply capability β of the drive transistor 22 is large and the capacitance value C of the pixel capacitor is small, as shown in FIG. 4A, an increasing speed of the source voltage V_s of the drive transistor 22 which is under the mobility correction operation is fast, and thus the source voltage V_s may reach a voltage value of V_cath+V_thel during writing of the signal voltage V_sig. Further, since a current starts to flow in the organic EL element 21 at the moment at which the source voltage Vs of the drive transistor 22 reaches the voltage value of V_cath+V_thel, mobility correction is not appropriately performed, or the organic EL element 21 erroneously emits light, which becomes a factor in deterioration of uniformity.

Thus, as shown in FIG. 4B, a driving method for shortening the mobility correction time (signal write and mobility correction period) and terminating the mobility correction operation before a current starts to flow in the organic EL element 21, that is, before the organic EL element 21 is turned on, is considered. The mobility correction time is determined by a pulse width of a mobility correction pulse which is a second pulse of the write scanning signal WS in the timing waveform diagram of FIG. 3. Accordingly, it is possible to shorten the mobility correction time by shortening the pulse width of the mobility correction pulse. Further, in accordance with this driving method, it is possible to suppress deterioration of uniformity due to turning-on of the organic EL element 21 during the mobility correction period.

However, in order to realize the driving for terminating the mobility correction operation before the above-mentioned driving, that is, before the organic EL element 21 is turned on, it is necessary to provide a circuit for generating a mobility correction pulse of a narrow (short) pulse width. Generally, a pulse signal of a pulse width of about several 100 nsec is input to the display panel 70, and generation of the write scanning signal WS including the mobility correction pulse is performed in the display panel 70 on the basis of the pulse signal. Under such an environment, in order to shorten the pulse width of the mobility correction pulse, specifically, in order to generate a mobility correction pulse of a pulse width of about several nsec, it is necessary to form a pulse width adjustment circuit on the display panel 70.

Pulse Width Adjustment Circuit

FIG. 5 shows a configuration example of a pulse width adjustment circuit in a peripheral circuit of the pixel array unit 30. FIG. 5 shows the pixel array unit 30, and the write scanning unit 40 which is one peripheral circuit thereof.

The write scanning unit 40 is configured by a shift register circuit, for example, and outputs shift signals WSSR₁ to WSSR_m from respective shift stages on the basis of a cross pulse WSCK and a start pulse WSST input from outside the display panel 70 through input terminals 71 and 72. The shift signals WSSR₁ to WSSR_m are supplied to respective pixel rows of the pixel array unit 30 as write scanning signals WS1 to SW_m including mobility correction pulses through switch circuits 41₁ to 41_m provided for the each pixel row.

Further, enable signals WSEN₁ and WSEN₂ are input to a peripheral circuit on the display panel 70 through the input terminal 73 and 74. Pulse widths of the enable signals WSEN₁ and WSEN₂ are about several 100 nsec. The enable signals WSEN₁ and WSEN₂ are supplied to the pulse width adjustment circuit 80 through level shift (L/S) circuits 75 and 76. The pulse width adjustment circuit 80 is configured by a delay circuit unit 81 and a gate circuit unit 82.

The delay circuit unit 81 is a circuit part for determining a pulse width of a mobility correction pulse, and has a configuration in which a plurality of inverter circuits are connected in series. The gate circuit unit 82 is configured by a NAND circuit 821, an inverter circuit 822, a NOR circuit 823, and an inverter circuit 824. The NAND circuit 821 receives an input signal and an output signal of the delay circuit unit 81 as two inputs. An output signal of the NAND circuit 821 becomes one input signal A of the NOR circuit 823 through the inverter circuit 822. A pulse width of the input signal A is about several nsec, and becomes a pulse width of a mobility correction pulse.

The NOR circuit 823 receives the enable signal WSEN₂ that has passed through the level shift circuit 76 as the other input signal. An output signal of the NOR circuit 823 is supplied to a buffer circuit 83 through the inverter circuit 824. The buffer circuit 83 has a configuration in which a plurality of inverter circuits are connected in series. An output signal B of the buffer circuit 83 is supplied to the switch circuits 41₁ to 41_m.

FIG. 6 shows waveforms of signals of the respective units in FIG. 5. Specifically, FIG. 6 shows respective waveforms of the cross pulse WSCK, the start pulse WSST, the enable signals WSEN₁ and WSEN₂, the one input signal A of the NOR circuit 823, and the output signal B of the buffer circuit 83. FIG. 6 further shows respective waveforms of the shift signals WSSR₁, WSSR₂, WSSR₃, and WSSR₄ corresponding to four pixel rows of the write scanning unit 40, and the write scanning signals WS₁, WS₂, WS₃, and WS₄ corresponding to four pixel rows.

As described above, in order to shorten the pulse width of the mobility correction pulse, it is necessary to form the pulse width adjustment circuit 80 having the above-mentioned configuration on the display panel 70. Further, also when the write scanning signals WS are output to the respective pixels 20 of the pixel array unit 30, it is necessary to increase element sizes of the switch circuits 41₁ to 41_m in order to prevent pulse delay. If the element sizes are increased, a parasitic capacitance attached to a wire connected to the drain electrode (the source electrode) of each of the switch circuits 41₁ to 41_m is increased, and thus, it is necessary to increase the element size of the buffer circuit 83.

In this way, in order to shorten the pulse width of the mobility correction pulse, it is necessary to form the pulse width adjustment circuit 80 on the display panel 70 or to increase the element size of the buffer circuit 83, so that the circuit size of the peripheral circuits of the pixel array unit 30 increase. Thus, the area of a peripheral circuit region of the pixel array unit 30 in which the peripheral circuits are disposed on the display panel 70, that is, the area of a frame region, increases. Further, when a configuration in which a semiconductor substrate such as a silicon substrate is used as the substrate of the display panel 70 is employed, a yield (theoretical yield) is reduced, which leads to increase in the cost of the display device.

Display Device According to Embodiment of Present Disclosure

In the active-matrix type organic EL display device according to the embodiment of the present disclosure, it is not necessary to shorten a pulse width of a mobility correction pulse (drive pulse), and in order to enable reduction in the circuit size of the peripheral circuits of the pixel array unit, an operation point of the drive transistor 22 is set as a cut-off region after the threshold value correction process. To be specific, the operation point of the drive transistor 22 is set to be the cut-off region by providing a potential change with respect to the source electrode of the drive transistor 22 by coupling (so-called capacity coupling) through the auxiliary capacitor 25.

By providing a potential change to the other terminal of the auxiliary capacitor 25, one terminal of which is connected to the source electrode of the drive transistor 22, it is possible to change the potential of the source electrode of the drive transistor 22. To be more specific, by connecting the other terminal of the auxiliary capacitor 25 to a control line and by switching a control signal OS that is provided to the other terminal of the auxiliary capacitor 25 through the control line from a non-active state to an active state, the potential change may be provided to the source electrode of the drive transistor 22.

The source voltage of the drive transistor 22 when the potential change is provided to the source electrode of the drive transistor 22 is set to be a voltage smaller than at least V_cath+V_thel. Here, V_cath is a cathode electrode of the organic EL element 21, and V_thel is a threshold value voltage of the organic EL element 21. The source voltage of the drive transistor 22 at that time is set as follows.

When the gate-source voltage of the drive transistor 22 after the potential change is provided is represented as V_gs′(=V_g′−V_s′), the source voltage V_s′ is set to a voltage that satisfies the following expression.

$V_s^{\prime }=V_{\mathrm{ofs}}-V_{\mathrm{th}}+\Delta V_{\mathrm{os}}\times \frac{C_{\mathrm{sub}}}{\left(C_{\mathrm{sub}}+C_{\mathrm{cs}}+C_{\mathrm{oled}}\right)}<V_{\mathrm{cath}}+V_{\mathrm{thel}}$

Here, when the amplitude of the control signal OS is represented as ΔV_os, if the following expression is used,

$\Delta V_{\mathrm{os}}\times \frac{C_{\mathrm{sub}}}{\left(C_{\mathrm{sub}}+C_{\mathrm{cs}}+C_{\mathrm{oled}}\right)}=\Delta V_s^{\prime }$

the gate voltage V_g′ of the drive transistor 22 is as follows.

$V_g^{\prime }=V_{\mathrm{ofs}}+\Delta V_s^{\prime }\times \frac{C_{\mathrm{cs}}}{\left(C_{\mathrm{cs}}+C_p\right)}$

Here, C_p represents a parasitic capacitance formed in the gate electrode of the write transistor 23.

Further, when a maximum voltage of the signal voltage V_sig of the video signal is known, voltage setting is performed so that the drive transistor 22 maintains the cut-off state even when the maximum voltage is written. To be specific, the voltage setting is performed as follows. Here, when the maximum voltage of the signal voltage V_sig of the video signal is represented as V_sigMAX, the gate-source voltage of the drive transistor 22 after writing of the signal voltage V_sig is set to a voltage that satisfies the following expression.

$V_g^{″}=V_{\mathrm{sig}\mathrm{MAX}}$ $V_s^{″}=V_s^{\prime }+\left(V_{\mathrm{sig}\mathrm{MAX}}-V_g^{\prime }\right)\times \frac{C_{\mathrm{cs}}}{\left(C_{\mathrm{sub}}+C_{\mathrm{cs}}+C_{\mathrm{oled}}\right)}$ $V_{\mathrm{gs}}^{″}=V_{\mathrm{sig}\mathrm{MAX}}-\left\{V_s^{\prime }+\left(V_{\mathrm{sig}\mathrm{MAX}}-V_g^{\prime }\right)\times \frac{C_{\mathrm{cs}}}{\left(C_{\mathrm{sub}}+C_{\mathrm{cs}}+C_{\mathrm{oled}}\right)}\right\}<V_{\mathrm{th}}$

As described above, by setting the operation point of the drive transistor as the cut-off region after the threshold value correction process, it is possible to obtain the following effects. After the threshold value correction process, when the signal voltage V_sig of the video signal is written by the write transistor 23, if the operation point of the drive transistor 22 is the cut-off region, it is natural for the current I_ds not to flow into the drive transistor 22. Thus, it is possible to remove a factor that causes the source voltage V_s of the drive transistor 22 to fluctuate other than the coupling associated with the writing of the signal voltage V_sig. Accordingly, it is not necessary to shorten the correction period (correction time), and thus it is not necessary to narrow the pulse width of the mobility correction pulse (drive pulse).

The fact that the pulse width of the mobility correction pulse does not need to be narrowed means that the pulse width adjustment circuit 80 (see FIG. 5) for shortening the pulse width of the mobility correction pulse does not need to be formed on the display panel 70. Thus, it is possible to achieve reduction in the circuit size of the peripheral circuits of the pixel array unit 30. Further, due to the reduction in the circuit size of the peripheral circuits of the pixel array unit 30, it is possible to narrow a frame of the display panel 70 compared with a case in which the pulse width of the mobility correction pulse is shortened, to thereby reduce the size of the display panel 70. Further, when a configuration in which a semiconductor substrate such as a silicon substrate is used as the substrate of the display panel 70 is employed, improvement in a yield is expected, and thus it is possible to contribute to cost reduction of the display device.

The above-described technology of the present disclosure may not only be applied to a case in which a transistor that forms the pixels (pixel circuit) 20 is formed by an N-channel type transistor, but may also be applied to a case in which the transistor is formed by a P-channel type transistor. Hereinafter, a pixel circuit formed by an N-channel type transistor will be described as a pixel circuit according to Example 1, and a pixel circuit formed by a P-channel type transistor will be described as a pixel circuit according to Example 2. As will be obvious from the following description, the pixel circuit according to Example 1 has an advantage in that the number of components of the pixel circuit is less than that of the pixel circuit according to Example 2.

Example 1

FIG. 7 is a system configuration diagram illustrating an overview of a configuration of the organic EL display device including the pixel circuit according to Example 1.

Basically, a pixel circuit 20A according to Example 1 is configured to have the same components as the pixel circuit 20 shown in FIG. 2. Specifically, the pixel circuit 20A includes the organic EL element 21, the drive transistor 22, the write transistor 23, the retention capacitor 24, and the auxiliary capacitor 25. The drive transistor 22 and the write transistor 23 are formed by an N-channel type MOS transistor. The pixel circuit 20A is different from the pixel circuit 20 in that the other terminal of the auxiliary capacitor 25 of which one terminal thereof is connected to the source electrode of the drive transistor 22 is connected to the control line 35.

The pixel circuits 20A having such a configuration are 2-dimensionally disposed in a matrix form to form a pixel array unit 30. Here, for simplification of illustration, only one pixel circuit 20A is shown. The control wire 35 is wired along a pixel row for each pixel row, with respect to the matrix arrangement of the pixel circuits 20A.

An organic EL display device 10 including the pixel circuits 20A according to Example 1 includes a control scanning unit 90 serving as a control unit, in addition to the write scanning unit 40 and the signal output unit 60, as a peripheral circuit of the pixel array unit 30. The control scanning unit 90 is provided in a peripheral circuit region (frame region) on the same side as the write scanning unit 40 with respect to the pixel array unit 30, for example. To be more specific, the control scanning unit 90 is provided in peripheral circuit region on one side in the lateral direction (row direction) of the pixel array 30.

The other terminal of the auxiliary capacitor 25 is connected to the control line 35 for each pixel circuit 20A. One terminal of the control line 35 is connected to an output terminal of a corresponding row of the control scanning unit 90. The control scanning unit 90 is configured by a shift register circuit or the like, similar to the write scanning unit 40. The control scanning unit 90 outputs a control signal OS which is in an active state over a period from the time after the threshold value correction process to the time before the write process of the signal voltage V_sig is terminated, in synchronization with the line sequential scanning performed by the write scanning unit 40.

It is preferable that the scanning line 31 that transmits the write scanning signal WS to the pixel array 20A and the control line 35 that transmits the control signal OS to the pixel circuit 20A be formed of the same wire materials. Further, it is preferable that the scanning line 31 and the control line 35 be formed to have the same thicknesses and widths. Here, the term “same” means not only “strictly the same,” but also includes “substantially the same.” That is, various variations in design or manufacturing are allowed.

FIG. 8 is a timing waveform diagram illustrating a circuit operation of the organic EL display device 10 including the pixel circuits 20A according to Example 1. The timing waveform diagram of FIG. 8 shows changes in waveforms of the power supply voltage (V_ccp/V_ini) DS, the write scanning signal WS, the control signal OS, and the gate voltage V_g and the source voltage V_s of the drive transistor 22.

After the threshold value correction process, the control scanning unit 90 switches the control signal OS provided to the other terminal of the auxiliary capacitor 25 through the control line 35 from a non-active state to an active state, that is, transitions from a low voltage state to a high voltage state, to thereby provide a potential change to the other terminal of the auxiliary capacitor 25. Further, by providing the potential change to the other terminal of the auxiliary capacitor 25, it is possible to change the potential of the source electrode of the drive transistor 22 by coupling through the auxiliary capacitor 25, and to set an operation point of the drive transistor 22 as a cut-off region.

After the threshold value correction process, when the signal voltage V_sig is written by the write transistor 23, if the operation point of the drive transistor 22 is the cut-off region, it is natural for the current Ids not to flow into the drive transistor 22. Thus, it is possible to remove a factor that causes the source voltage V_s of the drive transistor 22 to fluctuate other than the coupling associated with the writing of the signal voltage V_sig. Accordingly, it is not necessary to shorten the correction period (correction time), and thus it is not necessary to narrow the pulse width of the mobility correction pulse (the second pulse of the write scanning signal WS).

In other words, since it is not necessary to shorten the correction period (correction time), it is possible to set the pulse width of the mobility correction pulse to be wide. In the organic EL display device 10 including the pixel circuits 20A according to Example 1, the pulse width of the mobility correction pulse which is the second pulse of the write scanning signal WS is set to be the same pulse width as that of the first pulse of the write scanning signal WS. Here, the term “same” means not only “strictly the same,” but also includes “substantially the same.” That is, various variations in design or manufacturing are allowed.

In this way, by setting the pulse widths of two pulses when the write scanning signal WS enters the active state two times to be the same, a circuit configuration of the write scanning unit 40 that generates the write scanning signal WS can be simplified compared with a case in which the two pulse widths are different from each other. That is, when two pulses of which the pulse widths are different from each other are generated, two systems of logic circuits or the like for generating the respective pulses are necessary, but by setting the two pulse widths to be the same, one system of a logic circuit or the like is sufficient, and thus it is possible to simplify the circuit configuration of the write scanning unit 40.

Circuit Operation

Next, a circuit operation (a method for driving a display device) of the organic EL display device 10 including the pixel circuits 20A according to Example 1 will be described with reference to the timing waveform diagram of FIG. 8.

Since the write transistor 23 is configured by an N-channel type transistor, a high voltage state of the write scanning signal WS is an active state, and a low voltage state thereof is a non-active state. Further, the write transistor 23 enters a conductive state in the active state of the write scanning signal WS, and enters a non-conductive state in the non-active state thereof. In addition, with respect to the control signal OS, a high voltage state is an active state, and a low voltage state thereof is a non-active state.

In a light emission state of the organic EL element 21, at time point t₂₁, the power supply voltage DS is switched from the first power supply voltage V_ccp to the second power supply voltage V_ini. Here, when the second power supply voltage V_ini is set to V_ini<V_thel+V_cath, the source voltage V_s of the drive transistor 22 becomes approximately the same as the second power supply voltage V_ini, and thus the organic EL element 21 enters a reverse bias state to extinct.

Subsequently, as the write scanning signal WS enters the active state at time point t₂₂ (first pulse), the write transistor 23 enters the conductive state to write the reference voltage V_ofs into the pixel 20A. Thus, the gate voltage V_g of the drive transistor 22 is initialized as the reference voltage V_ofs. Further, a period from time point t₂₃ when the power supply voltage DS is switched from the second power supply voltage V_ini to the first power supply voltage V_ccp to time point t₂₄ when the write scanning signal WS transitions to the non-active state from the active state becomes a period for threshold value correction.

Then, at time point t₂₅ after the threshold value correction process, the control signal OS is switched to the active state from the non-active state, that is, transitions to the high voltage state from the low voltage state, and thus a potential change is provided to the other terminal of the auxiliary capacitor 25. Thus, since the source voltage V_s of the drive transistor 22 is changed by coupling (capacity coupling) through the auxiliary capacitor 25, the operation point of the drive transistor 22 becomes the cut-off region. Accordingly, the current I_ds does not flow into the drive transistor 22.

In the cut-off state of the drive transistor 22, as the write scanning signal WS enters the active state again at time point t₂₆ (second pulse), the write transistor 23 enters the conductive state to write the signal voltage V_sig of the video signal into the pixel 20A. Further, as the control signal OS is switched to the non-active state from the active state at time point t₂₇, the drive transistor 22 enters the conductive state, the current I_ds flows into the drive transistor 22, and the mobility correction process is performed.

Then, as the write scanning signal WS transitions to the non-active state from the active state at time point t₂₈, the signal write and the mobility correction period are terminated, and a light emission period of a new display frame is started.

The above-described circuit operation is characterized in that the potential change is provided to the other terminal of the auxiliary capacitor 25 after the threshold correction process and the potential change is provided to the source electrode of the drive transistor 22 by coupling through the auxiliary capacitor 25, so that the operation point of the drive transistor 22 is set as the cut-off region. In accordance with this circuit operation, when the signal voltage V_sig is written, since the current I_ds does not flow into the drive transistor 22, it is possible to remove the factor that causes the source voltage V_s of the drive transistor 22 to fluctuate other than the coupling associated with the writing of the signal voltage V_sig.

Thus, it is not necessary to shorten the mobility correction period. That is, it is not necessary to narrow the pulse width of the mobility correction pulse (the second pulse of the write scanning signal WS). As a result, it is not necessary to form the pulse width adjustment circuit 80 (see FIG. 5) that generates a mobility correction pulse of a narrow pulse width on the display panel 70, and thus it is possible to reduce the circuit size of the peripheral circuits of the pixel array unit 30. Further, by reducing the circuit size of the peripheral circuits, it is possible to narrow the frame, to thereby minimize the display panel 70.

Further, in the pixel circuit 20A according to Example 1, the control scanning unit 90 is provided in the peripheral circuit region on the same side as the write scanning unit 40 with respect to the pixel array unit 30. Thus, it is possible to set distances from the write scanning unit 40 and the control scanning unit 90 to the pixel circuit 20A which is a drive target to be approximately equal to each other, and thus it is possible to minimize a timing deviation caused by a difference between the distances between the write scanning signal WS and the control signal OD.

In particular, the scanning line 31 that transmits the write scanning signal WS to the pixel array 20A, and the control line 35 that transmits the control signal OS to the pixel circuit 20A are formed of the same wiring materials and to have the same wiring thicknesses and the same wiring widths. Thus, since delay amounts when the write scanning signal WS and the control signal OD are transmitted to the same pixel circuit 20A can be set to be approximately equal to each other, it is possible to remove a timing deviation between the signals. As a result, it is possible to more reliably perform the driving with respect to the pixel circuit 20A which is a drive target. Here, the wiring materials, the wiring thicknesses, and the wiring widths have all been assumed to be the same, but this is not limited thereto.

Example 2

FIG. 9 is a system configuration diagram illustrating an overview of a configuration of an organic EL display device including a pixel circuit according to Example 2.

As shown in FIG. 9, a pixel circuit 20B according to Example 2 is configured to include a switching transistor 26 and a current control transistor 27, in addition to the organic EL element 21, the drive transistor 22, the write transistor 23, the retention capacitor 24, and the auxiliary capacitor 25. The drive transistor 22, the write transistor 23, the switching transistor 26, and the current control transistor 27 are formed by P-channel type MOS transistors.

The pixel circuits 20B having such a configuration are 2-dimensionally disposed in a matrix form to form a pixel array unit 30. Here, for simplification of illustration, only one pixel circuit 20B is shown. The control wire 35 is wired along a pixel row for each pixel row, with respect to the matrix arrangement of the pixel circuits 20B. Further, a first drive line 36 and a second drive line 37 are wired along the pixel row for each pixel row.

An organic EL display device 10 including the pixel circuits 20B according to Example 2 includes a control scanning unit 90 serving as a control unit, in addition to the write scanning unit 40 and the signal output unit 60, as a peripheral circuit of the pixel array unit 30. The control scanning unit 90 is provided in a peripheral circuit region on the same side as the write scanning unit 40 with respect to the pixel array unit 30, to be more specific, in a peripheral circuit region on one side of the pixel array 30 in the lateral direction (row direction) in the figure of the pixel array unit 30, for example.

The other terminal of the auxiliary capacitor 25 is connected to the control line 35 for each of the pixel circuits 20B. One terminal of the control line 35 is connected to an output terminal of a corresponding row of the control scanning unit 90. The control scanning unit 90 is configured by a shift register circuit or the like, similar to the write scanning unit 40. The control scanning unit 90 outputs a control signal OS which is in an active state (in this example, a low voltage state) over a period from the time after the threshold value correction process to the time when a writing process of the signal voltage V_sig is terminated, in synchronization with the line sequential scanning performed by the write scanning unit 40.

It is preferable that the scanning line 31 that transmits the write scanning signal WS to the pixel array 20B and the control line 35 that transmits the control signal OS to the pixel circuit 20B be formed of the same wire material. Further, it is preferable that the scanning line 31 and the control line 35 be formed to have the same thicknesses and widths. Here, the term “same” means not only “strictly the same,” but also includes “substantially the same.” That is, various variations in design or manufacturing are allowed.

The organic EL display device 10 including the pixel circuits 20B according to Example 2 further includes a drive scanning unit 91 and a current control scanning unit 92 as peripheral circuits of the pixel array unit 30. The drive scanning unit 91 and the current control scanning unit 92 are provided in a peripheral circuit region opposite to the write scanning unit 40 and the control scanning unit 90 with the pixel array unit 30 interposed therebetween, for example. Here, the arrangements of the write scanning unit 40, the control scanning unit 90, the drive scanning unit 91, and the current control scanning unit 92 are only examples, and the present disclosure is not limited thereto.

The gate electrode of the switching transistor 26 is connected to the first drive line 36 for each pixel circuit 20B. One terminal of the first drive line 36 is connected to an output terminal of a corresponding row of the control scanning unit 91. The control scanning unit 91 is configured by a shift register circuit or the like, similar to the write scanning unit 40. The control scanning unit 91 outputs a control signal AZ which is in an active state over a period from the time before the threshold value correction process is started to the time when light emission is started, in synchronization with the line sequential scanning performed by the write scanning unit 40.

The gate electrode of the current control transistor 27 is connected to the second drive line 37 for each pixel circuit 20B. One terminal of the second drive line 37 is connected to an output terminal of a corresponding row of the current control scanning unit 92. The current control scanning unit 92 outputs a current control signal DS which is in a non-active state (in this example, a high voltage state) over a period from the time when the threshold value correction process is started to the time before the light emission is started and is in an active state in a period of time other than the above-mentioned period of time, in synchronization with the line sequential scanning performed by the write scanning unit 40.

Circuit Operation

Next, a circuit operation of the organic EL element 10 including the pixel circuits 20B according to Example 2 will be described with reference to a timing waveform diagram of FIG. 10. The timing waveform diagram of FIG. 10 shows respective changes in the voltage (V_sig/V_ofs) of the signal line 33, the current control signal DS, the drive signal AZ, the write scanning signal WS, the control signal OS, and the source voltage V_s, the gate voltage V_g, and the drain voltage V_d of the drive transistor 22.

Since each transistor of the pixel circuit 20B is configured by a P-channel type transistor, the low voltage state of each of the current control signal DS, the drive signal AZ, the write scanning signal WS, and the control signal OS is the active state, and the high voltage states thereof are the non-active state. Further, the write transistor 23 enters the conductive state in the active state of the write scanning signal WS, and enters the non-conductive state in the non-active state thereof. The switching transistor 26 enters the conductive state in the active state of the drive signal AZ, and enters the non-conductive state in the active state thereof. Further, the current control transistor 27 enters the conductive state in the active state of the current control signal DS, and enters the non-conductive state in the non-active state thereof.

In the timing waveform of FIG. 10, a period from time point t₃₁ to time point t₄₂ is 1 horizontal period (1 H). In a state in which the voltage of the signal line 33 becomes the reference voltage V_ofs from the light emission state of the organic EL element 21, the write scanning signal WS and the drive signal AZ enter the active state at time point t₃₂, and thus the write transistor 23 and the switching transistor 26 enter the conductive state.

Thus, the reference voltage V_ofs is written into the gate electrode of the drive transistor 22 (V_g=V_ofs). Here, since the current control transistor 27 is in the conductive state, the source voltage Vs of the drive transistor 22 becomes the power supply voltage V_ccp (V_s=V_ccp). Thus, the supply of the drive current to the organic EL element 21 from the drive transistor 22 is stopped, and thus the organic EL element 21 enters an extinction state.

Then, a period from time point t₃₂ to time point t₃₃ when the current control signal DS transitions to the non-active state from the active state becomes a period for extinction of the organic EL element 21, reset of the source voltage V_s and the drain voltage V_d of the drive transistor 22, and preparation of the threshold value correction process. During the period from t₃₂ to t₃₃, since the switching transistor 26 enters the conductive state, a power supply voltage V_ss is written into the drain voltage of the drive transistor 22 (V_d=V_ss).

Then, while the write scanning signal WS and the drive signal AZ are in the active state, the current control signal DS enters the non-active state at time point t₃₃, and the current control transistor 27 enters the non-conductive state, so that the threshold value correction period is started. The threshold value correction period becomes a period from time t₃₃ to time point t₃₃ when the write scanning signal WS transitions to the non-active state.

Next, the control signal OS is switched to the active state from the non-active state at time point t₃₅, that is, transitions to the low voltage state from the high voltage state, to provide a potential change to the other terminal of the auxiliary capacitor 25. Thus, the source voltage Vs of the drive transistor 22 is changed by the coupling through the auxiliary capacitor 25, and thus the operation point of the drive transistor 22 becomes the cut-off region. Accordingly, the current I_ds does not flow into the drive transistor 22.

Then, the voltage of the signal line 33 is switched into the signal voltage V_sig of the video signal from the reference voltage V_ofs at time point t₃₆. As the write scanning signal WS enters the active state again at time point t₃₇, and the write transistor 23 enters the conductive state, the signal voltage V_sig is imported (written) into the pixel circuit 20B. Further, a period from time point t₃₇ to time point t₃₈ when the write scanning signal WS transitions to the non-active state is a signal write and mobility correction period.

Then, as the control signal OS transitions to the non-active state at time point t₃₉, and then the current control signal DS transitions to the active state at time point t₄₀, the power supply voltage V_ccp is applied to the source electrode of the drive transistor 22, so that the current supply to the drive transistor 22 becomes possible. Further, as the drive signal AZ transitions to the non-active state at time point t₄₁, the light emission period of the organic EL element 21 is started. Then, as the voltage of the signal line 33 is switched to the reference voltage V_ofs from the signal voltage V_sig of the video signal at time point t₄₂, the period of 1 H is terminated.

While the pixel circuit 20B according to the above-described example 2 has a larger number of components than the pixel circuit 20A according to Example 1, by using the organic EL display device 10 including the pixel circuits 20B, it is possible to obtain the same effects as those of the organic EL display device 10 including the pixel circuits 20A according to Example 1.

That is, it is not necessary to prepare a mobility correction pulse of a narrow pulse width for mobility correction, and it is not necessary to form the pulse width adjustment circuit 80 (see FIG. 5) that generates the mobility correction pulse on the display panel 70, and thus it is possible to reduce the circuit size of the peripheral circuits of the pixel array unit 30. Further, by reducing the circuit size of the peripheral circuits of the pixel array unit, it is possible to narrow a frame, and accordingly, it is possible to reduce the size of the display panel 70.

Further, in the pixel circuit 20B according to Example 2, the control scanning unit 90 is provided in the peripheral circuit region on the same side as the write scanning unit 40 with respect to the pixel array unit 30. Thus, it is possible to set distances from the write scanning unit 40 and the control scanning unit 90 to the pixel circuit 20B which is a drive target to be approximately equal to each other, and thus it is possible to minimize a timing deviation caused by a difference between the distances between the write scanning signal WS and the control signal OD.

In particular, the scanning line 31 that transmits the write scanning signal WS to the pixel circuit 20A and the control line 35 that transmits the control signal OS to the pixel circuit 20B are formed of the same wire materials and to have the same wire thicknesses and wire widths. Thus, it is possible to set delay amounts when the write scanning signal WS and the control signal OS are transmitted to the same pixel circuit 20B to be approximately equal to each other, and thus it is possible to remove a timing deviation of the signals. As a result, it is possible to more reliably perform driving with respect to the pixel circuit 20B which is a drive target.

Here, the wire materials, the wire thicknesses, and the wire widths are all assumed to be the same, but this is not limited thereto.

Electronic Device

The display device according to the above-described present disclosure can be used as any of display units (display devices) of electronic devices in all fields that display video signal input to electronic devices or video signals generated in electronic devices as images or videos. For example, the display device can be used as any of display units of electronic devices such as a television set, a digital camera, a note-type personal computer, a portable terminal apparatus such as a mobile phone, a video camera, and a head mounted display.

In this way, in electronic devices in all fields, by using the display device of the present disclosure as a display unit thereof, the following effects can be obtained. According to the technology of the present disclosure, it is possible to suppress deterioration of uniformity due to turning-on of the organic EL element during a mobility correction period, and thus it is possible to enhance image quality. Further, it is possible to manufacture a small-sized display panel, and thus it is possible to enhance a reasonable yield. Thus, it is possible to reduce the cost of an electronic device including a display unit. In addition, as the display panel becomes smaller, it is possible to achieve miniaturization of a set, and thus it is possible to increase the degree of freedom in design of products (electronic devices).

The display device according to the present disclosure also has a module form configured to be sealed. For example, the module corresponds to a display module formed such that a facing unit such as a transparent glass is attached to a pixel array unit. In the display module, a circuit unit or a flexible printed circuit (FPC) that inputs and outputs signals or the like between the outside and the pixel array unit may be provided. Hereinafter, digital cameras and head mounted displays are exemplified as specific examples of an electronic device using the display device according to the present disclosure. Here, the specific examples exemplified here are merely examples and the present disclosure is not limited thereto.

Specific Example 1

FIG. 11 is an external view of a digital camera of a lens interchangeable single lens reflex type, in which FIG. 11A shows a front view thereof and FIG. 11B shows a back view thereof. The digital camera of the lens interchangeable single lens reflex type includes an interchangeable imaging lens unit (interchangeable lens) on a right front side of a camera main body (camera body) 111, and includes a grip portion 113 for a photographer to grip on a left front side, for example.

Further, a monitor 114 is provided in an approximately central portion of the back of the camera main body 111. A view finder (eyepiece window) 115 is provided above the monitor 114. The photographer looks at the view finder 115, and thus, it is possible to visually recognize a light image of a subject guided from the imaging lens unit 112 and to determine composition.

In the digital camera of the lens interchangeable single lens reflex type with such a configuration, the display device of the present disclosure may be used as the view finder 115. That is, the digital camera of the lens interchangeable single lens reflex type according to the present example is manufactured by using the display device of the present disclosure as the view finder 115.

Specific Example 2

FIG. 12 is an external view of a head mounted display. The head mounted display includes hook portions 212 for being mounted on a head portion of a user, on both sides of a spectacle display unit 211, for example. In the head mounted display, the display device of the present disclosure may be used as the display unit 211. That is, the head mounted display according to this example is manufactured by using the display device of the present disclosure as the display unit 211.

Additionally, the present technology may also be configured as below.

[1]

A display device including:

a pixel array unit in which pixel circuits are disposed in a matrix form, the pixel circuits each including a light emission unit, a write transistor that writes a signal voltage of a video signal, a retention capacitor that retains the signal voltage written by the write transistor, a drive transistor that drives the light emission unit on the basis of the signal voltage retained by the retention capacitor, and an auxiliary capacitor of which one terminal is connected to a source node of the drive transistor, the pixel circuit having a function of a threshold value correction process of changing a source voltage of the drive transistor toward a voltage obtained by subtracting a threshold value voltage of the drive transistor from an initialization voltage of a gate voltage of the drive transistor with reference to the initialization voltage; and

a control unit that provides a potential change to a source electrode of the drive transistor by coupling through the auxiliary capacitor to set an operation point of the drive transistor as a cut-off region after the threshold value correction process.

[2]

The display device according to [1],

wherein the control unit changes a potential of the source electrode of the drive transistor by providing the potential change to the other terminal of the auxiliary capacitor.

[3]

The display device according to [2],

wherein the other terminal of the auxiliary capacitor is connected to a control line, and

the control unit provides the potential change to the source electrode of the drive transistor by switching a control signal provided to the other terminal of the auxiliary capacitor through the control line from a non-active state to an active state.

[4]

The display device according to any of [1] to [3],

wherein the source voltage of the drive transistor when the potential change is provided to the source electrode of the drive transistor is a voltage smaller than at least the sum of a cathode voltage of the light emission unit and a threshold value voltage of the light emission unit.

[5]

The display device according to any of [1] to [4],

wherein the write transistor writes a signal voltage into a gate electrode of the drive transistor after the potential change is provided to the source electrode of the drive transistor.

[6]

The display device according to any of [3] to [5], including:

a write scanning unit that drives the write transistor through a scanning line in units of rows,

wherein the control unit and the write scanning unit are provided in a peripheral circuit region on the same side with respect to the pixel array unit.

[7]

The display device according to [6],

wherein the control line and the scanning line are formed of same wire material and have same thickness and same width.

[8]

The display device according to any of [1] to [7],

wherein a write scanning signal enters an active state two times during the threshold value correction process and during the writing of the signal voltage, and pulse widths of two pulses when the write scanning signal enters the active state two times are the same.

[9]

The display device according to [8],

wherein the pixel circuit performs a mobility correction process of applying negative feedback to a potential difference between the gate electrode and the source electrode of the drive transistor by a correction amount corresponding to a current flowing in the drive transistor to correct a mobility of the drive transistor in a period of a second pulse among the two pulses.

[10]

A method for driving a display device including a pixel array unit in which pixel circuits are disposed in a matrix form, the pixel circuits each including a light emission unit, a write transistor that writes a signal voltage of a video signal, a retention capacitor that retains the signal voltage written by the write transistor, a drive transistor that drives the light emission unit on the basis of the signal voltage retained by the retention capacitor, and an auxiliary capacitor of which one terminal is connected to a source node of the drive transistor, the pixel circuit having a function of a threshold value correction process of changing a source voltage of the drive transistor toward a voltage obtained by subtracting a threshold value voltage of the drive transistor from an initialization voltage of a gate voltage of the drive transistor with reference to the initialization voltage, the method including:

providing a potential change to a source electrode of the drive transistor by coupling through the auxiliary capacitor to set an operation point of the drive transistor as a cut-off region after the threshold value correction process, when driving the display device.

[11]

An electronic device including

a display device that includes:

• • a pixel array unit in which pixel circuits are disposed in a matrix form, the pixel circuits each including a light emission unit, a write transistor that writes a signal voltage of a video signal, a retention capacitor that retains the signal voltage written by the write transistor, a drive transistor that drives the light emission unit on the basis of the signal voltage retained by the retention capacitor, and an auxiliary capacitor of which one terminal is connected to a source node of the drive transistor, the pixel circuit having a function of a threshold value correction process of changing a source voltage of the drive transistor toward a voltage obtained by subtracting a threshold value voltage of the drive transistor from an initialization voltage of a gate voltage of the drive transistor with reference to the initialization voltage; and
  • a control unit that provides a potential change to a source electrode of the drive transistor by coupling through the auxiliary capacitor to set an operation point of the drive transistor as a cut-off region after the threshold value correction process.

REFERENCE SIGNS LIST

10 organic EL display device20, 20A, 20B unit pixel (pixel/pixel circuit)21 organic EL element22 drive transistor23 write transistor24 retention capacitor25 auxiliary capacitor26 switching transistor28 current control transistor30 pixel array unit31 (31₁ to 31_m) scanning lines32 (32₁ to 32_m) power supply lines33 (33₁ to 33_n) signal lines,34 common power supply line35 control lines36 first drive line37 second drive line40 write scanning line50 power supply scanning unit60 signal output unit70 display panel71 to 74 input terminal75, 76 level shift (L/S) circuit80 pulse width adjustment circuit81 delay circuit unit82 gate circuit unit83 buffer circuit90 control scanning unit91 drive scanning unit92 current control scanning unit

Claims

1. A display device comprising: a plurality of pixels, anda control circuitry,wherein at least one of the plurality of pixels comprisesa light emitting element including an anode and a cathode;a capacitor;a sampling transistor configured to supply a signal voltage from a data signal line to the capacitor according to a sampling control signal supplied through a sampling control signal line;a driving transistor configured to supply driving current from a first voltage line to the anode according to a voltage stored in the capacitor;a first transistor electrically connected between the anode and a second voltage line;a second transistor electrically connected between the first voltage line and the driving transistor; anda voltage control element configured to control a potential difference between a gate of the driving transistor and a source of the driving transistor,the sampling transistor and the first transistor are configured to turn on at a first timing, andthe sampling transistor is configured to turn off a plurality of times during a first state where the second transistor is in an off state, the first state being after the first timing.

2. The display device according to claim 1, wherein the voltage control element is electrically serially connected to the capacitor.

3. The display device according to claim 1, wherein the voltage control element is configured to control the potential difference between the gate of the driving transistor and the source of the driving transistor according to a voltage control signal supplied through a voltage control signal line, andthe sampling control signal line and the voltage control signal line are formed to have the same thicknesses and widths.

4. The display device according to claim 1, wherein the first transistor is configured to electrically connect the anode and the second voltage line according to a first control signal supplied through a first control signal line, andthe second transistor is configured to electrically connect the first voltage line and the driving transistor according to a second control signal supplied through a second control signal line.

5. The display device according to claim 1, wherein the sampling transistor, the driving transistor, the first transistor and the second transistor are P channel type transistors.

6. The display device according to claim 1, wherein a potential of the first voltage line is higher than a potential of the second voltage line.

7. The display device according to claim 1, wherein the voltage control element includes an auxiliary capacitor.

8. The display device according to claim 1, wherein the cathode is electrically connected to a third voltage line.

9. The display device according to claim 1, wherein the control circuitry includes a first control circuitry and a second control circuitry, andthe plurality of pixels are arranged between the first control circuitry and the second control circuitry.