Patent Application
20190244559
This application claims priority to, and the benefit of, Korean patent application 10-2018-0015620 filed on Feb. 8, 2018 in the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference.
An aspect of the present disclosure relates to a display device.
With the development of information technologies, the importance of a display device that is a connection medium between a user and information increases. Accordingly, display devices such as a liquid crystal display device, an organic light emitting display device, and a plasma display device are increasingly used.
The display device displays an image by emitting light from light-emitting elements of pixels. However, when each pixel includes only one light-emitting element, an area of each pixel is relatively large, which may make it difficult to achieve a high resolution of the display device.
Embodiments provide a display device capable of preventing color-breakup while achieving a high resolution because one pixel may include a plurality of light-emitting diodes of a plurality of colors.
According to an aspect of the present disclosure, there is provided a display device including a plurality of data lines to supply data voltages, a plurality of scan lines to supply scan signals, and a first pixel connected to at least one of the plurality of data lines, and connected to at least one of the plurality of scan lines, the first pixel including a first light-emitting diode of a first color, in which an anode is connected to a first node and a cathode is connected to a reference voltage line, and a second light-emitting diode of a second color that is different from the first color, in which an anode is connected to the reference voltage line, and a cathode is connected to the first node.
The display device may further include a second pixel connected to at least one of the plurality of data lines, and connected to at least one of the plurality of scan lines, the second pixel including a third light-emitting diode of the first color, in which an anode is connected to a second node, and a cathode is connected to the reference voltage line, and a fourth light-emitting diode of the second color, in which an anode is connected to the reference voltage line, and a cathode is connected to the second node.
A polarity of a first data voltage applied to the first node may be alternated in units of image frames with respect to a reference voltage applied to the reference voltage line, wherein a polarity of a second data voltage applied to the second node is alternated in units of the image frames with respect to the reference voltage, and wherein the polarity of the first data voltage and the polarity of the second data voltage are opposite to each other with respect to the reference voltage in units of the image frames.
The display device may further include a second pixel connected to at least one of the plurality of data lines and connected to at least one of the plurality of scan lines, the second pixel including a third light-emitting diode of the first color, in which an anode is connected to the reference voltage line, and a cathode is connected to a second node, and a fourth light-emitting diode of the second color, in which an anode is connected to the second node, and a cathode is connected to the reference voltage line.
The display device may further include a third pixel connected to at least one of the plurality of data lines, and connected to at least one of the plurality of scan lines, the third pixel including a fifth light-emitting diode of a third color that is different from the first color and the second color, in which an anode is connected to a third node, and a cathode is connected to the reference voltage line.
A polarity of a first data voltage applied to the first node may be alternated in units of image frames with respect to a reference voltage applied to the reference voltage line, wherein a polarity of a second data voltage applied to the second node is alternated in units of the image frames with respect to the reference voltage, and wherein the polarity of the first data voltage and the polarity of the second data voltage are identical to each other with respect to the reference voltage in units of the image frames.
A polarity of a third data voltage applied to the third node may be identically maintained in units of the image frames with respect to the reference voltage.
According to an aspect of the present disclosure, there is provided a display device including a plurality of data lines to supply data voltages, a plurality of scan lines to supply scan signals, and a first pixel connected to at least one of the plurality of data lines, and connected to at least one of the plurality of scan lines, the first pixel including a first light-emitting diode of a first color, in which a cathode is connected to a first power voltage line, and an anode is connected to a second power voltage line, and a second light-emitting diode of a second color that is different from the first color, in which a cathode is connected to the second power voltage line, and an anode is connected to the first power voltage line.
The display device may further include a second pixel connected to at least one of the plurality of data lines, and connected to at least one of the plurality of scan lines, the second pixel including a third light-emitting diode of the first color, in which a cathode is connected to the second power voltage line, and an anode is connected to the first power voltage line, and a fourth light-emitting diode of the second color, in which a cathode is connected to the first power voltage line and an anode is connected to the second power voltage line.
The display device may further include a third pixel connected to at least one of the plurality of data lines, and connected to at least one of the plurality of scan lines, the third pixel including a fifth light-emitting diode of a third color that is different from the first color and the second color, in which a cathode is connected to a common low voltage line.
Each of the first pixel and the second pixel may further include a first emission control transistor including one electrode connected to the second power voltage line, the other electrode connected to a fifth node, and a gate electrode connected to a first emission control line, and a second emission control transistor including one electrode connected to the first power voltage line, the other electrode connected to the fifth node, and a gate electrode connected to a second emission control line.
Each of the first pixel and the second pixel may further include a first transistor including one electrode connected to a corresponding data line and a gate electrode connected to a corresponding scan line, a second transistor including one electrode connected to a common high voltage line, the other electrode connected to the fifth node, and a gate electrode connected to the other electrode of the first transistor, and a storage capacitor including one electrode connected to the common high voltage line, and the other electrode connected to the gate electrode of the second transistor.
When the first transistor is in a turned-on state, the first emission control transistor and the second emission control transistor may be in a turned-off state.
The display device may further include a first switch to connect the first power voltage line and the common low voltage line, and a second switch to connect the second power voltage line and the common low voltage line.
The first switch and the second switch may be alternately turned on and off in units of image frames.
When the first switch is in a turned-on state, the second switch may be in a turned-off state, and vice versa.
The first emission control transistor and the second emission control transistor may be alternately turned on and off in units of image frames.
When the first emission control transistor is in a turned-on state, the second emission control transistor may be in a turned-off state, and vice versa.
Features of the inventive concept and methods of accomplishing the same may be understood more readily by reference to the following detailed description of embodiments and the accompanying drawings. Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings. The described embodiments, however, may be embodied in various different forms, and should not be construed as being limited to only the illustrated embodiments herein. Rather, these embodiments are provided as examples so that this disclosure will be thorough and complete, and will fully convey the aspects and features of the present inventive concept to those skilled in the art. Accordingly, processes, elements, and techniques that are not necessary to those having ordinary skill in the art for a complete understanding of the aspects and features of the present inventive concept may not be described. Unless otherwise noted, like reference numerals denote like elements throughout the attached drawings and the written description, and thus, descriptions thereof will not be repeated. Further, parts not related to the description of the embodiments might not be shown to make the description clear. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity.
Various embodiments are described herein with reference to sectional illustrations that are schematic illustrations of embodiments and/or intermediate structures. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances, are to be expected. Further, specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments according to the concept of the present disclosure. Thus, embodiments disclosed herein should not be construed as limited to the particular illustrated shapes of regions, but are to include deviations in shapes that result from, for instance, manufacturing. For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and/or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Likewise, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place. Thus, the regions illustrated in the drawings are schematic in nature and their shapes are not intended to illustrate the actual shape of a region of a device and are not intended to be limiting. Additionally, as those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention.
In the following description, for the purposes of explanation, numerous specific details are set forth to provide a thorough understanding of various embodiments. It is apparent, however, that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form in order to avoid unnecessarily obscuring various embodiments.
It will be understood that, although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section described below could be termed a second element, component, region, layer or section, without departing from the spirit and scope of the present invention.
Spatially relative terms, such as “beneath,” “below,” “lower,” “under,” “above,” “upper,” and the like, may be used herein for ease of explanation to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or in operation, in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as “below” or “beneath” or “under” other elements or features would then be oriented “above” the other elements or features. Thus, the example terms “below” and “under” can encompass both an orientation of above and below. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being arranged “on” a second part, this indicates that the first part is arranged at an upper side or a lower side of the second part without the limitation to the upper side thereof on the basis of the gravity direction.
It will be understood that when an element, layer, region, or component is referred to as being “on,” “connected to,” or “coupled to” another element, layer, region, or component, it can be directly on, connected to, or coupled to the other element, layer, region, or component, or one or more intervening elements, layers, regions, or components may be present. However, “directly connected/directly coupled” refers to one component directly connecting or coupling another component without an intermediate component. Meanwhile, other expressions describing relationships between components such as “between,” “immediately between” or “adjacent to” and “directly adjacent to” may be construed similarly. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present disclosure. As used herein, the singular forms “a” and “an” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises,” “comprising,” “have,” “having,” “includes,” and “including,” when used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
As used herein, the term “substantially,” “about,” “approximately,” and similar terms are used as terms of approximation and not as terms of degree, and are intended to account for the inherent deviations in measured or calculated values that would be recognized by those of ordinary skill in the art. “About” or “approximately,” as used herein, is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value. Further, the use of “may” when describing embodiments of the present disclosure refers to “one or more embodiments of the present disclosure.” As used herein, the terms “use,” “using,” and “used” may be considered synonymous with the terms “utilize,” “utilizing,” and “utilized,” respectively. Also, the term “exemplary” is intended to refer to an example or illustration.
When a certain embodiment may be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially at the same time or performed in an order opposite to the described order.
Also, any numerical range disclosed and/or recited herein is intended to include all sub-ranges of the same numerical precision subsumed within the recited range. For example, a range of “1.0 to 10.0” is intended to include all subranges between (and including) the recited minimum value of 1.0 and the recited maximum value of 10.0, that is, having a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limitation recited herein is intended to include all lower numerical limitations subsumed therein, and any minimum numerical limitation recited in this specification is intended to include all higher numerical limitations subsumed therein. Accordingly, Applicant reserves the right to amend this specification, including the claims, to expressly recite any sub-range subsumed within the ranges expressly recited herein. All such ranges are intended to be inherently described in this specification such that amending to expressly recite any such subranges would comply with the requirements of 35 U.S.C. § 112(a) and 35 U.S.C. § 132(a).
The electronic or electric devices and/or any other relevant devices or components according to embodiments of the present disclosure described herein may be implemented utilizing any suitable hardware, firmware (e.g. an application-specific integrated circuit), software, or a combination of software, firmware, and hardware. For example, the various components of these devices may be formed on one integrated circuit (IC) chip or on separate IC chips. Further, the various components of these devices may be implemented on a flexible printed circuit film, a tape carrier package (TCP), a printed circuit board (PCB), or formed on one substrate. Further, the various components of these devices may be a process or thread, running on one or more processors, in one or more computing devices, executing computer program instructions and interacting with other system components for performing the various functionalities described herein. The computer program instructions are stored in a memory which may be implemented in a computing device using a standard memory device, such as, for example, a random access memory (RAM). The computer program instructions may also be stored in other non-transitory computer readable media such as, for example, a CD-ROM, flash drive, or the like. Also, a person of skill in the art should recognize that the functionality of various computing devices may be combined or integrated into a single computing device, or the functionality of a particular computing device may be distributed across one or more other computing devices without departing from the spirit and scope of the embodiments of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present inventive concept belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and/or the present specification, and should not be interpreted in an idealized or overly formal sense, unless expressly so defined herein.
Referring to
The timing controller 110a receives an image signal and an image control signal from a host system, such as an external application processor (AP). For example, the image signal may include a red image signal, a green image signal, a blue image signal, and the like. For example, the image control signal may include a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, and the like. The data enable signal may be an indicator indicating whether the image signal is transmitted or not. The vertical synchronization signal may be an indicator indicating the start or end of the image frame constituting each viewpoint of a moving picture. The horizontal synchronization signal may be an indicator for indicating the start or end of each pixel row constituting the image frame.
The timing controller 110a may convert the image signal and the image control signal into a data signal DATA, a data control signal DCS, a scan control signal SCS, or the like according to specifications of the data driver 130a and the scan driver 120a. The timing controller 110a may transmit the data signal DATA and the data control signal DCS to the data driver 130a, and may transmit the scan control signal SCS to the scan driver 120a.
The scan driver 120a supplies scan signals through scan lines S1, S2, S3, S4, . . . , Sn−1, and Sn to the respective pixel rows of the display unit 140a. The scan driver 120a may be composed of scan stage circuits connected in the form of a shift register. Each scan stage circuit may be connected to a corresponding scan line S1 to Sn. The scan control signal SCS may include, for example, a clock signal and a scan start signal. When the first scan stage circuit operates in accordance with the clock signal responding to the scan start signal as a start point to generate a scan signal of a turn-on level, each of the second scan stage circuit and the subsequent scan stage circuits generates a scan signal responding to the scan signal of the turn-on level of the previous scan stage circuit as the scan start signal. The scan signal of the turn-on level refers to a scan signal of a voltage level capable of turning on a scan transistor of each pixel.
The data driver 130a supplies data voltages to the pixel columns of the display unit 140a through data lines D1, D2, D3, D4, . . . , and Dm. The data control signal DCS may include, for example, a clock signal, a sampling start signal, a data output signal, or the like. The data driver 130a may sample the received data signal DATA in accordance with the clock signal responding to the sampling start signal as a start point, may convert the data signal DATA into the corresponding data voltages in accordance with the specification of the display unit 140a, and may sequentially output the data voltages in units of pixel rows responding to the data output signal.
The display unit 140a includes pixels connected to at least one of the data lines D1 to Dm and at least one of the scan lines S1 to Sn. By the scan signal of the turn-on level, pixels of the pixel row connected to the corresponding scan line are selected, and the data voltages are input to the selected pixels so that the selected pixels emit light at the corresponding grayscales.
In the embodiment, the pixels of the display unit 140a may be grouped into pixel groups PG1a, PG2a, . . . . Each pixel group may include the same number of pixels. For example, the first pixel group PG1a includes a first pixel PX1a, a second pixel PX2a, a third pixel PX3a, and a fourth pixel PX4a, and the second pixel group PG2a includes a first pixel PX1a′, a second pixel PX2a′, a third pixel PX3a′, and a fourth pixel PX4a′. The first pixels PX1a and PX1a′ of the pixel groups PG1a and PG2a may have the same pixel circuit structure as one another. Furthermore, the second pixels PX2a and PX2a′ of the pixel groups PG1a and PG2a may have the same pixel circuit structure as one another. The third pixels PX3a and PX3a′ of the pixel groups PG1a and PG2a may have the same pixel circuit structure as one another. The fourth pixels PX4a and PX4a′ of the pixel groups PG1a and PG2a may have the same pixel circuit structure as one another.
The first pixel group PG1a and the second pixel group PG2a may be positioned adjacent to each other. For example, when the display unit 140a is in a matrix form, the first pixel group PG1a and the second pixel group PG2a may be alternately arranged in the row direction, or may be alternately arranged in the column direction.
For example, in
Hereinafter, for convenience of explanation, a pixel circuit structure and a driving method of each of the pixels PX1a, PX2a, PX3a, and PX4a will be described with reference to the first pixel group PG1a.
Referring to
In the transistor T1a, one electrode is connected to the data line D1, the other electrode is connected to a first node N1a, and the gate electrode is connected to the scan line S1. The transistor T1a may be referred to as a scan transistor.
In the first light-emitting diode LD1a, the anode is connected to the first node N1a, and the cathode is connected to a reference voltage line VrefL. The first light-emitting diode LD1a is a light-emitting diode of a first color.
In the second light-emitting diode LD2a, the anode is connected to the reference voltage line VrefL, and the cathode is connected to the first node N1a. The second light-emitting diode LD2a is a light-emitting diode of a second color.
The first color and the second color may be different colors from each other. The color may be defined by an emission wavelength, a bandgap of the light-emitting diode, or the like. For example, if the first color is green, the second color may be blue or red. Similarly, if the first color is red, the second color may be blue or green, and if the first color is blue, the second color may be green or red. Each color can be determined differently depending on the product.
As shown in
The light-emitting diodes may be nano light-emitting diodes (nano-LEDs). The nano-LED, for example, has a size of several microns, so that about 10 to about 20 nano-LEDs may be arranged per pixel. The material of the nano-LED may be similar to that of general LEDs. For example, a plurality of nano-LEDs may be fabricated from one LED wafer by sequentially stacking a non-doped GaN layer, a GaN layer doped with n-type impurities, a quantum well, and a GaN layer doped with p-type impurities on a sapphire substrate, or the like, and by then etching and separating them. These nano-LEDs may be dispersed in a solvent and made into a nano-LED ink, and they may then be applied to a pixel circuit by using a slit coating or an inkjet printing method. An appropriate electric field may be applied to the pixel circuit to align the nano LEDs in the desired polarity direction.
In
Referring to
In the transistor T2a, one electrode is connected to the data line D1, the other electrode is connected to a second node N2a, and the gate electrode is connected to the scan line S2. The transistor T2a may be referred to as a scan transistor.
In the third light-emitting diode LD3a, the anode is connected to the reference voltage line VrefL and the cathode is connected to the second node N2a. The third light-emitting diode LD3a is a light-emitting diode of the first color.
In the fourth light-emitting diode LD4a, the anode is connected to the second node N2a, and the cathode is connected to the reference voltage line VrefL. The fourth light-emitting diode LD4a is a light-emitting diode of the second color.
As shown in
Referring to
In the transistor T3a, one electrode is connected to the data line D2, the other electrode is connected to a third node N3a, and the gate electrode is connected to the scan line S1. The transistor T3a may be referred to as a scan transistor.
In the fifth light-emitting diode LD5a, the anode is connected to the third node N3a, and the cathode is connected to the reference voltage line VrefL. The fifth light-emitting diode LD5a is a light-emitting diode of a third color.
The third color is different from the first color and the second color. For example, if the third color is blue, the first color and the second color may be green and red, or red and green. Similarly, when the third color is green, the first color and the second color may be blue and red, or red and blue. Similarly, when the third color is red, the first color and the second color may be green and blue, or blue and green.
As shown in
Referring to
In the transistor T4a, one electrode is connected to the data line D2, the other electrode is connected to a fourth node N4a, and the gate electrode is connected to the scan line S2. The transistor T4a may be referred to as a scan transistor.
In the sixth light-emitting diode LD6a, the anode is connected to the fourth node N4a, and the cathode is connected to the reference voltage line VrefL. The sixth light-emitting diode LD6a is a light-emitting diode of the third color.
As shown in
Hereinafter, only the signals applied to the first to fourth pixels PX1a to PX4a of the first pixel group PG1a in two image frames will be described for convenience of explanation.
The first image frame may be an odd image frame, and the second image frame may be an even image frame. Therefore, the display device 10a may display an image to the user by displaying the first image frame and the second image frame alternately over time.
First, in the first image frame, the scan signal of the turn-on level (low level) is supplied through the scan line S1. Thus, the transistor T1a of the first pixel PX1a is turned on to connect the data line D1 and the first node N1a, and the transistor T3a of the third pixel PX3a is turned on to connect the data line D2 and the third node N3a.
Accordingly, a data voltage DS1ao applied to the data line D1 is applied to the anode of the first light-emitting diode LD1a of the first pixel PX1a, and a reference voltage Vref applied to the reference voltage line VrefL is applied to the cathode of the first light-emitting diode LD1a. Because the polarity of the data voltage DS1ao is positive with respect to the reference voltage Vref, the first light-emitting diode LD1a emits light at a grayscale corresponding to the potential difference between the data voltage DS1ao and the reference voltage Vref.
On the other hand, because the reference voltage Vref is applied to the anode of the second light-emitting diode LD2a of the first pixel PX1a, and the data voltage DS of the positive polarity with respect to the reference voltage Vref is applied to the cathode of the second light-emitting diode LD2a, a reverse voltage is applied to the second light-emitting diode LD2a, and no light is emitted from the second light-emitting diode LD2a.
Accordingly, the first pixel PX1a of the first image frame emits light of a first color A.
Also, a data voltage DS3ao applied to the data line D2 is applied to the anode of the fifth light-emitting diode LD5a of the third pixel PX3a, and the reference voltage Vref applied to the reference voltage line VrefL is applied to the cathode of the fifth light-emitting diode LD5a. Therefore, the fifth light-emitting diode LD5a emits light at a grayscale corresponding to the potential difference between the data voltage DS3ao and the reference voltage Vref.
Accordingly, the third pixel PX3a of the first image frame emits light of a third color C.
Next, in the first image frame, the scan signal of the turn-on level (low level) is supplied through the scan line S2. The transistor T2a of the second pixel PX2a is turned on to connect the data line D1 to the second node N2a, and the transistor T4a of the fourth pixel PX4a is turned on to connect the data line D2 and the fourth node N4a.
Therefore, the data voltage DS2ao applied to the data line D1 is applied to the anode of the fourth light-emitting diode LD4a of the second pixel PX2a, and the reference voltage Vref applied to the reference voltage line VrefL is applied to the cathode of the fourth light-emitting diode LD4a. Because the polarity of the data voltage DS2ao is positive with respect to the reference voltage Vref, the fourth light-emitting diode LD4a emits light at a grayscale corresponding to the potential difference between the data voltage DS2ao and the reference voltage Vref.
On the other hand, the reference voltage Vref is applied to the anode of the third light-emitting diode LD3a of the second pixel PX2a, and the data voltage DS2ao of the positive polarity with respect to the reference voltage Vref is applied to the cathode of the third light-emitting diode LD3a, so that a reverse voltage is applied to the third light-emitting diode LD3a, and no light is emitted from the third light-emitting diode LD3a.
Accordingly, the second pixel PX2a of the first image frame emits light of a second color B.
On the other hand, the data voltage DS4ao applied to the data line D2 is applied to the anode of the sixth light-emitting diode LD6a of the fourth pixel PX4a, and the reference voltage Vref applied to the reference voltage line VrefL. Therefore, the sixth light-emitting diode LD6a emits light at a grayscale corresponding to the potential difference between the data voltage DS4ao and the reference voltage Vref.
Accordingly, the fourth pixel PX4a of the first image frame emits light of the third color C.
Similarly, in the first image frame, the first pixel PX1a′ of the second pixel group PG2a emits light of the first color A, the second pixel PX2a′ emits light of the second color B, the third pixel PX3a′ emits light of the third color C, and the fourth pixel PX4a′ emits light of the third color C.
According to the present embodiment, because light of the first color, the second color, and the third color are concurrently or simultaneously emitted from the pixel groups PG1a, PG2a, . . . of the first image frame, the color-breakup phenomenon does not occur. The color-breakup phenomenon refers to, for example, among all three colors, light of two or less colors is emitted in one frame, and light of two or fewer different colors is emitted in the next frame, so that the color difference between one frame and the next frame is perceived by the user.
In addition, according to the present embodiment, because the color arrangement of the first pixel group PG1a and the color arrangement of the second pixel group PG2a that is most adjacent to the first pixel group PG1a are vertically opposite to each other, the color-breakup phenomenon may be further prevented.
In addition, according to the embodiment, because each of the first and second pixels includes a plurality of light-emitting diodes of plural colors in one pixel circuit, the total area of the pixel circuits is reduced, so that the display device 10a may be manufactured with a higher resolution.
Next, in the second image frame, the scan signal of the turn-on level (low level) is supplied again through the scan line S1. Thus, the transistor T1a of the first pixel PX1a is turned on to connect the data line D1 and the first node N1a, and the transistor T3a of the third pixel PX3a is turned on to connect the data line D2 and the third node N3a.
Therefore, the data voltage DS1ae applied to the data line D1 is applied to the anode of the first light-emitting diode LD1a of the first pixel PX1a, and the reference voltage Vref applied to the reference voltage line VrefL is applied to the cathode of the first light-emitting diode LD1a. Because the polarity of the data voltage DS1ae is negative with respect to the reference voltage Vref, the first light-emitting diode LD1a does not emit light in accordance with the reverse potential difference.
On the other hand, because the reference voltage Vref is applied to the anode of the second light-emitting diode LD2a of the first pixel PX1a, and the data voltage DS of the negative polarity with respect to the reference voltage Vref is applied to the cathode of the second light-emitting diode LD2a, the second light-emitting diode LD2a emits light at a grayscale corresponding to the potential difference between the reference voltage Vref and the data voltage DS1ae.
Accordingly, the first pixel PX1a of the second image frame emits light of the second color B. That is, the polarity of the voltage applied to the first node N1a is alternated with respect to the reference voltage Vref applied to the reference voltage line VrefL in units of image frames, so that the first pixel PX1a emits light of the first color A in the first image frame, and emits light of the second color B in the second image frame.
On the other hand, the data voltage DS3ae applied to the data line D2 is applied to the anode of the fifth light-emitting diode LD5a of the third pixel PX3a, and the reference voltage Vref applied to the reference voltage line VrefL is applied to the cathode of the fifth light-emitting diode LD5a. Therefore, the fifth light-emitting diode LD5a emits light at a grayscale corresponding to the potential difference between the data voltage DS3ae and the reference voltage Vref.
Accordingly, the third pixel PX3a of the second image frame emits light of the third color C. That is, the polarity of the voltage applied to the third node N3a is maintained with reference to the reference voltage Vref applied to the reference voltage line VrefL in units of image frames, so that the third pixel PX3a emits light of the third color C in both the first image frame and the second image frame.
Next, in the second image frame, the scan signal of the turn-on level (low level) is supplied through the scan line S2. The transistor T2a of the second pixel PX2a is turned on to connect the data line D1 and the second node N2a, and the transistor T4a of the fourth pixel PX4a is turned on to connect the data line D2 and the fourth node N4a.
Accordingly, the data voltage DS2ae applied to the data line D1 is applied to the anode of the fourth light-emitting diode LD4a of the second pixel PX2a, and the reference voltage Vref applied to the reference voltage line VrefL is applied to the cathode of the fourth light-emitting diode LD4a. Because the polarity of the data voltage DS2ae is negative with respect to the reference voltage Vref, the fourth light-emitting diode LD4a does not emit light due to a reverse voltage applied thereto.
On the other hand, because the reference voltage Vref is applied to the anode of the third light-emitting diode LD3a of the second pixel PX2a and the data voltage DS2ae of the negative polarity with respect to the reference voltage Vref is applied to the cathode of the third light-emitting diode LD3a, the third light-emitting diode LD3a emits light at a grayscale corresponding to the potential difference between the reference voltage Vref and the data voltage DS2ae.
Accordingly, the second pixel PX2a of the second image frame emits light of the first color A. That is, the polarity of the voltage applied to the second node N2a is alternated with respect to the reference voltage Vref applied to the reference voltage line VrefL in units of image frames, and the second pixel PX2a emits light of the second color B in the first image frame, and emits light of the first color A in the second image frame. According to the embodiment of
On the other hand, the data voltage DS4ae applied to the data line D2 is applied to the anode of the sixth light-emitting diode LD6a of the fourth pixel PX4a, and the reference voltage Vref applied to the reference voltage line VrefL is applied to the cathode of the sixth light-emitting diode LD6a. Accordingly, the sixth light-emitting diode LD6a emits light at a grayscale corresponding to the potential difference between the data voltage DS4ae and the reference voltage Vref.
Therefore, the fourth pixel PX4a of the second image frame emits light of the third color C. That is, the polarity of the voltage applied to the fourth node N4a is maintained with respect to the reference voltage Vref applied to the reference voltage line VrefL in units of image frames, so that the fourth pixel PX4a emits light of the third color C in both the first image frame and the second image frame.
In a similar manner, in the second image frame, the first pixel PX1a′ of the second pixel group PG2a emits light of the second color B, the second pixel PX2a′ emits light of the first color A, the third pixel PX3a′ emits light of the third color C, and the fourth pixel PX4a′ emits light of the third color C.
According to the embodiment, because the color arrangement of each of the pixel groups PG1a and PG2a is vertically reversed in the first image frame and the second image frame, it is possible to further prevent the occurrence of the color-breakup phenomenon.
Referring to
In the transistor T2aS, one electrode is connected to the data line D1, the other electrode is connected to the second node N2aS, and the gate electrode is connected to the scan line S2. The transistor T2aS may be referred to as a scan transistor.
In the third light-emitting diode LD3aS, unlike the embodiment of
In addition, unlike the embodiment of
That is, the second pixel PX2aS of
The driving method of
That is, in
Even if the second pixel PX2aS is designed using the embodiment of
As described above, even if the second pixel PX2aS of
Referring to
Comparing the display device 10b of the second embodiment of
The timing controller 110b further generates an emission control signal ECS and a power control signal PCS. The emission control signal ECS is transmitted to the emission controller 150b, and the power control signal PCS is transmitted to a first switch SW1 and a second switch SW2. Although the power supplier 160b and the switches SW1 and SW2 are separately shown in the present embodiment to clearly show the operation of the device, the switches SW1 and SW2 may also be interpreted as a part of the power supplier 160b. The power control signal PCS may be expressed as being transmitted to the power supplier 160b.
The emission controller 150b is connected to the display unit 140b through first emission control lines Eo1, Eo2, Eo3, Eo4, . . . , Eo(n−1), and Eon, and through second emission control lines Ee1, Ee2, Ee3, Ee4, . . . , Ee(n−1), and Een. The first emission control lines Eo1 to Eon and the second emission control lines Ee1 to Een are connected to the first and second pixels PX1b, PX2b, . . . including a plurality of light-emitting diodes of a plurality of colors. In the present embodiment, the emission control lines are not connected to the third and fourth pixels PX3b, PX4b, . . . including single-color light-emitting diodes. However, in another embodiment, the emission control lines may be connected to the third and fourth pixels PX3b, PX4b, . . . so as to clearly distinguish between the data writing period and the light emitting period.
The power supplier 160b supplies power voltages to the display unit 140b. The power supplier 160b supplies a common low voltage via a common low voltage line QVCOML, and supplies a common high voltage via a common high voltage line QVDDL. In the present embodiment, each of the voltage lines QVCOML and QVDDL supplies a single level voltage for the sake of convenience. However, in another embodiment, the voltage levels of the voltage lines QVCOML and QVDDL may be adjusted in accordance with a luminance condition, a grayscale condition, a temperature condition, or the like to reduce power consumption.
Additionally, a first power voltage line QV1L and a second power voltage line QV2L are also connected to the display unit 140b. The first power voltage line QV1L is connected to the common low voltage line QVCOML through the first switch SW1, and the second power voltage line QV2L is connected to the common low voltage line QVCOML through the second switch SW2.
The first switch SW1 and the second switch SW2 are controlled to be ON/OFF in accordance with the power control signal PCS. The first switch SW1 and the second switch SW2 are alternately turned on and off in units of image frames. For example, when the first switch SW1 is turned on in the first image frame, the second switch SW2 is turned off, and when the second switch SW2 is turned on in the second image frame, the first switch SW1 is turned off. The switch turned on among the switches SW1 and SW2 connects the corresponding power voltage line QV1L or QV2L and the common low voltage line QVCOML, so that the common low voltage is applied to the corresponding power voltage line QV1L or QV2L. Because the switch that is turned off separates the other power voltage line QV1L or QV2L and the common low voltage line QVCOML, the other power voltage line QV1L or QV2L is floated, so that one end of the other power voltage line QV1L or QV2L may be interpreted to be connected to the high impedance Hi-Z. See also
Referring to
In the transistor T11b, one electrode is connected to the data line D1, the other electrode is connected to the gate electrode of the transistor T21b, and the gate electrode is connected to the scan line S1. The transistor T11b may be referred to as a scan transistor.
In the transistor T21b, one electrode is connected to the common high voltage line QVDDL, the other electrode is connected to a fifth node N51b, and the gate electrode is connected to the other electrode of the transistor T11b. The transistor T21b may be referred to as a driving transistor.
In the storage capacitor Cst1b, one electrode is connected to the common high voltage line QVDDL, and the other electrode is connected to the gate electrode of the transistor T21b.
In the first emission control transistor T31b, one electrode is connected to the second power voltage line QV2L, the other electrode is connected to the fifth node N51b, and the gate electrode is connected to the first emission control line Eo1.
In the second emission control transistor T41b, one electrode is connected to the first power voltage line QV1L, the other electrode is connected to the fifth node N51b, and the gate electrode is connected to the second emission control line Ee1.
In the first light-emitting diode LD1b, the cathode is connected to the first power voltage line QV1L, and the anode is connected to the second power voltage line QV2L. The first light-emitting diode LD1b may be a light-emitting diode of the first color A.
In the second light-emitting diode LD2b, the cathode is connected to the second power voltage line QV2L, and the anode is connected to the first power voltage line QV1L. The second light-emitting diode LD2b may be a light-emitting diode of the second color B. As described above, the first color A and the second color B are different colors.
As shown in
Referring to
In the transistor T12b, one electrode is connected to the data line D1, the other electrode is connected to the gate electrode of the transistor T22b, and the gate electrode is connected to the scan line S2. The transistor T12b may be referred to as a scan transistor.
In the transistor T22b, one electrode is connected to the common high voltage line QVDDL, the other electrode is connected to a fifth node N52b, and the gate electrode is connected to the other electrode of the transistor T12b. The transistor T22b may be referred to as a driving transistor.
In the storage capacitor Cst2b, one electrode is connected to the common high voltage line QVDDL, and the other electrode is connected to the gate electrode of the transistor T22b.
In the first emission control transistor T32b, one electrode is connected to the second power voltage line QV2L, the other electrode is connected to the fifth node N52b, and the gate electrode is connected to the first emission control line Eo2.
In the second emission control transistor T42b, one electrode is connected to the first power voltage line QV1L, the other electrode is connected to the fifth node N52b, and the gate electrode is connected to the second emission control line Ee2.
In the third light-emitting diode LD3b, the cathode is connected to the second power voltage line QV2L, and the anode is connected to the first power voltage line QV1L. The third light-emitting diode LD3b may be a light-emitting diode of the first color A.
In the fourth light-emitting diode LD4b, the cathode is connected to the first power voltage line QV1L, and the anode is connected to the second power voltage line QV2L. The fourth light-emitting diode LD4b may be a light-emitting diode of the second color B.
As shown in
Referring to
In the transistor T13b, one electrode is connected to the data line D2, the other electrode is connected to the gate electrode of the transistor T23b, and the gate electrode is connected to the scan line S1. The transistor T13b may be referred to as a scan transistor.
In the transistor T23b, one electrode is connected to the common high voltage line QVDDL, the other electrode is connected to the anode of the fifth light-emitting diode LD5b, and the gate electrode is connected to the other electrode of the storage capacitor Cst3b. The transistor T23b may be referred to as a driving transistor.
In the storage capacitor Cst3b, one electrode is connected to the common high voltage line QVDDL, and the other electrode is connected to the gate electrode of the transistor T23b.
In the fifth light-emitting diode LD5b, the anode is connected to the other electrode of the transistor T23b, and the cathode is connected to the common low voltage line QVCOML. The fifth light-emitting diode LD5b may be a light-emitting diode of the third color C. As described above, the third color C is different from the first color A and the second color B.
In
Referring to
In the transistor T14b, one electrode is connected to the data line D2, the other electrode is connected to the gate electrode of the transistor T24b, and the gate electrode is connected to the scan line S2. The transistor T14b may be referred to as a scan transistor.
In the transistor T24b, one electrode is connected to the common high voltage line QVDDL, the other electrode is connected to the anode of the sixth light-emitting diode LD6b, and the gate electrode is connected to the other electrode of the storage capacitor Cst4b. The transistor T24b may be referred to as a driving transistor.
In the storage capacitor Cst4b, one electrode is connected to the common high voltage line QVDDL, and the other electrode is connected to the gate electrode of the transistor T24b.
In the sixth light-emitting diode LD6b, the anode is connected to the other electrode of the transistor T24b, and the cathode is connected to the common low voltage line QVCOML. The sixth light-emitting diode LD6b may be a light-emitting diode of the third color C.
As shown in
Referring to
First, as mentioned above by referring to
The scan signal of the turn-on level (low level) is supplied through the scan line S1 during a period t1 to t2. Thus, the transistor T11b of the first pixel PX1b is turned on to connect the data line D1 and the other electrode of the storage capacitor Cst1b. The storage capacitor Cst1b records, or stores, the potential difference between the common high voltage QVDD applied to the common high voltage line QVDDL and the data voltage DS1bo applied to the data line D1.
Similarly, during the same period t1 to t2, the transistor T13b of the third pixel PX3b is turned on to connect the data line D2 and the other electrode of the storage capacitor Cst3b. The storage capacitor Cst3b records, or stores, the potential difference between the common high voltage QVDD applied to the common high voltage line QVDDL and the data voltage DS3bo applied to the data line D2.
Next, the scan signal of the turn-on level (low level) is supplied through the scan line S2 in a period t3 to t4. Thus, the transistor T12b of the second pixel PX2b is turned on to connect the data line D1 to the other electrode of the storage capacitor Cst2b. The storage capacitor Cst2b records the potential difference between the common high voltage QVDD applied to the common high voltage line QVDDL and the data voltage DS2bo applied to the data line D1.
Similarly, during the same period t3 to t4, the transistor T14b of the fourth pixel PX4b is turned on to connect the data line D2 and the other electrode of the storage capacitor Cst4b. The storage capacitor Cst4b records the potential difference between the common high voltage QVDD applied to the common high voltage line QVDDL and the data voltage DS4bo applied to the data line D2.
Next, the emission control signal of the turn-on level (low level) is supplied through the first emission control lines Eo1, Eo2, . . . at a time t5. Thus, the first emission control transistor T31b of the first pixel PX1b is turned on. Because the transistor T21b is turned on in accordance with the potential difference recorded in the storage capacitor Cst1b, a driving current path through the common high voltage line QVDDL, the transistor T21b, the first emission control transistor T31b, the first light-emitting diode LD1b, and the first power voltage line QV1L is formed. Accordingly, the first light-emitting diode LD1b emits light at a grayscale corresponding to the driving current depending on the potential difference recorded in the storage capacitor Cst1b. The second light-emitting diode LD2b does not emit light because the corresponding driving current path is not formed. Accordingly, the first pixel PX1b emits light of the first color A in the first image frame.
Similarly, the first emission control transistor T32b of the second pixel PX2b is turned on. Because the transistor T22b is turned on in accordance with the potential difference recorded in the storage capacitor Cst2b, a driving current path through the common high voltage line QVDDL, the transistor T22b, the first emission control transistor T32b, the fourth light-emitting diode LD4b, and the first power voltage line QV1L is formed. Therefore, the fourth light-emitting diode LD4b emits light at a grayscale corresponding to the driving current depending on the potential difference recorded in the storage capacitor Cst2b. The third light-emitting diode LD3b does not emit light because the corresponding driving current path is not formed. Therefore, the second pixel PX2b emits light of the second color B in the first image frame.
Because each of the third pixel PX3b and the fourth pixel PX4b includes only a single-color light-emitting diode, each of the pixels PX3b and PX4b emits light of the third color C in the first image frame.
At a time t6, the emission control signal of the turn-off level (high level) may be supplied through the first emission control lines Eo1, Eo2, . . . . Therefore, the first pixel PX1b and the second pixel PX2b do not emit light. However, because the light emissions of the third pixel PX3b and the fourth pixel PX4b of this embodiment are not separately controlled (e.g., with emission control transistors), they may be in a continuous light emitting state.
Next, as mentioned above by referring to
The scan signal of the turn-on level (low level) is supplied through the scan line S1 during the period t7 to t8. Thus, the transistor T11b of the first pixel PX1b is turned on to connect the data line D1 and the other electrode of the storage capacitor Cst1b. The storage capacitor Cst1b records the potential difference between the common high voltage QVDD applied to the common high voltage line QVDDL and the data voltage DS1be applied to the data line D1.
Similarly, during the same period t7 to t8, the transistor T13b of the third pixel PX3b is turned on to connect the data line D2 and the other electrode of the storage capacitor Cst3b. The storage capacitor Cst3b records the potential difference between the common high voltage QVDD applied to the common high voltage line QVDDL and the data voltage DS3be applied to the data line D2.
Next, the scan signal of the turn-on level (low level) is supplied through the scan line S2 in the period t9 to t10. Thus, the transistor T12b of the second pixel PX2b is turned on to connect the data line D1 to the other electrode of the storage capacitor Cst2b. The storage capacitor Cst2b records the potential difference between the common high voltage QVDD applied to the common high voltage line QVDDL and the data voltage DS2be applied to the data line D1.
Similarly, during the same period t9 to t10, the transistor T14b of the fourth pixel PX4b is turned on to connect the data line D2 and the other electrode of the storage capacitor Cst4b. The storage capacitor Cst4b records the potential difference between the common high voltage QVDD applied to the common high voltage line QVDDL and the data voltage DS4be applied to the data line D2.
Next, the emission control signal of the turn-on level (low level) is supplied through the second emission control lines Ee1, Ee2, . . . at a time t11. Thus, the second emission control transistor T41b of the first pixel PX1b is turned on. Because the transistor T21b is turned on in accordance with the potential difference recorded in the storage capacitor Cst1b, a driving current path through the common high voltage line QVDDL, the transistor T21b, the second emission control transistor T41b, the second light-emitting diode LD2b, and the second power voltage line QV2L is formed. Accordingly, the second light-emitting diode LD2b emits light at a grayscale corresponding to the driving current depending on the potential difference recorded in the storage capacitor Cst1b. The first light-emitting diode LD1b does not emit light because the corresponding driving current path is not formed. Accordingly, the first pixel PX1b emits light of the second color B in the second image frame.
Similarly, the second emission control transistor T42b of the second pixel PX2b is turned on. Because the transistor T22b is turned on in accordance with the potential difference recorded in the storage capacitor Cst2b, a driving current path through the common high voltage line QVDDL, the transistor T22b, the second emission control transistor T42b, the third light-emitting diode LD3b, and the second power voltage line QV2L is formed. Therefore, the third light-emitting diode LD3b emits light at a grayscale corresponding to the driving current depending on the potential difference recorded in the storage capacitor Cst2b. The fourth light-emitting diode LD4b does not emit light because the corresponding driving current path is not formed. Therefore, the second pixel PX2b emits light of the first color A in the second image frame.
Because each of the third pixel PX3b and the fourth pixel PX4b includes only a single-color light-emitting diode, each of the pixels PX3b and PX4b emits light of the third color C in the second image frame.
At a time t12, the emission control signal of the turn-off level (high level) may be supplied through the second emission control lines Ee1, Ee2, . . . . Therefore, the first pixel PX1b and the second pixel PX2b do not emit light. However, because the light emissions of the third pixel PX3b and the fourth pixel PX4b of this embodiment are not separately controlled, they may be in a continuous light emitting state.
The display device according to the present disclosure may reduce or prevent color-breakup while achieving a high resolution because one pixel may include light-emitting elements of a plurality of colors.
Example embodiments have been disclosed herein, and although specific terms are employed, they are used and are to be interpreted in a generic and descriptive sense only and not for purpose of limitation. In some instances, as would be apparent to one of ordinary skill in the art as of the filing of the present application, features, characteristics, and/or elements described in connection with a particular embodiment may be used singly or in combination with features, characteristics, and/or elements described in connection with other embodiments unless otherwise specifically indicated. Accordingly, it will be understood by those of skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present disclosure as set forth in the following claims, with functional equivalents thereof to be included.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2018-0015620 | Feb 2018 | KR | national |
