Patent Application
20240212538
The present invention relates to a display device including a semiconductor chip mounted in a frame region arranged around a display region of a display panel in order to supply a video signal to a plurality of pixels arranged in the display region.
There is known a display device including a semiconductor chip mounted in a frame region arranged around a liquid crystal display portion in order to supply a video signal to a plurality of liquid crystal display pixels arranged in the liquid crystal display portion of a liquid crystal panel (PTL 1). A vertical drive circuit is arranged under this semiconductor chip.
The following problem occurs when a circuit such as a video protection circuit that needs to be arranged in each of a plurality of pixels arranged in a display region is arranged under a semiconductor chip (chip on plastic (COP)) mounted on a display panel.
A large number of COP terminals are formed on the back side of the COP. Since a panel terminal to be joined to the COP terminal is arranged at a position where the COP terminal exists, the circuit cannot be arranged. For this reason, when the region where the COP terminals do not exist on the back side of the COP is narrow, the region where the circuit is arranged becomes narrow, and there arises a problem that the arrangement of the circuit becomes difficult.
An object of one aspect of the present invention is to provide a display device in which a circuit that needs to be arranged in each of a plurality of pixels arranged in a display region can be appropriately arranged in a display panel.
In order to solve the above problem, a display device according to one aspect of the present invention includes: a semiconductor chip mounted in a frame region arranged around a display region in which a plurality of pixels of a display panel are formed; and a peripheral circuit formed in the frame region, in which the peripheral circuit includes an off-chip division circuit formed between the semiconductor chip and the display region, and an under-chip division circuit formed under the semiconductor chip.
According to one aspect of the present invention, in a display panel, a circuit that needs to be arranged in each of a plurality of pixels arranged in a display region can appropriately be arranged.
The display device 1 includes a semiconductor chip 2 mounted in a frame region 8 arranged around a display region 7 in order to supply a video signal to a plurality of pixels arranged in the display region 7 of a display panel 6, and the video protection circuit 3 (peripheral circuit) formed in the frame region 8 in order to protect the pixels of the display region 7 before the semiconductor chip 2 is mounted in the frame region 8.
The video protection circuit 3 includes a low power supply connection portion 4 (video protection circuit, first potential circuit, off-chip division circuit, and peripheral circuit) formed between the semiconductor chip 2 and the display region 7 and a high power supply connection portion 5 (video protection circuit, second potential circuit, under-chip division circuit, and peripheral circuit) formed under the semiconductor chip 2. The low power supply connection portion 4 is connected to a low power supply (first potential power supply) having a first potential. The high power supply connection portion 5 is connected to a high power supply (second potential power supply) having a second potential higher than the first potential.
The semiconductor chip 2 includes, on a lower surface facing the display panel 6, a plurality of input terminals 24 formed on the opposite side of the display region 7 and a plurality of output terminals 25 formed on the display region 7 side. The plurality of input terminals 24 are arrayed along an X direction corresponding to a longitudinal direction of the semiconductor chip 2. The plurality of output terminals 25 are arrayed along the X direction corresponding to the longitudinal direction of the semiconductor chip 2. The display panel 6 includes the panel terminal portion 9 to which the plurality of input terminals 24 and the plurality of output terminals 25 of the semiconductor chip 2 are each joined
The panel terminal portion 9 includes an input terminal portion 12 for supplying an input signal to the input terminals 24 of the semiconductor chip 2 and an output terminal portion 13 for receiving a video signal output from the output terminals 25 of the semiconductor chip 2. The high power supply connection portion 5 is arranged between the input terminal portion 12 and the output terminal portion 13.
The output terminal portion 13 includes a plurality of panel terminals 14R arrayed along the X direction for receiving, from the semiconductor chip 2, a video signal corresponding to a pixel that emits red light, a plurality of panel terminals 14G arrayed along the X direction for receiving a video signal corresponding to a pixel that emits green light, and a plurality of panel terminals 14B arrayed along the X direction for receiving a video signal corresponding to a pixel that emits blue light. The plurality of panel terminals 14R, the plurality of panel terminals 14G, and the plurality of panel terminals 14B are arrayed in a staggered array in which the panel terminals are arrayed obliquely to one another.
The video protection circuit 3 is provided to protect, from static electricity entering through the panel terminals 14R, the panel terminals 14G, or the panel terminals 14B, the pixel circuit of the display region 7, the pixel circuits for controlling the pixels.
In the low power supply connection portion 4, low power supply connection circuits 15R, 15G, and 15B (video protection circuit, first potential circuit, off-chip division circuit, and peripheral circuit) are repeatedly arrayed in this order along the X direction. These low power supply connection circuits 15R, 15G, and 15B are connected to a low power supply line 18 that is common and coupled to the low power supply.
The low power supply connection circuit 15R is connected to a pixel that emits red light of the display region 7 and a pixel circuit for controlling the pixel. The low power supply connection circuit 15G is connected to a pixel that emits green light and a pixel circuit for controlling the pixel. The low power supply connection circuit 15B is connected to a pixel that emits blue light and a pixel circuit for controlling the pixel.
In the high power supply connection portion 5, high power supply connection circuits 16R, 16G, and 16B (video protection circuit, second potential circuit, under-chip division circuit, and peripheral circuit) are repeatedly arrayed in this order along the X direction. These high power supply connection circuits 16R, 16G, and 16B are connected to a high power supply line 17 that is common and coupled to the high power supply.
The panel terminal 14R is connected to the low power supply connection circuit 15R arranged outside the semiconductor chip 2 via a wiring line B, and is connected to the high power supply connection circuit 16R arranged under the semiconductor chip 2 via a wiring line C. Then, the low power supply connection circuit 15R is connected to the pixel for emitting red light of the display region 7 via a wiring line A.
Similarly, the panel terminal 14G is connected to the low power supply connection circuit 15G via the wiring line B, and is connected to the high power supply connection circuit 16G via the wiring line C. Then, the low power supply connection circuit 15G is connected to the pixel for emitting green light of the display region 7 via the wiring line A. Similarly, the panel terminal 14B is connected to the low power supply connection circuit 15B via the wiring line B, and is connected to the high power supply connection circuit 16G via the wiring line C. Then, the low power supply connection circuit 15B is connected to the pixel for emitting blue light of the display region 7 via the wiring line A.
The input terminal portion 12, the output terminal portion 13, and the high power supply connection portion 5 are arranged in a region R3 under the semiconductor chip 2. The low power supply connection portion 4 and the display region 7 are arranged in a region R4 outside the semiconductor chip 2.
The video protection circuit 3 is divided into the high power supply connection portion 5 and the low power supply connection portion 4. The high power supply connection portion 5 is arranged between the input terminal portion 12 and the output terminal portion 13 under the semiconductor chip 2. The low power supply connection portion 4 is arranged between the output terminal portion 13 and the display region 7.
The low power supply connection portion 4 includes a protective resistor R1 whose electric resistance value is defined by the length of the wiring line B, and the low power supply connection circuits 15R, 15G, and 15B. The high power supply connection portion 5 includes a protective resistor R2 whose electric resistance value is defined by the length of the wiring line C, and the high power supply connection circuits 16R, 16G, and 16B.
As described above, in the video protection circuit 93 according to the comparative example, the high power supply connection circuit and the low power supply connection circuit are integrated, and provided between the semiconductor chip 2 and the display region 7.
When static electricity of +200 V enters through the panel terminals 14R, 14G, and 14B, the entered static electricity flows to the high power supply through the protective resistor R and the high power supply connection circuits 16R, 16G, and 16B as indicated by an arrow A1 in
The video protection circuit 93 is preferably arranged between the output terminal portion 13 and the display region 7, but there is a problem that the frame region 8 becomes wider. Therefore, when an attempt is made to arrange the video protection circuit 93 under the semiconductor chip 2, there is a problem that the video protection circuit 93 cannot be collectively arranged in a case where there is no margin in the region between the input terminal portion 12 and the output terminal portion 13.
Even in a case where the video protection circuit 93 according to the comparative example cannot collectively be arranged because there is no margin in the region under the semiconductor chip 2, the video protection circuit 3 according to the present embodiment is divided into the low power supply connection portion 4 and the high power supply connection portion 5, the high power supply connection portion 5 is arranged under the semiconductor chip 2, and the low power supply connection portion 4 is arranged outside the semiconductor chip 2.
By dividing the video protection circuit 93 into the low power supply connection portion 4 and the high power supply connection portion 5, the low power supply connection portion 4 and the high power supply connection portion 5 of the video protection circuit 3 can be laid out smaller than those by dividing the video protection circuit 93 for each video terminal (signal). One of the reasons is that the power supply lines (the low power supply line 18 and the high power supply line 17) connected to each power supply can be reduced to one type (one line) in each of the circuits of the low power supply connection portion 4 and the high power supply connection portion 5.
The purpose of the video protection circuit 3 is to prevent static electricity from entering other circuits and pixels by causing static electricity to flow through the low power supply line 18 and the high power supply line 17 in a case where the static electricity actually enters from the panel terminals 14R, 14G, and 14B. Therefore, it is desirable to make the wiring line widths of the low power supply line 18 and the high power supply line 17 as wide as possible to reduce the resistance. Therefore, reducing the number of the low power supply line 18 and the high power supply line 17 can greatly contribute to widening of the wiring line widths of the low power supply line 18 and the high power supply line 17.
If the low power supply connection portion 4 and the high power supply connection portion 5 can be laid out smaller, they can be accommodated in a small arrangement region, and the distance from the output terminal portion 13 becomes long, and therefore the protective resistors R1 and R2 can be increased, and the withstand voltage of the video protection circuit 3 can be improved.
In a manufacturing process in which it is known in advance whether static electricity having a high frequency of entering through the panel terminals 14R, 14G, and 14B is static electricity on the high power supply side or static electricity on the low power supply side, one of the low power supply connection portion 4 and the high power supply connection portion 5 corresponding to the one having a high frequency may be arranged outside the semiconductor chip 2 farther from the panel terminals 14R, 14G, and 14B, and the other of the low power supply connection portion 4 and the high power supply connection portion 5 corresponding to the one having a low frequency may be arranged under the semiconductor chip 2 closer to the panel terminals 14R, 14G, and 14B. This improves the withstand voltage of the low power supply connection portion 4 and the high power supply connection portion 5.
For example, as illustrated in
When the video protection circuit 3 is divided into the low power supply connection portion 4 and the high power supply connection portion 5, a circuit width D2 of the high power supply connection portion 5 under the semiconductor chip 2 becomes narrower than that in a case where the video protection circuit 3 is not divided. Therefore, a distance D1 between the output terminal portion 13 of the panel terminal portion 9 and the high power supply connection portion 5 can be increased. Therefore, the protective resistor R2 between the panel terminals 14R, 14G, and 14B of the output terminal portion 13 and the high power supply connection circuits 16R, 16G, and 16B of the high power supply connection portion 5 can be further increased, and the withstand voltage of the high power supply connection portion 5 can be improved well.
Since the semiconductor chip 2 is small or the peripheral circuit such as the video protection circuit 3 including a thin film transistor is large, in a case where the peripheral circuit including the thin film transistor cannot be arranged to overlap the semiconductor chip 2, it is conceivable that the peripheral circuit including the thin film transistor is divided, a part of the peripheral divided circuit is arranged to overlap the semiconductor chip 2, and the rest is arranged at a position not overlapping the semiconductor chip 2. At that time, the video protection circuit 3 is not divided for each video terminal (signal), but divided into a circuit connected to the high power supply side and a circuit connected to the low power supply side. This enables the circuit to be laid out small.
The high power supply connection circuits 16R, 16G, and 16B (peripheral circuit elements) may be arrayed in accordance with a staggered array in which the panel terminals are arrayed obliquely to one another in accordance with a distance D3 between the output terminal portion 13 and the input terminal portion 12.
The pixels arrayed in the display region 7 are self-luminous display elements and are preferably organic light emitting diodes (OLEDs), but a liquid crystal display element can also achieve the same effect.
Note that the same effect can be achieved by arranging the low power supply connection portion 4 under the semiconductor chip 2 and arranging the high power supply connection portion 5 between the semiconductor chip 2 and the display region 7.
The display device 1A includes a semiconductor chip 2 mounted in a frame region 8 arranged around a display region 7 in order to supply a video signal to a plurality of pixels arranged in the display region 7 of a display panel 6, and the panel inspection circuit 19 (peripheral circuit) formed in the frame region 8 in order to inspect the pixels of the display region 7 before the semiconductor chip 2 is mounted in the frame region 8.
The panel inspection circuit 19 supplies, to the pixel and the pixel circuit for controlling the pixel, a signal for inspecting the operation of the pixel before the semiconductor chip 2 is mounted.
Each pixel arranged in the display region 7 includes the first subpixel 23R for emitting red (first luminescent color) light, the second subpixel 23G for emitting green (second luminescent color) light, and the third subpixel 23B for emitting blue (third luminescent color) light. The first subpixels 23R, the second subpixels 23G, and the third subpixels 23B are arrayed in accordance with the configuration of RB/G by subpixel rendering (SPR) as illustrated in
The panel inspection circuit 19 includes the first luminescent color inspection circuit 20 (panel inspection circuit and peripheral circuit) that supplies a first data signal for inspecting the operation of the first subpixels 23R to the first subpixels 23R, the second luminescent color inspection circuit 21 (panel inspection circuit and peripheral circuit) that supplies a second data signal for inspecting the operation of the second subpixels 23G to the second subpixels 23G, and the third luminescent color inspection circuit 22 (panel inspection circuit and peripheral circuit) that supplies a third data signal for inspecting the operation of the third subpixels 23B to the third subpixels 23B.
The first luminescent color inspection circuit 20 and the third luminescent color inspection circuit 22 are arranged between the semiconductor chip 2 and the display region 7. The second luminescent color inspection circuit 21 is arranged between the output terminal portion 13 and the input terminal portion 12 under the semiconductor chip 2.
A plurality of the first luminescent color inspection circuits 20 and a plurality of the third luminescent color inspection circuits 22 are alternately arrayed along the X direction outside the semiconductor chip 2. A supply line T_DATA(R) for supplying the first data signal to the first luminescent color inspection circuit 20 is provided in common for the plurality of first luminescent color inspection circuits 20. A supply line T_DATA(B) for supplying the third data signal to the third luminescent color inspection circuit 22 is provided in common for the plurality of third luminescent color inspection circuits 22.
A plurality of the second luminescent color inspection circuits 21 are arrayed along the X direction under the semiconductor chip 2. A supply line T_DATA(G) for supplying the second data signal to the second luminescent color inspection circuit 21 is provided in common for the plurality of second luminescent color inspection circuits 21.
The plurality of panel terminals 14R, the plurality of panel terminals 14G, and the plurality of panel terminals 14B are arrayed in a staggered array in which the panel terminals are arrayed obliquely to one another.
The panel terminal 14R is connected to the first luminescent color inspection circuit 20. The first luminescent color inspection circuit 20 is connected to the first subpixel 23R arranged in the display region 7. The panel terminal 14B is connected to the third luminescent color inspection circuit 22. The third luminescent color inspection circuit 22 is connected to the third subpixel 23B arranged in the display region 7.
The panel terminal 14G is connected to the second luminescent color inspection circuit 21 and the second subpixels 23G arranged in the display region 7.
The second luminescent color inspection circuits 21 (peripheral circuit element) may be arrayed in accordance with a staggered array in which the panel terminals are arrayed obliquely to one another in accordance with a distance D3 between the output terminal portion 13 and the input terminal portion 12.
The panel inspection circuit 19 includes the first luminescent color inspection circuit 20 and the third luminescent color inspection circuit 22 alternately arrayed along the X direction outside the semiconductor chip 2, and the second luminescent color inspection circuit 21 arrayed along the X direction under the semiconductor chip 2. The panel inspection circuit 89 according to the comparative example includes the first luminescent color inspection circuit 20, the second luminescent color inspection circuit 21, and the third luminescent color inspection circuit 22 arrayed along the X direction. When a signal for turning on the transistor is input to a wiring line TSMP in a state before the semiconductor chip 2 is mounted, a video signal is input to each of the data lines T_DATA(R), T_DATA(G), and T_DATA(B), display in the first subpixel 23R, the second subpixel 23G, and the third subpixel 23B arranged in the display region 7 becomes possible, and inspection of the first subpixel 23R, the second subpixel 23G, and the third subpixel 23B becomes possible.
In a case where the entire panel inspection circuit 89 cannot be collectively arranged under the semiconductor chip 2 because there is no margin in the region under the semiconductor chip 2, the panel inspection circuit 89 is divided and arranged for each luminescent color of the corresponding subpixel as in the panel inspection circuit 19. That is, the panel inspection circuit 19 has the first luminescent color inspection circuit 20 corresponding to the first subpixel 23R that emits red light and the third luminescent color inspection circuit 22 corresponding to the third subpixel 23B that emits blue light arranged between the semiconductor chip 2 and the display region 7 outside the semiconductor chip 2. Then, the panel inspection circuit 19 has the second luminescent color inspection circuit 21 corresponding to the second subpixel 23G that emits green light arranged under the semiconductor chip 2.
In the display region 7 of the display panel 6, the first subpixels 23R that emit red light, the second subpixels 23G that emit green light, and the third subpixels 23B that emit blue light are arrayed as illustrated in
The first luminescent color inspection circuit 20, the second luminescent color inspection circuit 21, and the third luminescent color inspection circuit 22 are arrayed such that the sum of the numbers of the first luminescent color inspection circuits 20 and the third luminescent color inspection circuits 22 corresponds to the number of the second luminescent color inspection circuits 21 so as to match the first subpixels 23R, the second subpixels 23G, and the third subpixels 23B. Therefore, the number of the second luminescent color inspection circuits 21 under the semiconductor chip 2 and the sum of the number of the first luminescent color inspection circuits 20 and the number of the third luminescent color inspection circuits 22 outside the semiconductor chip 2 can be made substantially the same.
As described above, when the panel inspection circuit 19 is divided on an RB pixel side and a G pixel side, the panel inspection circuit 19 can be laid out smaller than that when divided for each video terminal (signal). One of the reasons is that a test video signal supply wiring line can be made to one type the RB pixel side and the G pixel side.
When the panel inspection circuit 19 is divided into an even-numbered video terminal (signal) and an odd-numbered video terminal (signal), three types of test video signal supply wiring lines of RGB are required on both the even-numbered side and the odd-numbered side, and hence the panel inspection circuit 19 cannot be laid out smaller.
In a case where each of the panel inspection circuits on the RB pixel side and the G pixel side performs a panel inspection, particularly in a case where an AC signal is input, it is desirable that the wiring line width for the test video signal is as wide as possible and the resistance is reduced. Therefore, reducing the number of test video signal supply wiring lines can greatly contribute to widening of the wiring line width.
In particular, as in the example illustrated in
Since the panel inspection circuit 19 also has an element capable of releasing static electricity as in the video protection circuit 3, an effect similar to that of the video protection circuit 3 can be expected.
As an effect of arranging the second luminescent color inspection circuit 21 of the panel inspection circuit 19 having a narrow circuit width under the semiconductor chip 2, since the circuit width D2 of the second luminescent color inspection circuit 21 can be made narrower than that of the comparative example, the distance D1 from the output terminal portion 13 to the second luminescent color inspection circuit 21 of the panel inspection circuit 19 can be secured longer. By securing a long distance from the panel terminal 14G to the second luminescent color inspection circuit 21 of the panel inspection circuit 19, it is assumed that the resistance from the panel terminal 14G to the second luminescent color inspection circuit 21 can be increased more, and the withstand voltage is improved more.
The present invention is not limited to each of the embodiments described above, and various modifications may be made within the scope of the claims. Embodiments obtained by appropriately combining technical approaches disclosed in each of the different embodiments also fall within the technical scope of the present invention. Furthermore, novel technical features can be formed by combining the technical approaches disclosed in each of the embodiments.
| Filing Document | Filing Date | Country | Kind |
|---|---|---|---|
| PCT/JP2021/021904 | 6/9/2021 | WO |
