Patent Application
20250095575
This application claims priority to Korean Patent Application No. 10-2023-0124651, filed on Sep. 19, 2023, and all the benefits accruing therefrom under 35 USC § 119, the content of which in its entirety is herein incorporated by reference.
The present invention relates to a display device, and more particularly to a display device in which an emission time of a light emitting element of a pixel is controlled.
A display device may display an image by driving a light emitting element, such as a micro light emitting diode (μLED) or an organic light emitting diode (OLED), in a pulse amplitude modulation (PAM) method or a pulse width modulation (PWM) method. In the PAM method, a gray level may be represented by adjusting an amount (or an amplitude) of a driving current provided to the light emitting element. In the PWM method, the gray level may be represented by adjusting a time (or a pulse width) during which the driving current is provided to the light emitting element.
A wavelength of light emitted by the μLED may be shifted according to the amount of the driving current. Thus, in a case where the light emitting element such as the μLED is driven in the PAM method, a color shift phenomenon may occur, and the image may be distorted.
Some embodiments provide a display device capable of having an improved image quality.
According to embodiments, there is provided a display device including a plurality of pixels. Each of the plurality of pixels includes a light emitting element, an initialization circuit configured to provide a first initialization voltage to a first node, a data writing circuit configured to provide a data voltage to a second node, a ramp generating circuit configured to provide a ramp voltage to the first node in response to an enable signal, a comparator configured to generate an emission signal by comparing the ramp voltage at the first node and the data voltage at the second node, and a driving circuit configured to provide a constant current to the light emitting element in response to the emission signal.
In an embodiment, an emission time of the light emitting element of each of the plurality of pixels may be determined according to a voltage level of the data voltage for each of the plurality of pixels.
In an embodiment, the plurality of pixels may include the ramp generating circuits.
In an embodiment, the ramp generating circuit may include a ramp current source configured to generate a ramp current, a ramp enable transistor connected in series with the ramp current source, and configured to selectively provide the ramp current generated by the ramp current source to the first node in response to the enable signal, and a ramp capacitor connected to the first node, and configured to generate the ramp voltage based on the ramp current.
In an embodiment, the ramp current source may include a ramp current transistor configured to generate the ramp current based on a ramp bias voltage. Gates of the ramp current transistors of the plurality of pixels may be connected to a same line for transferring the ramp bias voltage.
In an embodiment, the display device may further include a reference ramp current source, and a reference ramp current transistor connected in series with the reference ramp current source, the reference ramp current transistor including a drain and a gate connected to each other. The ramp current source may include a ramp current transistor configured to generate the ramp current. Gates of the ramp current transistors of the plurality of pixels may be connected to the gate of the reference ramp transistor.
In an embodiment, the initialization circuit may include a first initialization transistor configured to transfer the first initialization voltage to the first node.
In an embodiment, the initialization circuit may further include a second initialization transistor configured to transfer a second initialization voltage to the second node.
In an embodiment, the data writing circuit may include at least one of a first data writing transistor for transferring the data voltage to the second node in response to a writing signal, and a second data writing transistor for transferring the data voltage to the second node in response to an inverted writing signal.
In an embodiment, the data writing circuit may further include a storage capacitor connected to the second node, and configured to store the data voltage.
In an embodiment, the driving circuit may include a constant current source configured to generate the constant current, and an emission transistor configured to selectively provide the constant current generated by the constant current source to the light emitting element in response to the emission signal.
In an embodiment, the driving circuit may further include at least one driving enable transistor connected in series with the emission transistor, the at least one driving enable transistor being selectively turned on in response to the enable signal or an inverted enable signal.
In an embodiment, the ramp voltage may gradually decrease in a sweep period in which the enable signal has a high level, wherein the comparator may generate the emission signal having a low level when the ramp voltage is higher than the data voltage, the driving circuit may include an emission transistor that is turned on while the emission signal has the low level, and an emission time of the light emitting element may start at a start time point of the sweep period, and may end when a voltage level of the ramp voltage becomes equal to a voltage level of the data voltage.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node, and a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to the second node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the first node, and a second terminal, a ramp current source connected between the second terminal of the ramp enable transistor and a line for transferring a second power supply voltage, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the second node, a negative input terminal connected to the first node, and an output terminal for outputting the emission signal. The driving circuit may include a constant current source connected to a line for transferring a first power supply voltage, a first driving enable transistor including a gate for receiving an inverting enable signal, a first terminal connected to the constant current source, and a second terminal, an emission transistor including a gate for receiving the emission signal, a first terminal connected to the second terminal of the first driving enable transistor, and a second terminal, and a second driving enable transistor including a gate for receiving the enable signal, a first terminal connected to the second terminal of the emission transistor, and a second terminal. The light emitting element may include an anode connected to the second terminal of the second driving enable transistor, and a cathode connected to the line for transferring the second power supply voltage.
In an embodiment, a frame period may include an initialization period in which the initialization signal has a high level, and the enable signal and the writing signal have a low level, a data writing period in which the writing signal has the high level, and the enable signal and the initialization signal have the low level, and a sweep period in which the enable signal has the high level, and the initialization signal and the writing signal have the low level. In the initialization period, the first initialization transistor may provide the first initialization voltage to the first node in response to the enable signal having the low level, and the second initialization transistor may provide the second initialization voltage to the second node in response to the initialization signal having the high level. In the data write period, the first data writing transistor may provide the data voltage to the second node in response to the writing signal having the high level, the second data writing transistor may provide the data voltage to the second node in response to the inverted writing signal having the low level, and the storage capacitor may store the data voltage at the second node. In the sweep period, the ramp enable transistor may provide a ramp current generated by the ramp current source to the ramp capacitor in response to the enable signal having the high level, the ramp capacitor may provide the first node with the ramp voltage that gradually decreases from the first initialization voltage based on the ramp current, the comparator may generate the emission signal having the low level during an emission time from a start time point of the sweep period to a time point at which the ramp voltage becomes the data voltage, the first driving enable transistor may be turned on in response to the inverted enable signal having the low level, the second driving enable transistor may be turned on in response to the enable signal having the high level, the emission transistor may be turned on in response to the emission signal having the low level during the emission time, and the light emitting element may emit light based on the constant current generated by the constant current source during the emission time.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the first node, and a second terminal, a ramp current source connected between the second terminal of the ramp enable transistor and a line for transferring a second power supply voltage, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the second node, a negative input terminal connected to the first node, and an output terminal for outputting the emission signal. The driving circuit may include a constant current source connected to a line for transferring a first power supply voltage, a first driving enable transistor including a gate for receiving an inverting enable signal, a first terminal connected to the constant current source, and a second terminal, an emission transistor including a gate for receiving the emission signal, a first terminal connected to the second terminal of the first driving enable transistor, and a second terminal, and a second driving enable transistor including a gate for receiving the enable signal, a first terminal connected to the second terminal of the emission transistor, and a second terminal. The light emitting element may include an anode connected to the second terminal of the second driving enable transistor, and a cathode connected to the line for transferring the second power supply voltage. In the initialization period of a current frame period, a voltage of the second node may be maintained as the data voltage in a previous frame period.
In an embodiment, the ramp voltage may gradually decrease in a sweep period in which the enable signal has a high level, the comparator may generate the emission signal having the high level when the ramp voltage is higher than the data voltage, the driving circuit may include an emission transistor that is turned on while the emission signal has the high level, and an emission time of the light emitting element may start at a start time point of the sweep period, and may end when a voltage level of the ramp voltage becomes equal to a voltage level of the data voltage.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node, and a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to the second node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the first node, and a second terminal, a ramp current source connected between the second terminal of the ramp enable transistor and a line for transferring a second power supply voltage, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the first node, a negative input terminal connected to the second node, and an output terminal for outputting the emission signal. The driving circuit may include a first driving enable transistor including a gate for receiving an inverting enable signal, a first terminal, and a second terminal, an emission transistor including a gate for receiving the emission signal, a first terminal connected to the second terminal of the first driving enable transistor, and a second terminal, a second driving enable transistor including a gate for receiving the enable signal, a first terminal connected to the second terminal of the emission transistor, and a second terminal, and a constant current source connected between the second terminal of the second driving enable transistor and the line for transferring the second power supply voltage. The light emitting element may include an anode connected to a line for transferring a first power supply voltage, and a cathode connected to the first terminal of the first driving enable transistor.
In an embodiment, the ramp voltage may gradually increase in a sweep period in which the enable signal has a low level, wherein the comparator may generate the emission signal having the low level when the ramp voltage is lower than the data voltage, the driving circuit may include an emission transistor that is turned on while the emission signal has the low level, and an emission time of the light emitting element may start at a start time point of the sweep period, and may end when a voltage level of the ramp voltage becomes equal to a voltage level of the data voltage.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node, and a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to the second node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp current source connected to a line for transferring a first power supply voltage, a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the ramp current source, and a second terminal connected to the first node, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the first node, a negative input terminal connected to the second node, and an output terminal for outputting the emission signal. The driving circuit may include a constant current source connected to the line for transferring the first power supply voltage, a first driving enable transistor including a gate for receiving the enable signal, a first terminal connected to the constant current source, and a second terminal, an emission transistor including a gate for receiving the emission signal, a first terminal connected to the second terminal of the first driving enable transistor, and a second terminal, and a second driving enable transistor including a gate for receiving an inverted enable signal, a first terminal connected to the second terminal of the emission transistor, and a second terminal. The light emitting element may include an anode connected to the second terminal of the second driving enable transistor, and a cathode connected to a line for transferring a second power supply voltage.
In an embodiment, the ramp voltage may gradually increase in a sweep period in which the enable signal has a low level, the comparator may generate the emission signal having a high level when the ramp voltage is lower than the data voltage, the driving circuit may include an emission transistor that is turned on while the emission signal has the high level, and an emission time of the light emitting element may start at a start time point of the sweep period, and may end when a voltage level of the ramp voltage becomes equal to a voltage level of the data voltage.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node, and a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to the second node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp current source connected to a line for transferring a first power supply voltage, a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the ramp current source, and a second terminal connected to the first node, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the second node, a negative input terminal connected to the first node, and an output terminal for outputting the emission signal. The driving circuit may include a first driving enable transistor including a gate for receiving the enable signal, a first terminal, and a second terminal, an emission transistor including a gate for receiving the emission signal, a first terminal connected to the second terminal of the first driving enable transistor, and a second terminal, a second driving enable transistor including a gate for receiving an inverted enable signal, a first terminal connected to the second terminal of the emission transistor, and a second terminal, and a constant current source connected between the second terminal of the second driving enable transistor and a line for transferring a second power supply voltage. The light emitting element may include an anode connected to the line for transferring the first power supply voltage, and a cathode connected to the first terminal of the first driving enable transistor.
In an embodiment, the ramp voltage may gradually decrease in a sweep period in which the enable signal has a high level, wherein the comparator may generate the emission signal having a low level when the ramp voltage is lower than the data voltage, the driving circuit may include an emission transistor that is turned on while the emission signal has the low level, and an emission time of the light emitting element may start when a voltage level of the ramp voltage becomes equal to a voltage level of the data voltage, and may end at an end time point of the sweep period.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node, and a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to the second node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the first node, and a second terminal, a ramp current source connected between the second terminal of the ramp enable transistor and a line for transferring a second power supply voltage, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the first node, a negative input terminal connected to the second node, and an output terminal for outputting the emission signal. The driving circuit may include a constant current source connected to a line for transferring a first power supply voltage, and an emission transistor including a gate for receiving the emission signal, a first terminal connected to the constant current source, and a second terminal. The light emitting element may include an anode connected to the second terminal of the emission transistor, and a cathode connected to the line for transferring the second power supply voltage.
In an embodiment, a frame period may include an initialization period in which the initialization signal has a high level, and the enable signal and the writing signal have a low level, a data writing period in which the writing signal has the high level, and the enable signal and the initialization signal have the low level, and a sweep period in which the enable signal has the high level, and the initialization signal and the writing signal have the low level. In the initialization period, the first initialization transistor may provide the first initialization voltage to the first node in response to the enable signal having the low level, and the second initialization transistor may provide the second initialization voltage to the second node in response to the initialization signal having the high level. In the data write period, the first data writing transistor may provide the data voltage to the second node in response to the writing signal having the high level, the second data writing transistor may provide the data voltage to the second node in response to the inverted writing signal having the low level, and the storage capacitor may store the data voltage at the second node. In the sweep period, the ramp enable transistor may provide a ramp current generated by the ramp current source to the ramp capacitor in response to the enable signal having the high level, the ramp capacitor may provide the first node with the ramp voltage that gradually decreases from the first initialization voltage based on the ramp current, the comparator may generate the emission signal having the low level during an emission time from a time point at which the ramp voltage becomes the data voltage to an end time point of the sweep period, the emission transistor may be turned on in response to the emission signal having the low level during the emission time, and the light emitting element may emit light based on the constant current generated by the constant current source during the emission time.
In an embodiment, the ramp voltage may gradually decrease in a sweep period in which the enable signal has a high level, wherein the comparator may generate the emission signal having the high level when the ramp voltage is lower than the data voltage, the driving circuit may include an emission transistor that is turned on while the emission signal has the high level, and an emission time of the light emitting element may start when a voltage level of the ramp voltage becomes equal to a voltage level of the data voltage, and may end at an end time point of the sweep period.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node, and a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to the second node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the first node, and a second terminal, a ramp current source connected between the second terminal of the ramp enable transistor and a line for transferring a second power supply voltage, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the second node, a negative input terminal connected to the first node, and an output terminal for outputting the emission signal. The driving circuit may include an emission transistor including a gate for receiving the emission signal, a first terminal, and a second terminal, and a constant current source connected between the second terminal of the emission transistor and the line for transferring the second power supply voltage. The light emitting element may include an anode connected to a line for transferring a first power supply voltage, and a cathode connected to the first terminal of the emission transistor.
In an embodiment, the ramp voltage may gradually increase in a sweep period in which the enable signal has a low level, wherein the comparator may generate the emission signal having the low level when the ramp voltage is higher than the data voltage, the driving circuit may include an emission transistor that is turned on while the emission signal has the low level, and an emission time of the light emitting element may start when a voltage level of the ramp voltage becomes equal to a voltage level of the data voltage, and may end at an end time point of the sweep period.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node, and a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to the second node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp current source connected to a line for transferring a first power supply voltage, a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the ramp current source, and a second terminal connected to the first node, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the second node, a negative input terminal connected to the first node, and an output terminal for outputting the emission signal. The driving circuit may include a constant current source connected to the line for transferring the first power supply voltage, and an emission transistor including a gate for receiving the emission signal, a first terminal connected to the constant current source, and a second terminal. The light emitting element may include an anode connected to the second terminal of the emission transistor, and a cathode connected to a line for transferring a second power supply voltage.
In an embodiment, the ramp voltage may gradually increase in a sweep period in which the enable signal has a low level, wherein the comparator may generate the emission signal having a high level when the ramp voltage is higher than the data voltage, the driving circuit may include an emission transistor that is turned on while the emission signal has the high level, and an emission time of the light emitting element may start when a voltage level of the ramp voltage becomes equal to a voltage level of the data voltage, and may end at an end time point of the sweep period.
In an embodiment, the initialization circuit may include a first initialization transistor including a gate for receiving the enable signal, a first terminal for receiving the first initialization voltage, and a second terminal connected to the first node, and a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to the second node. The data writing circuit may include a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, and a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage. The ramp generating circuit may include a ramp current source connected to a line for transferring a first power supply voltage, a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the ramp current source, and a second terminal connected to the first node, and a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage. The comparator may include a positive input terminal connected to the first node, a negative input terminal connected to the second node, and an output terminal for outputting the emission signal. The driving circuit may include an emission transistor including a gate for receiving the emission signal, a first terminal, and a second terminal, and a constant current source connected between the second terminal of the emission transistor and a line for transferring a second power supply voltage. The light emitting element may include an anode connected to the line for transferring the first power supply voltage, and a cathode connected to the first terminal of the emission transistor.
According to an embodiment, there is provided a display device including a plurality of pixels. Each of the plurality of pixels includes a first initialization transistor including a gate for receiving an enable signal, a first terminal for receiving a first initialization voltage, and a second terminal connected to a first node, a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to a second node, a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage, a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the first node, and a second terminal, a ramp current source connected between the second terminal of the ramp enable transistor and a line for transferring a second power supply voltage, a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage, a comparator including a positive input terminal connected to the second node, a negative input terminal connected to the first node, and an output terminal for outputting an emission signal, a constant current source connected to a line for transferring a first power supply voltage, a first driving enable transistor including a gate for receiving an inverting enable signal, a first terminal connected to the constant current source, and a second terminal, an emission transistor including a gate for receiving the emission signal, a first terminal connected to the second terminal of the first driving enable transistor, and a second terminal, a second driving enable transistor including a gate for receiving the enable signal, a first terminal connected to the second terminal of the emission transistor, and a second terminal, and a light emitting element including an anode connected to the second terminal of the second driving enable transistor, and a cathode connected to the line for transferring the second power supply voltage.
According to an embodiment, there is provided a display device including a plurality of pixels. Each of the plurality of pixels includes a first initialization transistor including a gate for receiving an enable signal, a first terminal for receiving a first initialization voltage, and a second terminal connected to a first node, a second initialization transistor including a gate for receiving an initialization signal, a first terminal for receiving a second initialization voltage, and a second terminal connected to a second node, a first data writing transistor including a gate for receiving a writing signal, a first terminal connected to a data line, and a second terminal connected to the second node, a second data writing transistor including a gate for receiving an inverted writing signal, a first terminal connected to the data line, and a second terminal connected to the second node, a storage capacitor including a first electrode connected to the second node, and a second electrode for receiving a ground voltage, a ramp enable transistor including a gate for receiving the enable signal, a first terminal connected to the first node, and a second terminal, a ramp current source connected between the second terminal of the ramp enable transistor and a line for transferring a second power supply voltage, a ramp capacitor including a first electrode connected to the first node, and a second electrode for receiving the ground voltage, a comparator including a positive input terminal connected to the first node, a negative input terminal connected to the second node, and an output terminal for outputting an emission signal, a constant current source connected to a line for transferring a first power supply voltage, an emission transistor including a gate for receiving the emission signal, a first terminal connected to the constant current source, and a second terminal, and a light emitting element including an anode connected to the second terminal of the emission transistor, and a cathode connected to the line for transferring the second power supply voltage.
As described above, in a display device according to an embodiment, a driving circuit of each pixel may provide a constant (or fixed) current to a light emitting element. Accordingly, a color shift phenomenon may be prevented in the display device. Further, in the display device, according to an embodiment, each pixel may include a ramp generating circuit that generates a ramp voltage. Accordingly, image quality deterioration due to a distortion of the ramp voltage may be prevented in the display device.
Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.
Hereinafter, embodiments of the invention will be explained in detail with reference to the accompanying drawings, in which various embodiments are shown. This invention may, however, be embodied in many different forms, and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It will be understood that when an element (or a region, a layer, a portion, or the like) is referred to as being related to another such as being “on”, “connected to” or “coupled to” another element, it may be directly disposed on, connected or coupled to the other element, or intervening elements may be disposed therebetween.
Like reference numerals or symbols refer to like elements throughout. In the drawings, the thickness, the ratio, and the size of the element are exaggerated for effective description of the technical contents. As used herein, the term “and/or” includes any and all combinations of one or more of the associated listed items.
The term “and/or,” includes all combinations of one or more of which associated configurations may define.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the scope of the invention. Similarly, a second element, component, region, layer or section may be termed a first element, component, region, layer or section. As used herein, the singular forms, “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.
Also, terms of “below”, “on lower side”, “above”, “on upper side”, or the like may be used to describe the relationships of the elements illustrated in the drawings. These terms have relative concepts and are described on the basis of the directions indicated in the drawings.
It will be further understood that the terms “comprise”, “includes” and/or “have”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, being “disposed directly on” may mean that there is no additional layer, film, region, plate, or the like between a part and another part such as a layer, a film, a region, a plate, or the like. For example, being “disposed directly on” may mean that two layers or two members are disposed without using an additional member such as an adhesive member, therebetween.
“About” or “approximately” as used herein is inclusive of the stated value and means within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, considering the measurement in question and the error associated with measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” can mean within one or more standard deviations, or within ±30%, 20%, 10% or 5% of the stated value.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
In an embodiment and referring to
In an embodiment, the initialization circuit 110 may initialize a first node N1 by providing a first initialization voltage VINT1 to the first node N1. In some embodiments, the initialization circuit 110 may further initialize a second node N2 by providing a second initialization voltage VINT2 to the second node N2. Here, the first node N1 may be a ramp node NRAMP to which a ramp voltage is provided, and the second node N2 may be a data node NDAT to which a data voltage is provided. In some embodiments, the first initialization voltage VINT1 may be a first power supply voltage VDD (e.g., a high power supply voltage), and the second initialization voltage VINT2 may be a second power supply voltage VSS (e.g. a low power supply voltage). In other embodiments, the first initialization voltage VINT1 may be different from the first power supply voltage VDD, and the second initialization voltage VINT2 may be different from the second power supply voltage VSS. For example, the first initialization voltage VINT1 may be less than or equal to the first power supply voltage VDD and higher than or equal to a highest data voltage, and the second initialization voltage VINT2 may be higher than or equal to the second power supply voltage VSS and lower than or equal to a lowest data voltage.
In an embodiment, the initialization circuit 110 may include a first initialization transistor INTT1 for transferring the first initialization voltage VINT1 to the first node N1, and a second initialization transistor INTT2 for transferring the second initialization voltage VINT2 to the second node N2. In the pixel 100 of
In an embodiment, in a pixel 100a of
In an embodiment, as described below with reference to
In an embodiment, the data writing circuit 130 may provide a data voltage of a data line DL to the second node N2, and may store the data voltage at the second node N2. In an embodiment, as illustrated in
In an embodiment, as illustrated in
In an embodiment, as illustrated in
In an embodiment, the ramp generating circuit 150 may provide a ramp voltage to the first node N1 in response to the enable signal EN. In some embodiments, as illustrated in
In an embodiment and as illustrated in
In an embodiment, as illustrated in
In an embodiment, as illustrated in
In an embodiment, the first reference high power supply voltage VDD_REF1 may have a voltage level substantially the same as a voltage level of the first power supply voltage VDD, or may have a voltage level different from the voltage level of the first power supply voltage VDD. Further, in a case where the first reference high power supply voltage VDD_REF1 and the first power supply voltage VDD have substantially the same voltage level, the first reference high power supply voltage VDD_REF1 and the first power supply voltage VDD may be transferred through the same line, or may be transferred through different lines. In some embodiments, the first reference low power supply voltage VSS_REF1 may have a voltage level substantially the same as a voltage level of the second power supply voltage VSS. Further, the first reference low power supply voltage VSS_REF1 and the second power supply voltage VSS may be transferred through the same line, or may be transferred through different lines. Meanwhile,
In an embodiment, in a conventional display device, a single ramp generating circuit provides a ramp voltage to a plurality of pixels. In this case, a ramp voltage may be distorted due to signal delay in a line for transferring the ramp voltage, and image quality may deteriorate. However, in the display device, according to embodiments, the plurality of pixels may respectively include the ramp generating circuits. Thus, since the ramp voltage is not transferred through external lines connected to the plurality of pixels, the distortion of the ramp voltage due to the signal delay may not occur, and the deterioration of image quality due to the distortion of the ramp voltage may be prevented.
In an embodiment, the comparator 170 may generate an emission signal EM by comparing the ramp voltage at the first node N1 and the data voltage at the second node N2. In some embodiments, as illustrated in
In an embodiment, as illustrated in
In an embodiment, as illustrated in
In an embodiment, although
In an embodiment, the driving circuit 190 may provide a constant (or fixed) current to the light emitting element LED in response to the emission signal EM. The driving circuit 190 may include a constant current source CCS that generates the constant current, and an emission transistor EMT that is disposed between the constant current source CCS and the light emitting element LED and that selectively connects the constant current source CCS to the light emitting element LED in response to the emission signal EM. In some embodiments, the emission transistor EMT may be implemented as a PMOS transistor. In this case, the emission transistor EMT may be turned on while the emission signal EM has a low level.
In an embodiment, the driving circuit 190 may further include at least one driving enable transistor DET1 and DET2 that is selectively turned on in response to the enable signal EN or an inverted enable signal ENB. In some embodiments, as illustrated in
In an embodiment, as illustrated in
In an embodiment, as illustrated in
Further, in an embodiment, as illustrated in
In an embodiment, as illustrated in
In an embodiment, gates of the constant current transistors CCT′ of the plurality of pixels may be connected to the gate of the reference constant current transistor RCCT. For example, the gates of the constant current transistors CCT′ of all pixels may be connected to the gate of the reference constant current transistor RCCT. In another example, the display device may include red, green and blue reference constant current sources and red, green and blue reference constant current transistors respectively connected thereto, the constant current transistors CCT′ of the red pixels may be connected to the same red reference current source, the constant current transistors CCT′ of the green pixels may be connected to the same green reference constant current transistor, and the constant current transistors CCT′ of the blue pixels may be connected to the same blue reference constant current transistor.
In an embodiment, the second reference high power supply voltage VDD_REF2 may have a voltage level substantially the same as the first power supply voltage VDD. Further, the second reference high power supply voltage VDD_REF2 and the first power supply voltage VDD may be transferred through the same line, or may be transferred through different lines. In some embodiments, the second reference low power supply voltage VSS_REF2 may have a voltage level substantially the same as a voltage level of the second power supply voltage VSS, or may have a voltage level different from the voltage level of the second power supply voltage VSS. Further, in a case where the second reference low power supply voltage VSS_REF2 and the second power supply voltage VSS have substantially the same voltage level, the second reference low power supply voltage VSS_REF2 and the second power supply voltage VSS may be transferred through the same line, or may be transferred through different lines. Meanwhile,
In an embodiment, a conventional display device, an amount of a driving current provided to a light emitting element is adjusted according to a gray level indicated by image data or a voltage level of the data voltage. However, a wavelength of light emitted by the light emitting element such as a micro light emitting diode is shifted according to the amount of the driving current. Thus, if the driving current provided to the light emitting element is changed, a color shift phenomenon may occur, and an image may be distorted. However, in the display device according to embodiments, the driving circuit 190 of each pixel 100 may provide the constant (or fixed) current to the light emitting element LED by using the constant current source CCS. Accordingly, the color shift phenomenon may be prevented in the display device according to embodiments.
In an embodiment, the light emitting element LED may emit light based on the constant current provided by the driving circuit 190. For example, as illustrated in
In an embodiment and as described above, in the display device the driving circuit 190 of each pixel 100 may provide the constant current to the light emitting element LED. Accordingly, the color shift phenomenon may be prevented in the display device, according to embodiments. Further, in the display device according to embodiments, each pixel 100 may include the ramp generating circuit 150 that generates the ramp voltage. Accordingly, the deterioration of image quality due to the distortion of the ramp voltage may be prevented in the display device according to embodiments.
In an embodiment and referring to
In an embodiment, in the initialization period INTP, an initialization signal GI may have a high level, and an enable signal EN and a writing signal GW may have a low level. Thus, as illustrated in
In an embodiment, in the data writing period DWP, the writing signal GW may have the high level, and the enable signal EN and the initialization signal GI may have the low level. Thus, as illustrated in
In an embodiment, In the sweep period SWP, the enable signal EN may have the high level, and the initialization signal GI and the writing signal GW may have the low level. Thus, as illustrated in
In an embodiment, during the emission time ET in which the ramp voltage VRAMP applied to the negative input terminal of the comparator 170 is higher than the data voltage VDAT applied to the positive input terminal of the comparator 170, the comparator 170 may generate the emission signal EM having the low level (“L”). That is, the comparator 170 may the emission signal EM having the low level (“L”) during the emission time ET from a start time point of the sweep period SWP to a time point at which the ramp voltage VRAMP becomes the data voltage VDAT. Further, the first driving enable transistor DET1 may be turned on in response to an inverted enable signal ENB having the low level, the second driving enable transistor DET2 may be turned on in response to the enable signal EN having the high level, and the emission transistor EMT may be turned on in response to the emission signal EM having the low level (“L”) during the emission time ET. Accordingly, during the emission time ET, the constant current source CCS may be connected to the light emitting element LED, and thus a current ILED applied to the light emitting element LED may be the constant current CC generated by the constant current source CCS. Thus, the light emitting element LED may emit light based on the constant current CC generated by the constant current source CCS during the emission time ET. As described above, since the emission time ET of the light emitting element LED ends at the time point when a voltage level of the ramp voltage VRAMP becomes a voltage level of the data voltage VDAT, a time length of the emission time ET may be determined according to the voltage level of the data voltage VDAT. That is, (the time length of) the emission time (ET) of the light emitting element LED of each pixel 100 may be determined according to the voltage level of the data voltage VDAT for the pixel 100. For example, in a case where image data for the pixel 100 represent a relatively high gray level, the data voltage VDAT may have a relatively low voltage level, the emission time ET may be relatively long, and luminance of the pixel 100 may be relatively high. In another embodiment, in a case where the image data for the pixel 100 represents a relatively low gray level, the data voltage VDAT may have a relatively high voltage level, the emission time ET may be relatively short, and the luminance of the pixel 100 may relatively low.
In an embodiment, as illustrated in
In an embodiment and as described above, in the display device, the ramp voltage VRAMP may gradually decrease in the sweep period SWP in which the enable signal EN has the high level, the comparator 170 may generate the emission signal EM having the low level (“L”) when the ramp voltage VRAMP is higher than the data voltage VDAT, and the emission transistor EMT may be implemented as the PMOS transistor that is turned on while the emission signal EM has the low level (“L”). Therefore, the emission time ET of the light emitting element LED may start at the start time point of the sweep period SWP, and may end when the voltage level of the ramp voltage VRAMP becomes equal to the voltage level of the data voltage VDAT.
In an embodiment and referring to
In an embodiment and referring to
In an embodiment, the initialization circuit 210 may include a first initialization transistor INTT1 including a gate for receiving an enable signal EN, a first terminal for receiving a first initialization voltage VINT1, and a second terminal connected to the first node N1, and a second initialization transistor INTT2 including a gate for receiving an initialization signal GI, a first terminal for receiving a second initialization voltage VINT2, and a second terminal connected to the second node N2.
In an embodiment, the data writing circuit 230 may include a first data writing transistor DWT1 including a gate for receiving a writing signal GW, a first terminal connected to a data line DL, and a second terminal connected to the second node N2, a second data writing transistor DWT2 including a gate for receiving an inverted writing signal GWB, a first terminal connected to the data line DL, and a second terminal connected to the second node N2, and a storage capacitor CST including a first electrode connected to the second node N2, and a second electrode for receiving a ground voltage VGND. Although
In an embodiment, the ramp generating circuit 250 may include a ramp enable transistor RET including a gate for receiving the enable signal EN, a first terminal connected to the first node N1, a second terminal, and a ramp current source RCS connected between the second terminal of the ramp enable transistor RET and the line for transferring the second power supply voltage VSS, and a ramp capacitor CR including a first electrode connected to the first node N1, and a second electrode for receiving the ground voltage VGND.
In an embodiment, the comparator 270 may include the positive input terminal (“+”) connected to the first node N1, the negative input terminal (“−”) connected to the second node N2, and an output terminal for outputting an emission signal EM. Thus, in a sweep period SWP, the comparator 270 may generate the emission signal EM having a high level when a ramp voltage VRAMP applied to the positive input terminal is higher than a data voltage VDAT applied to the negative input terminal.
In an embodiment, the driving circuit 290 may include a first driving enable transistor DET1 including a gate for receiving an inverted enable signal ENB, a first terminal, and a second terminal, the emission transistor EMT′ including a gate for receiving the emission signal EM, a first terminal connected to the second terminal of the first driving enable transistor DET1, and a second terminal, a second driving enable transistor DET2 including a gate for receiving the enable signal EN, a first terminal connected to the second terminal of the emission transistor EMT′, and a constant current source CCS connected between the second terminal of the second driving enable transistor DET2 and the line for transferring the second power supply voltage VSS.
In an embodiment, the light emitting element LED may include an anode connected to the line for transferring the first power supply voltage VDD, and a cathode connected to the first terminal of the first driving enable transistor DET1.
In an embodiment and as illustrated in
In an embodiment and referring to
In an embodiment, the initialization circuit 310 may include a first initialization transistor INTT1′ including a gate that receives an enable signal EN, a first terminal for receiving a first initialization voltage VINT1′, and a second terminal connected to the first node N1, and a second initialization transistor INTT2′ including a gate for receiving an initialization signal GI, a first terminal for receiving a second initialization voltage VINT2′, and a second terminal connected to the second node N2. In some embodiments, the first initialization voltage VINT1′ may be a second power supply voltage VSS, and the second initialization voltage VINT2′ may be a first power supply voltage VDD. In other embodiments, the first initialization voltage VINT1′ may be different from the second power supply voltage VSS, and the second initialization voltage VINT2′ may be different from the first power supply voltage VDD. For example, the first initialization voltage VINT1′ may be greater than or equal to the second power supply voltage VSS and lower than or equal to a lowest data voltage, and the second initialization voltage VINT2′ may be lower than or equal to the first power supply voltage VDD and higher than or equal to a highest data voltage.
Further, in an embodiment, the first initialization transistor INTT1′ may be implemented as an NMOS transistor, and the second initialization transistor INTT2′ may be implemented as a PMOS transistor. The enable signal EN may have a high level in an initialization period INTP and a data writing period DWP, and may have a low level in a sweep period SWP. The initialization signal GI may have the low level in the initialization period INTP, and may have the high level in the data writing period DWP and the sweep period SWP. Thus, the first initialization transistor INTT1′ may be turned on in the initialization period INTP and the data writing period DWP, and the second initialization transistor INTT2′ may be turned on in the initialization period INTP.
In an embodiment, the data writing circuit 330 may include a first data writing transistor DWT1 including a gate for receiving a writing signal GW, a first terminal connected to a data line DL, and a second terminal connected to the second node N2, a second data writing transistor DWT2 including a gate for receiving an inverted writing signal GWB, a first terminal connected to the data line DL, and a second terminal connected to the second node N2, and a storage capacitor CST including a first electrode connected to the second node N2, and a second electrode for receiving a ground voltage VGND. Although
In an embodiment, the ramp generating circuit 350 may include a ramp current source RCS connected to a line for transferring the first power supply voltage VDD, a ramp enable transistor RET′ including a gate for receiving the enable signal EN, a first terminal connected to the ramp current source RCS, and a second terminal connected to the first node N1, and a ramp capacitor CR including a first electrode connected to the first node N1, and a second electrode for receiving the ground voltage VGND. The ramp enable transistor RET′ may be implemented as a PMOS transistor, and may be turned on during the sweep period SWP in which the enable signal EN has the low level. Further, during the sweep period SWP, the ramp current source RCS may provide a positive ramp current to the ramp capacitor CR. That is, during the sweep period SWP, the ramp current may flow from the line for transferring the first power supply voltage VDD to the ramp capacitor CR. Accordingly, during the sweep period SWP, a voltage of the first node N1 to which the ramp capacitor CR is connected may gradually increase from the first initialization voltage VINT1. Further, in some embodiments, the gradually increasing voltage may be referred to as a ramp-up voltage.
In an embodiment, the comparator 370 may include the positive input terminal (“+”) connected to the first node N1, the negative input terminal (“−”) connected to the second node N2, and an output terminal for outputting an emission signal EM. Thus, in the sweep period SWP, the comparator 370 may generate the emission signal EM having the low level when the ramp voltage VRAMP applied to the positive input terminal is lower than the data voltage VDAT applied to the negative input terminal.
In an embodiment, the driving circuit 390 may include a constant current source CCS connected to the line for transferring the first power supply voltage VDD, a first driving enable transistor DET1′ including a gate for receiving the enable signal EN, a first terminal connected to the constant current source CCS, and a second terminal, an emission transistor EMT including a gate for receiving the emission signal EM, a first terminal connected to the second terminal of the first driving enable transistor DET1′, and a second terminal, a second driving enable transistor DET2′ including a gate for receiving an inverted enable signal ENB, a first terminal connected to the second terminal of the emission transistor EMT, and a second terminal.
In an embodiment, the light emitting element LED may include an anode connected to the second terminal of the second driving enable transistor DET2′, and a cathode connected to a line for transferring the second power supply voltage VSS.
In an embodiment and as illustrated in
In an embodiment and referring to
In an embodiment, the initialization circuit 410 may include a first initialization transistor INTT1′ including a gate for receiving an enable signal EN, a first terminal for receiving a first initialization voltage VINT1′, and a second terminal connected to the first node N1, and a second initialization transistor INTT2′ including a gate for receiving an initialization signal GI, a first terminal for receiving a second initialization voltage VINT2′, and a second terminal connected to the second node N2.
In an embodiment, the data writing circuit 430 may include a first data writing transistor DWT1 including a gate for receiving a writing signal GW, a first terminal connected to a data line DL, and a second terminal connected to the second node N2, a second data writing transistor DWT2 including a gate for receiving an inverted writing signal GWB, a first terminal connected to the data line DL, and a second terminal connected to the second node N2, and a storage capacitor CST including a first electrode connected to the second node N2, and a second electrode for receiving a ground voltage VGND. Although
In an embodiment, the ramp generating circuit 450 may include a ramp current source RCS connected to a line for transferring a first power supply voltage VDD, a ramp enable transistor RET′ including a gate for receiving the enable signal EN, a first terminal connected to the ramp current source RCS, and a second terminal connected to the first node N1, and a ramp capacitor CR including a first electrode connected to the first node N1, and a second electrode for receiving the ground voltage VGND.
In an embodiment, the comparator 470 may include the positive input terminal (“+”) connected to the second node N2, the negative input terminal (“−”) connected to the first node N1, and an output terminal for outputting an emission signal EM. Thus, in a sweep period SWP, the comparator 470 may generate the emission signal EM having a high level when a ramp voltage VRAMP applied to the negative input terminal is lower than a data voltage VDAT applied to the positive input terminal.
In an embodiment, the driving circuit 490 may include a first driving enable transistor DET1′ including a gate for receiving the enable signal EN, a first terminal, and a second terminal, the emission transistor EMT′ including a gate for receiving the emission signal EM, a first terminal connected to the second terminal of the first driving enable transistor DET1′, and a second terminal, a second driving enable transistor DET2′ including a gate for receiving an inverted enable signal ENB, a first terminal connected to the second terminal of the emission transistor EMT′, and a second terminal, and a constant current source CCS connected between the second terminal of the second driving enable transistor DET2′ and a line for transferring a second power supply voltage VSS.
In an embodiment, the light emitting element LED may include an anode connected to the line for transferring the first power supply voltage VDD, and a cathode connected to the first terminal of the first driving enable transistor DET1′.
In an embodiment and as illustrated in
In an embodiment and referring to
In an embodiment, the initialization circuit 510 may include a first initialization transistor INTT1 including a gate for receiving an enable signal EN, a first terminal for receiving a first initialization voltage VINT1, and a second terminal connected to the first node N1, and a second initialization transistor INTT2 including a gate for receiving an initialization signal GI, a first terminal for receiving a second initialization voltage VINT2, and a second terminal connected to the second node N2.
In an embodiment, the data writing circuit 530 may include a first data writing transistor DWT1 including a gate for receiving a writing signal GW, a first terminal connected to a data line DL, and a second terminal connected to the second node N2, a second data writing transistor DWT2 including a gate for receiving an inverted writing signal GWB, a first terminal connected to the data line DL, and a second terminal connected to the second node N2, and a storage capacitor CST including a first electrode connected to the second node N2, and a second electrode for receiving a ground voltage VGND. Although
In an embodiment, the ramp generating circuit 550 may include a ramp enable transistor RET including a gate for receiving the enable signal EN, a first terminal connected to the first node N1, and a second terminal, a ramp current source RCS connected between the second terminal of the ramp enable transistor RET and a line for transferring a second power supply voltage VSS, and a ramp capacitor CR including a first electrode connected to the first node N1, and a second electrode for receiving the ground voltage VGND.
In an embodiment, the comparator 570 may include the positive input terminal (“+”) connected to the first node N1, the negative input terminal (“−”) connected to the second node N2, and an output terminal for outputting an emission signal EM. Thus, in a sweep period SWP, the comparator 570 may generate the emission signal EM having a low level when a ramp voltage VRAMP applied to the positive input terminal is lower than a data voltage VDAT applied to the negative input terminal.
In an embodiment, the driving circuit 590 may include a constant current source CCS connected to a line for transferring a first power supply voltage VDD, and an emission transistor EMT including a gate for receiving the emission signal EM, a first terminal connected to the constant current source CCS, and a second terminal. In some embodiments, as illustrated in
In an embodiment, the light emitting element LED may include an anode connected to the second terminal of the emission transistor EMT, and a cathode connected to the line for transferring the second power supply voltage VSS.
In an embodiment, each frame period FP may include an initialization period INTP in which the initialization signal GI may have a high level, and the enable signal EN and the writing signal GW have a low level, a data writing period DWP in which the writing signal GW may have the high level, and the enable signal EN and the initialization signal GI may have the low level, and the sweep period SWP in which the enable signal EN may have the high level, and the initialization signal GI and the writing signal GW may have the low level.
In an embodiment, in the initialization period INTP, the first initialization transistor INTT1 may provide the first initialization voltage VINT1 to the first node N1 in response to the enable signal EN having the low level, and the second initialization transistor INTT2 may provide the second initialization voltage VINT2 to the second node N2 in response to the initialization signal GI having the high level.
In an embodiment, in the data write period DWP, the first data writing transistor DWT1 may provide the data voltage VDAT to the second node N2 in response to the writing signal GW having the high level, the second data writing transistor DWT2 may provide the data voltage VDAT to the second node N2 in response to the inverted writing signal GWB having the low level, and the storage capacitor CST may store the data voltage VDAT at the second node N2.
In an embodiment, in the sweep period SWP, the ramp enable transistor RET may provide a ramp current generated by the ramp current source RCS to the ramp capacitor CR in response to the enable signal EN having the high level, the ramp capacitor CR may provide the first node N1 with the ramp voltage VRAMP that gradually decreases from the first initialization voltage VINT1 based on the ramp current, the comparator 570 may generate the emission signal EM having the low level during an emission time ET from a time point at which the ramp voltage VRAMP becomes the data voltage VDAT to an end time point of the sweep period SWP, the emission transistor EMT may be turned on in response to the emission signal EM having the low level during the emission time ET, and the light emitting element LED may emit light based on a constant current generated by the constant current source CCS during the emission time ET.
In an embodiment and as illustrated in
In an embodiment, referring to
In an embodiment, the initialization circuit 610 may include a first initialization transistor INTT1 including a gate for receiving an enable signal EN, a first terminal for receiving a first initialization voltage VINT1, and a second terminal connected to the first node N1, and a second initialization transistor INTT2 including a gate for receiving an initialization signal GI, a first terminal for receiving a second initialization voltage VINT2, and a second terminal connected to the second node N2.
In an embodiment, the data writing circuit 630 may include a first data writing transistor DWT1 including a gate for receiving a writing signal GW, a first terminal connected to a data line DL, and a second terminal connected to the second node N2, a second data writing transistor DWT2 including a gate for receiving an inverted writing signal GWB, a first terminal connected to the data line DL, and a second terminal connected to the second node N2, and a storage capacitor CST including a first electrode connected to the second node N2, and a second electrode for receiving a ground voltage VGND. Although
The ramp generating circuit 650 may include a ramp enable transistor RET including a gate for receiving the enable signal EN, a first terminal connected to the first node N1, and a second terminal, a ramp current source RCS connected between the second terminal of the ramp enable transistor RET and a line for transferring a second power supply voltage VSS, and a ramp capacitor CR including a first electrode connected to the first node N1, and a second electrode for receiving the ground voltage VGND.
In an embodiment, the comparator 670 may include the positive input terminal (“+”) connected to the second node N2, the negative input terminal (“−”) connected to the first node N1, and an output terminal for outputting an emission signal EM. Thus, in a sweep period SWP, the comparator 670 may generate the emission signal EM having a high level when a ramp voltage VRAMP applied to the negative input terminal is lower than a data voltage VDAT applied to the positive input terminal.
In an embodiment, the driving circuit 690 may include an emission transistor EMT′ including a gate for receiving the emission signal EM, a first terminal, and a second terminal, and a constant current source CCS connected between the second terminal of the emission transistor EMT′ and the line for transferring the second power supply voltage VSS.
In an embodiment, the light emitting element LED may include an anode connected to a line for transferring a first power supply voltage VDD, and a cathode connected to the first terminal of the emission transistor EMT′.
In an embodiment and as illustrated in
In an embodiment and referring to
In an embodiment, the initialization circuit 710 may include a first initialization transistor INTT1′ including a gate for receiving an enable signal EN, a first terminal for receiving a first initialization voltage VINT1′, and a second terminal connected to the first node N1, and a second initialization transistor INTT2′ including a gate for receiving an initialization signal GI, a first terminal for receiving a second initialization voltage VINT2′, and a second terminal connected to the second node N2.
In an embodiment, the data writing circuit 730 may include a first data writing transistor DWT1 including a gate for receiving a writing signal GW, a first terminal connected to a data line DL, and a second terminal connected to the second node N2, a second data writing transistor DWT2 including a gate for receiving an inverted writing signal GWB, a first terminal connected to the data line DL, and a second terminal connected to the second node N2, and a storage capacitor CST including a first electrode connected to the second node N2, and a second electrode for receiving a ground voltage VGND. Although
In an embodiment, the ramp generating circuit 750 may include a ramp current source RCS connected to a line for transferring a first power supply voltage VDD, a ramp enable transistor RET′ including a gate for receiving the enable signal EN, a first terminal connected to the ramp current source RCS, and a second terminal connected to the first node N1, and a ramp capacitor CR including a first electrode connected to the first node N1, and a second electrode for receiving the ground voltage VGND.
In an embodiment, the comparator 770 may include the positive input terminal (“+”) connected to the second node N2, the negative input terminal (“−”) connected to the first node N1, and an output terminal for outputting an emission signal EM. Thus, in a sweep period SWP, the comparator 770 may generate the emission signal EM having a low level when a ramp voltage VRAMP applied to the negative input terminal is higher than a data voltage VDAT applied to the positive input terminal.
In an embodiment, the driving circuit 790 may include a constant current source CCS connected to the line for transferring the first power supply voltage VDD, and an emission transistor EMT including a gate for receiving the emission signal EM, a first terminal connected to the constant current source CCS, and a second terminal.
In an embodiment, the light emitting element LED may include an anode connected to the second terminal of the emission transistor EMT, and a cathode connected to a line for transferring a second power supply voltage VSS.
In an embodiment and as illustrated in
In an embodiment and referring to
In an embodiment, the initialization circuit 810 may include a first initialization transistor INTT1′ including a gate for receiving an enable signal EN, a first terminal for receiving a first initialization voltage VINT1′, and a second terminal connected to the first node N1, and a second initialization transistor INTT2′ including a gate for receiving an initialization signal GI, a first terminal for receiving a second initialization voltage VINT2′, and a second terminal connected to the second node N2.
In an embodiment, the data writing circuit 830 may include a first data writing transistor DWT1 including a gate for receiving a writing signal GW, a first terminal connected to a data line DL, and a second terminal connected to the second node N2, a second data writing transistor DWT2 including a gate for receiving an inverted writing signal GWB, a first terminal connected to the data line DL, and a second terminal connected to the second node N2, and a storage capacitor CST including a first electrode connected to the second node N2, and a second electrode for receiving a ground voltage VGND. Although
In an embodiment, the ramp generating circuit 850 may include a ramp current source RCS connected to a line for transferring a first power supply voltage VDD, a ramp enable transistor RET including a gate for receiving the enable signal EN, a first terminal connected to the ramp current source RCS, and a second terminal connected to the first node N1, and a ramp capacitor CR including a first electrode connected to the first node N1, and a second electrode for receiving the ground voltage VGND.
In an embodiment, the comparator 870 may include the positive input terminal (“+”) connected to the first node N1, the negative input terminal (“−”) connected to the second node N2, and an output terminal for outputting an emission signal EM. Thus, in a sweep period SWP, the comparator 870 may generate the emission signal EM having a high level when a ramp voltage VRAMP applied to the positive input terminal is higher than a data voltage VDAT applied to the negative input terminal.
In an embodiment, the driving circuit 890 may include an emission transistor EMT′ including a gate for receiving the emission signal EM, a first terminal, and a second terminal, and a constant current source CCS connected between the second terminal of the emission transistor EMT′ and a line for transferring a second power supply voltage VSS.
In an embodiment, the light emitting element LED may include an anode connected to the line for transferring the first power supply voltage VDD, and a cathode connected to the first terminal of the emission transistor EMT′.
In an embodiment and as illustrated in
In an embodiment and referring to
In an embodiment, the display panel 910 may include the plurality of pixels PX.
According to embodiments, each pixel PX of the display panel 910 may be a pixel 100 of
In an embodiment, the data driver 930 may provide the data voltages VDAT to the plurality of pixels PX based on output image data ODAT and a data control signal DCTRL received from the controller 970. In some embodiments, the data control signal DCTRL may include, but not limited to, an output data enable signal, a horizontal start signal and a load signal. In some embodiments, the data driver 930 and the controller 970 may be implemented as a single integrated circuit, and the single integrated circuit may be referred to as a timing controller embedded data driver (TED). In other embodiments, the data driver 930 and the controller 970 may be implemented as separate integrated circuits.
In an embodiment, the scan driver 950 may provide the writing signals GW, the initialization signals GI and the enable signals EN to the plurality of pixels PX based on a scan control signal SCTRL received from the controller 970. In some embodiments, the scan control signal SCTRL may include, but not limited to, a scan start signal and a scan clock signal. In some embodiments, the scan driver 950 may be integrated or formed in the display panel 910. In other embodiments, the scan driver 950 may be implemented as one or more integrated circuits.
In an embodiment, the controller 970 (e.g., a timing controller) may receive input image data IDAT and a control signal CTRL from an external host processor (e.g., a graphics processing unit (GPU), an application processor (AP) or a graphics card). In some embodiments, the control signal CTRL may include, but not limited to, a vertical synchronization signal, a horizontal synchronization signal, an input data enable signal, a master clock signal, etc. The controller 970 may generate the output image data ODAT, the data control signal DCTRL and the scan control signal SCTRL based on the input image data IDAT and the control signal CTRL. The controller 970 may control an operation of the data driver 930 by providing the output image data ODAT and the data control signal DCTRL to the data driver 930, and may control an operation of the scan driver 950 by providing the scan control signal SCTRL to the scan driver 950.
In the display device 900 according to an embodiment, a driving circuit of each pixel PX may provide a constant (or fixed) current to a light emitting element. Accordingly, a color shift phenomenon may be prevented in the display device 900. Further, in the display device 900, according to an embodiment, each pixel PX may include a ramp generating circuit that generates a ramp voltage. Accordingly, image quality deterioration due to a distortion of the ramp voltage may be prevented in the display device 900.
In an embodiment and referring to
In an embodiment, the processor 1110 may perform various computing functions or tasks. The processor 1110 may be an application processor (AP), a microprocessor, a central processing unit (CPU), etc. The processor 1110 may be coupled to other components via an address bus, a control bus, a data bus, etc. Further, in some embodiments, the processor 1110 may be further coupled to an extended bus such as a peripheral component interconnection (PCI) bus.
In an embodiment, the memory device 1120 may store data for operations of the electronic device 1100. For example, the memory device 1120 may include at least one non-volatile memory device such as an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, a flash memory device, a phase change random access memory (PRAM) device, a resistance random access memory (RRAM) device, a nano floating gate memory (NFGM) device, a polymer random access memory (PoRAM) device, a magnetic random access memory (MRAM) device, a ferroelectric random access memory (FRAM) device, etc., and/or at least one volatile memory device such as a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a mobile dynamic random access memory (mobile DRAM) device, etc.
In an embodiment, the storage device 1130 may be a solid state drive (SSD) device, a hard disk drive (HDD) device, a CD-ROM device, etc. The I/O device 1140 may be an input device such as a keyboard, a keypad, a mouse, a touch screen, etc., and an output device such as a printer, a speaker, etc. The power supply 1150 may supply power for operations of the electronic device 1100. The display device 1160 may be coupled to other components through the buses or other communication links.
In an embodiment, in the display device 1160, a driving circuit of each pixel may provide a constant (or fixed) current to a light emitting element. Accordingly, a color shift phenomenon may be prevented in the display device 1160. Further, in the display device 1160, according to embodiments, each pixel may include a ramp generating circuit that generates a ramp voltage. Accordingly, image quality deterioration due to a distortion of the ramp voltage may be prevented in the display device 1160.
In an embodiment, the invention may be applied to any display device 1160 and any electronic device 1100 including the display device 1160. For example, the invention may be applied to a smart phone, a wearable electronic device, a tablet computer, a mobile phone, a television (TV) (e.g., a digital TV, a 3D TV, etc.), a personal computer (PC), a home appliance, a laptop computer, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a music player, a portable game console, a navigation device, etc.
The foregoing is illustrative of embodiments and is not to be construed as limiting thereof. Although a few embodiments have been described, those skilled in the art will readily appreciate that many modifications are possible in the embodiments without materially departing from the novel teachings and advantages of the invention. Accordingly, all such modifications are intended to be included within the scope of the invention. Therefore, it is to be understood that the foregoing is illustrative of various embodiments and is not to be construed as limited to the specific embodiments disclosed, and that modifications to the disclosed embodiments, as well as other embodiments, are intended to be included within the scope of the appended claims. Moreover, the embodiments or parts of the embodiments may be combined in whole or in part without departing from the scope of the invention.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-2023-0124651 | Sep 2023 | KR | national |
