Patent Grant
11783756
This application claims priority to Chinese Patent Application 202211366229.8, filed Nov. 3, 2022, the entire disclosure of which is incorporated herein by reference.
The present disclosure belongs to the field of display technology, and particularly relates to a pixel driving circuit and a display device.
With the development of small spacings, LED (Light-Emitting Diode) display screens have put forward higher requirements for row driving, from row switching of pure P-type MOSFETs (Metal-Oxide Semiconductor Field Effect Transistors) to multifunctional row driving with higher integration level and better functionality.
There are provided a display driving circuit and a display device, according to embodiments of the present disclosure. The technical solution is as below:
A first aspect of the present disclosure provides a display driving circuit, including:
a first timing controller;
a second timing controller; and
at least one selector circuit having a first signal receiving end, a second signal receiving end, a data connection end, and a reference voltage end, wherein the first signal receiving end is connected to the first timing controller and configured to receive a level signal output by the first timing controller; the second signal receiving end is connected to the second timing controller and configured to receive a level signal output by the second timing controller; the data connection end is connected to a data line and configured to output a level signal thereon to the data line;
the selector circuit is configured to choose to, in a row scanning stage, control the reference voltage end and the data connection end to be connected to each other in response to the level signal output by the first timing controller; and the selector circuit is configured to at least choose to, in a two-adjacent-row scanning gap stage, control the reference voltage end and the data connection end to be connected to each other in response to the level signal output by the second timing controller.
According to a second aspect of the present disclosure, there is provided a display device, including a display panel located in a display area, a scan driving circuit located in a non-display area, and any one of the display driving circuits described above, wherein the display panel includes a plurality of arrayed light-emitting pixels, a plurality of columns of data lines, and a plurality of rows of scan lines, first electrodes of the light-emitting pixels are connected to the scan lines, the scan lines are connected to the scan driving circuit, second electrodes of the light-emitting pixels are connected to the data lines, and the data lines are connected to data connection ends of the display driving circuit.
Other features and advantages of the present disclosure will become apparent through the detailed description below, or partially learned through the practice of the present disclosure.
It should be understood that the general description above and the detailed description below are only exemplary and explanatory, and cannot limit the present disclosure.
The accompanying drawings herein are incorporated into the specification, constitute part of this specification, show the embodiments consistent with the present disclosure, and are used together with the specification to explain the principle of the present disclosure. Apparently, the accompanying drawings in the description below merely illustrate some embodiments of the present disclosure. Those of ordinary skill in the art may also derive other accompanying drawings from these accompanying drawings without creative efforts.
The exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be implemented in various forms and should not be understood to be limited to the examples elaborated herein; and rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete, and the concept of the exemplary embodiments will be fully communicated to those skilled in the art.
In the present disclosure, the terms such as “first” and “second” are only used for descriptive purposes, and cannot be construed as indicating or implying relative importance or implying the number of technical features indicated. Thus, the features defined with “first” and “second” may explicitly or implicitly include one or more of the features. In the description of the present disclosure, “a plurality of” means two or more, unless otherwise expressly and specifically defined.
In addition, the features, structures, or characteristics described may be combined in any suitable way in one or more embodiments. In the description below, many specific details are provided to give a full understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solution of the present disclosure may be practiced without one or more specific details, or other methods, components, devices, steps, etc. may be employed. In other cases, the well-known methods, devices, implementations, or operations are not shown or described in detail to avoid blurring various aspects of the present disclosure.
The present disclosure provides a display device. As shown in
The scan driving circuit 20 writes a first voltage into the first electrodes of the light-emitting pixels 30 through the scan lines 50. The display driving circuit 10 writes a second voltage into the second electrodes of the light-emitting pixels 30 through the data lines 40. When a difference between the first voltage and the second voltage at two ends of the light-emitting pixel 30 is greater than a threshold voltage of the light-emitting pixel 30, the light-emitting pixel 30 may emit light. When the difference between the first voltage and the second voltage of the light-emitting pixel 30 is less than the threshold voltage of the light-emitting pixel 30, the light-emitting pixel 30 does not emit light.
For example, the display panel in the embodiment of the present disclosure may be an OLED display, a Mini-LED display, or a Micro-LED display. In other words, the light-emitting pixels 30 may be light-emitting diodes (LEDs for short).
It should be understood that the light-emitting diodes have first electrodes being anodes and second electrodes being cathodes, wherein each of the rows of scan lines 50 is correspondingly connected to the anodes of the light-emitting diodes in a row, and each of the columns of data lines 40 is correspondingly connected to the cathodes of the light-emitting diodes in a column.
When a data signal Row of a control row in the scan driving circuit 20 is low, a voltage (i.e. an anode voltage of the LEDs) on the scan line 50 will be pulled up, and output data (which may be understood as a cathode voltage of the LEDs) Out of the display driving circuit that is received from the data line 40 will be displayed. A transistor, connected to the scan line 50, in the scan driving circuit 20 in
As shown in
When the data signal Row(n+1) of the control row in the scan driving circuit 20 is low, a voltage on the (n+1)th row of scan line will be pulled up. In this stage, the mth column of data line, the (m+1)th column of data line, and the (m+2)th column of data line correspondingly receive a low-level signal of the data signal Out(m), a low-level signal of the data signal Out(m+1), and a low-level signal of the data signal Out(m+2), so that mth, (m+2)th, and (m+2)th LEDs in the (n+1)th row emit light. As shown in
At low brightness (low grayscale or low gray level), the LEDs emit light for a short time, and a current in a discharge path of parasitic capacitors is constant, resulting in a smaller proportion of the current flowing through the LEDs to cause color deviation of the LEDs. For example, if the proportion of current flowing through a red LED is less affected, the whole LED tends to be red; if the proportion of the current flowing through a blue LED is less affected, the whole LED tends to be blue; and if the proportion of the current flowing through a green LED is less affected, the whole LED tends to be green.
At low grayscale, the time for turning on PWM is shorter, the total current flowing through the LEDs is lower, and the current at the data connection end (a port connected to the data line 40) of the display driving circuit 10 is a sum of the current flowing through the LEDs and the current of the parasitic capacitor on the data line 40, so that compared with high grayscale, the low grayscale has different current proportion than the high grayscale, which leads to different effects of the parasitic capacitor on R (red), G (green) and B (blue) LEDs, and the current on the parasitic capacitor at low grayscale (generally referring to grayscale of 0-31) will obviously affect display to cause color deviation. The current passing through the data connection end of the display driving circuit 10 does not completely passes through the LEDs and also includes the charge on the parasitic capacitor of the data line 40, in other words, the root cause for color deviation at low grayscale is that the current required for the LED to emit light is lower than the current flowing through the data connection end of the display driving circuit 10, that is, the actual brightness of the LEDs has not reached its original brightness.
To improve this situation, the aforementioned display driving circuit 10 is improved in the embodiment of the present disclosure. Specifically, as shown in
The first timing controller 101 is configured to control, in a normal display stage (the row scanning stage), the light-emitting pixels 30 to emit light; and the second timing controller 102 is configured to control, in the two-adjacent-row scanning gap stage, charge of the parasitic capacitors on the data lines 40 to be released.
Specifically, as shown in
It should be understood that the display driving circuit 10 may include a plurality of selection circuits 103, and the data connection end D of each of the selector circuits 103 is correspondingly connected to one data line 40.
As shown in
For example, as shown in
The selector circuit 103 is configured to at least choose to, in the two-adjacent-row scanning gap stage B, control the reference voltage end S and the data connection end D to be connected to each other in response to the level signal output by the second timing controller 102, so that the voltage on the reference voltage end S is written into the second electrode of the light-emitting pixel 30 through the data connection end D. During a stage B1 in
It should be understood that to ensure that the light-emitting pixel 30 does not emit light in the two-adjacent-row scanning gap stage B, a difference between the voltage received by the scan line 50 and the reference voltage provided by the reference voltage end S should be less than the threshold voltage of the light-emitting pixel 30, so as to avoid affecting normal data display.
For example, in the two-adjacent-row scanning gap stage B, G2 is at a low level, which means that the voltage received by the corresponding row of scan line 50 is a low-level voltage. In this stage, the voltage of Out2 in the stage B1 is a low-level voltage provided by the reference voltage end S to the corresponding data line 40, and the electric potential thereof in a stage B2 is a blanking voltage corresponding to the data line 40, so that the voltage difference between the two electrodes of the light-emitting pixel 30 is equal to 0 (in the stage B1) or less than 0 (in the stage B2). Because the threshold voltage of the light-emitting pixel is greater than 0, the light-emitting pixel 30 does not emit light in the two-adjacent-row scanning gap stage B.
In addition, it should be noted that the two-adjacent-row scanning gap stage B in this embodiment refers to a stage after nth row scanning and before (n+1)th row scanning.
In an optional embodiment, the selector circuit 103 is configured to choose to, during part of time periods (such as a time period B1 in
Further, the two-adjacent-row scanning gap stage B may be divided into at least two time periods, for example, as shown in
It should be understood that the level signals output by the second timing controller 102 during the first time period B1 and the second time period B2 in the two-adjacent-row scanning gap stage B are different, that is, one of the first level signal output by the second timing controller 102 in the first time period B1 and the second level signal output by the second timing controller in the second time period B2 is a high-level signal, while the other of the first level signal output by the second timing controller in the first time period and the second level signal output by the second timing controller in the second time period is a low-level signal, which may be selected according to a specific structure of the selector circuit 103.
It should be understood that a control signal output by the first timing controller 101 is not affected by the second timing controller 102, and only needs to be controlled to be output according to specific display requirements. In the normal row scanning display stage (i.e. the row scanning stage), the selector circuit 103 will normally write the reference voltage of the reference voltage end S into the data line 40 through the data connection end D in response to the level signal output by the first timing controller 101.
In a specific embodiment, the second timing controller 102 can adjust an output duration of the first level signal in the two-adjacent-row scanning gap stage B based on display parameter information, that is, a duration of the first time period B1 in the two-adjacent-row scanning gap stage B is adjusted, to adjust a charge release duration of the parasitic capacitor on the data line 40. It should be noted that this display parameter information may include parameters such as color deviation.
For example, when there is still color deviation in a detected display picture, it may be that the charge of the parasitic capacitor on the data line 40 has not been fully released, and the second timing controller 102 prolongs the output duration of the first level signal in the two-adjacent-row scanning gap stage B, that is, the duration of the first time period B1 in the two-adjacent-row scanning gap stage B is prolonged, so that the charge of the parasitic capacitor on the data line 40 is fully released, thereby improving the color deviation.
In the embodiment of the present disclosure, as shown in
For example, this switching transistor T may be an N-type transistor. In the two-adjacent-row scanning gap stage B, if the level signal output by the first timing controller 101 to the first signal receiving end Cr1 is a low-level signal, and the level signal output by the second timing controller 102 to the second signal receiving end Cr2 is a high-level signal, a control signal output by the OR gate Or to the switching transistor T is a high-level signal, so that the first end and the second end of the switching transistor T are connected to each other, that is, the reference voltage end S is connected to the data connection end D, and thus the reference voltage output by the reference voltage end S is written into the data line 40 through the data connection end D, thereby implementing charge release of the parasitic capacitor on the data line 40.
Specifically, when the two-adjacent-row scanning gap stage B includes the above-mentioned first time period B1 and second time period B2, the first level signal output by the second timing controller 102 in the first time period B1 is a high-level signal, and the second level signal output by the second timing controller in the second time period B2 is a low-level signal.
It should be understood that in the row scanning stage A, the level signal output by the first timing controller 101 is a high-level signal, and the level signal output by the second timing controller 102 is not limited and may be a high-level signal or a low-level signal.
The switching transistor T is not limited to the N-type transistor and may also be a P-type transistor, and it is only needed to correspondingly adjust the level signals output by the first timing controller 101 and the second timing controller 102. There is no excessive limitation herein.
In this embodiment, a reference voltage provided by the reference voltage end S in the row scanning stage A may be equal to a reference voltage provided by the reference voltage end in the two-adjacent-row scanning gap stage. As shown in
There is a main difference between Embodiment 2 and Embodiment 1 that specific structures of the selector circuit 103 are different. Other structures may refer to those in Embodiment 1 and will not be repeated herein.
In this embodiment, as shown in
A control end of the first transistor T1, a control end of the third transistor T3, and a control end of the fourth transistor T4 are connected to the second signal receiving end Cr2; the first transistor T1 has a first end connected to the first signal receiving end Cr1 and a second end connected to a control end of the second transistor T2; the second transistor T2 has a first end connected to the data connection end D and a second end connected to the first reference voltage end S1; the third transistor T3 has a first end connected to the data connection end D and a second end connected to the second reference voltage end S2; and the fourth transistor T4 has a first end connected to the control end of the second transistor T2 and a second end connected to the first reference voltage end S1.
In this embodiment, the first transistor T1 is a first-type transistor, each of the second transistor T2, the third transistor T3, and the fourth transistor T4 is a second-type transistor, and one of the first-type transistor and the second-type transistor is a P-type transistor, while the other of the first-type transistor and the second-type transistor is an N-type transistor.
For example, the first switching transistor T1 is a P-type transistor, the second switching transistor T2, the third switching transistor T3, and the fourth switching transistor T4 are N-type switching transistors.
In the normal display stage (i.e. in the row scanning stage A), the level signal output by the second timing controller 102 to the second signal receiving end Cr2 is a low-level signal. In this case, the third transistor T3 and the fourth transistor T4 are turned off, the first transistor T1 is turned on, and the first timing controller 101 outputs a level signal to the first signal receiving end Cr1 to control turn-on or turn-off of the second transistor T2. When the level signal output by the first timing controller 101 to the first signal receiving end Cr1 is a high-level signal, the second transistor T2 is turned on, and the first reference voltage end S1 writes its reference voltage into the data line 40 through the data connection end D, that is, the voltage on the data line 40 is equal to the reference voltage (V1 as shown in
During a time period of switching between rows (i.e., the two-adjacent-row scanning gap stage B), the level signal output by the second timing controller 102 to the second signal receiving end Cr2 is a high-level signal. In this case, the third transistor T3 and the fourth transistor T4 are turned on, and the first transistor T1 is turned off. Because each of voltages of a gate and a source (the control end and the second end) of the second transistor T2 is the voltage provided by the first reference voltage end S1, that is, a voltage difference Vgs between the gate and the source of the second transistor T2 is equal to 0, the voltage difference between the gate and the source of the second transistor is less than a threshold voltage Vth of the second transistor T2, so that the second transistor T2 is turned off. In this case, the voltage on the data line 40 is equal to the reference voltage (V2 as shown in
The selector circuit 103 in this embodiment adopts this design, so that the reference voltages written into the data line 40 in the row scanning stage A and the two-adjacent-row scanning gap stage B may be different or same, and may be adjusted and matched according to the actual situation, making it more flexible.
For example, in this embodiment, the voltage provided by the first reference voltage end S1 is not equal to the voltage provided by the second reference voltage end S2. Specifically, the voltage V2 provided by the second reference voltage end S2 is between the blanking voltage of the data line 40 and the reference voltage V1 provided by the first reference voltage end S1, so that the light-emitting pixels 30 may be protected while the consumption is reduced.
According to the solution of the present disclosure, the selector circuit connects, in the two-adjacent-row scanning gap stage, the reference voltage end to the data connection end by using the signal output by the second timing controller, without affecting normal display, that is, in the two-adjacent-row scanning gap stage, the reference voltage of the reference voltage end is written into the data line, so that charge of a parasitic capacitor on the data line is released in advance before this column of light-emitting pixels (i.e., the column of light-emitting pixels driven by this data line) emit light, thereby ensuring that the total current of the data connection end is equal to or basically close to the current passing through the light-emitting pixels. In other words, it is ensured that the current for this column of light-emitting pixels to emit light basically completely passes through the data connection end, so that the problem of color deviation of the light-emitting pixels at low grayscale may be solved and the display uniformity may be improved.
It should be understood that to ensure that the light-emitting pixel does not emit light in the two-adjacent-row scanning gap stage, a difference between a voltage provided by the scan line and the reference voltage provided by the reference voltage end is less than a threshold voltage of the light-emitting pixel, so as to avoid affecting normal data display.
In the description of this specification, the description with reference to the terms such as “some embodiments” and “examples” means that the specific features, structures, materials or characteristics described in combination with the embodiments or examples are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable way in any one or more embodiments or examples. In addition, those skilled in the art may combine different embodiments or examples described in this specification and features of different embodiments or examples, without mutual contradiction.
Although the embodiments of the present disclosure have been shown and described above, it may be understood that the above embodiments are exemplary and cannot be understood as a limitation to the present disclosure. Those of ordinary skill in the art may make changes, modifications, substitutions, and modifications to the above embodiments within the scope of the present disclosure. Therefore, any changes or modifications made in accordance with the claims and specification of the present disclosure should fall within the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211366229.8 | Nov 2022 | CN | national |
| Number | Date | Country |
|---|---|---|
| 1710636 | Dec 2005 | CN |
| 103943066 | Jul 2014 | CN |
| 104091568 | Oct 2014 | CN |
| 113450701 | Sep 2021 | CN |
| 113450701 | Sep 2021 | CN |
| 113643658 | Nov 2021 | CN |
| 115132129 | Sep 2022 | CN |
| H0667622 | Mar 1994 | JP |
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| CN113450701A Machine Translation (Year: 2023). |
| CNIPA, Notification to Grant Patent Right for Invention for CN Application No. 202211366229.8, dated Dec. 26, 2022. |
| CNIPA, First Office Action for CN Application No. 202211366229.8, dated Dec. 8, 2022. |
