Patent Application
20240431165
This application claims priority to Chinese Patent Application No. 202311309253.2 filed Oct. 10, 2023, the disclosure of which is incorporated herein by reference in its entirety.
Embodiments of the present disclosure relate to the field of display technology and, in particular, to a display panel and a display device.
With the diversification of display usage scenarios, the demand for irregular screens increases, such as in-vehicle electronic rear-view mirrors and other products. As the market and terminal audiences diversify, various irregular products emerge one after another. However, the existing irregular in-vehicle display product may be wide at the position of the irregular bezel and cannot satisfy the trend of narrow bezels.
The present disclosure provides a display panel and a display device to rationally lay out the structure of an irregular bezel region, implement the narrow bezel design of the irregular bezel region, and satisfy the trend of narrow bezels.
In a first aspect, an embodiment of the present disclosure provides a display panel. The display panel includes a display region and a non-display region. The non-display region and the display region are connected to each other. The display region includes multiple data signal lines and multiple scanning signal lines. The data signal lines intersect the scanning signal lines.
The non-display region includes an irregular bezel region. The boundary line between the irregular bezel region and the display region intersects the extension lines of the data signal lines and the extension lines of the scanning signal lines. The irregular bezel region includes a gate driver circuit region and a source driver circuit region. The source driver circuit region is located between the gate driver circuit region and the display region.
A shift register circuit is configured in the gate driver circuit region. The shift register circuit is electrically connected to the scanning signal lines and configured to provide a gate drive signal to the multiple scanning signal lines in sequence.
A demultiplexing circuit is configured in the source driver circuit region. The demultiplexing circuit is electrically connected to the data signal lines and configured to provide a data signal to the multiple data signal lines in sequence.
The irregular bezel region also includes multiple data fan-out wires. A data fan-out wire is electrically connected to at least two data signal lines through the demultiplexing circuit.
The data fan-out wires and the shift register circuit are located in different film layers of the display panel, and the data fan-out wires and the demultiplexing circuit are located in different film layers of the display panel. The projections of the data fan-out wires on the light emission surface of the display panel are overlapped with the projection of the shift register circuit and/or the projection of the demultiplexing circuit on the light emission surface of the display panel.
In a second aspect, an embodiment of the present disclosure provides a display device. The display device includes the display panel according to any one of the first aspect.
In the display panel and the display device provided by embodiments of the present disclosure, the irregular bezel region of the display panel includes a gate driver circuit region and a source driver circuit region. A shift register circuit is configured in the gate driver circuit region. The shift register circuit may provide a scanning signal to a pixel unit of the display region through a scanning signal line. A demultiplexing circuit is configured in the source driver circuit region. The demultiplexing circuit may receive a data signal according to the data fan-out wires configured in the irregular bezel region and provide the data signal to the pixel unit in the display region through a data signal line. Thus, the corresponding pixel unit in the display region is driven to implement the image display function. At the same time, the data fan-out wires are configured in a different film layer of the display panel from the shift register circuit and the demultiplexing circuit. The projections of the data fan-out wires are configured to are overlapped with the projection of the shift register circuit and/or the projection of the demultiplexing circuit. Thus, the data fan-out wires and the shift register circuit or the demultiplexing circuit may be vertically stacked up and down. In this manner, the data fan-out wires may be prevented from occupying excessive horizontal area of the irregular bezel region, and the horizontal spacing between the shift register circuit and demultiplexing circuit may be shortened, so that the horizontal width of the irregular bezel region may be effectively reduced, thereby implementing the design of a narrow bezel.
Hereinafter the present disclosure is further described in detail in conjunction with the drawings and embodiments. It is to be understood that the specific embodiments described herein are intended to illustrate and not to limit the present disclosure. Additionally, it is to be noted that, for ease of description, only part, not all, of structures related to the present disclosure are illustrated in the drawings.
Terms used in the embodiments of the present disclosure are merely used to describe the specific embodiments and not intended to limit the present disclosure. It is to be noted that spatially related terms, including “on”, “below”, “left” and “right” used in the embodiments of the present disclosure, are described from the perspective of the drawings, and are not to be construed as a limitation to the present disclosure. In addition, in the context, it is to be understood that when a component is formed “on” or “below” another component, the component may not only be directly formed “on” or “below” another component, and may also be indirectly formed “on” or “below” another component via an intermediate component. The terms “first” and “second” are merely used for description and used to distinguish between different components rather than indicate any order, quantity, or importance. For those of ordinary skill in the art, specific meanings of the preceding terms in the present disclosure may be understood based on specific situations.
The term “comprising” and its variations used in the present disclosure are open-ended, that is, “including but not limited to”. The term “based on” refers to “at least partially based on”. The term “an embodiment” refers to “at least one embodiment.”
It is to be noted that concepts such as “first” and “second” mentioned in the present disclosure are only used to distinguish corresponding contents, and are not used to limit the sequence or interdependence relationship.
It is to be noted that the modifications of “one” and “multiple” mentioned in the present disclosure are illustrative and not limited, and it is to be understood by those skilled in the art that unless the context clearly indicates otherwise, “one” or “multiple” should be understood as “one or more”.
At present, for the structural layout of the irregular bezel region NA2, referring to
In response to the preceding technical problems, an embodiment of the present disclosure provides a display panel. The display panel includes a display region and a non-display region. The non-display region and the display region are connected to each other. The display region includes multiple data signal lines and multiple scanning signal lines. The data signal lines intersect the scanning signal lines.
The non-display region includes an irregular bezel region. The boundary line between the irregular bezel region and the display region intersects the extension lines of the data signal lines and the extension lines of the scanning signal lines. The irregular bezel region includes a gate driver circuit region and a source driver circuit region. The source driver circuit region is located between the gate driver circuit region and the display region.
A shift register circuit is configured in the gate driver circuit region. The shift register circuit is electrically connected to the scanning signal lines and configured to provide a gate drive signal to the multiple scanning signal lines in sequence.
A demultiplexing circuit is configured in the source driver circuit region. The demultiplexing circuit is electrically connected to the data signal lines and configured to provide a data signal to the multiple data signal lines in sequence.
The irregular bezel region also includes multiple data fan-out wires. A data fan-out wire is electrically connected to at least two data signal lines through the demultiplexing circuit.
The data fan-out wires and the shift register circuit are located in different film layers of the display panel, and the data fan-out wires and the demultiplexing circuit are located in different film layers of the display panel. The projections of the data fan-out wires on the light emission surface of the display panel are overlapped with the projection of the shift register circuit and/or the projection of the demultiplexing circuit on the light emission surface of the display panel.
In the preceding technical solutions, the irregular bezel region of the display panel includes a gate driver circuit region and a source driver circuit region. A shift register circuit is configured in the gate driver circuit region. The shift register circuit may provide a scanning signal to a pixel unit of the display region through a scanning signal line. A demultiplexing circuit is configured in the source driver circuit region. The demultiplexing circuit may receive a data signal according to the data fan-out wires configured in the irregular bezel region and provide the data signal to the pixel unit in the display region through a data signal line. Thus, the corresponding pixel unit in the display region is driven to implement the image display function. At the same time, the data fan-out wires are configured in a different film layer of the display panel from the shift register circuit and the demultiplexing circuit. The projections of the data fan-out wires are configured to are overlapped with the projection of the shift register circuit and/or the projection of the demultiplexing circuit. Thus, the data fan-out wires and the shift register circuit or the demultiplexing circuit may be vertically stacked up and down. In this manner, the data fan-out wires may be prevented from occupying excessive horizontal area of the irregular bezel region, and the horizontal spacing between the shift register circuit and demultiplexing circuit may be shortened, so that the horizontal width of the irregular bezel region may be effectively reduced, thereby implementing the design of a narrow bezel.
The above is the core concept of the present disclosure, and the technical solutions in the embodiments of the present disclosure are described clearly and completely hereinafter in conjunction with the drawings in the embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of the present disclosure.
The non-display region NA includes an irregular bezel region NA2. The boundary line between the irregular bezel region NA2 and the display region AA intersects the extension lines of the data signal lines 120 and the extension lines of the scanning signal lines 110. The irregular bezel region NA2 includes a gate driver circuit region and a source driver circuit region (not shown). The source driver circuit region is located between the gate driver circuit region and the display region AA.
A shift register circuit is configured in the gate driver circuit region 11. The shift register circuit 11 is electrically connected to the scanning signal lines 110 and configured to provide a gate drive signal to the multiple scanning signal lines 110 in sequence.
A demultiplexing circuit is configured in the source driver circuit region 12. The demultiplexing circuit 12 is electrically connected to the data signal lines 120 and configured to provide a data signal to the multiple data signal lines 120 in sequence.
The irregular bezel region NA2 also includes multiple data fan-out wires 130. A data fan-out wire 130 is electrically connected to at least two data signal lines 120 through the demultiplexing circuit 12.
The data fan-out wires 130 and the shift register circuit 11 are located in different film layers of the display panel, and the data fan-out wires 130 and the demultiplexing circuit 12 are located in different film layers of the display panel. The projections of the data fan-out wires 130 on the light emission surface of the display panel are overlapped with the projection of the shift register circuit 11 and/or the projection of the demultiplexing circuit 12 on the light emission surface of the display panel.
The scanning signal lines 110 in the display region AA extend in a first direction X (the row direction in the example) and are arranged in a second direction Y (the column direction in the example). The data signal lines 120 extend in the second direction Y (the column direction in the example) and are arranged in the first direction X (the row direction in the example). It should be understood by those skilled in the art that multiple scanning signal line 110 and multiple data signal line 120 in the display region AA intersect to form multiple pixel units (not shown). The scanning signal lines 110 provide a scanning signal to the pixel units, and the data signal lines 120 provide a data signal to the pixel units, thereby driving each pixel unit of the display region to light up one by one to implement the display of the entire image. Based on this, as described above, for an irregular display panel, the bezel region NA may be divided into a regular bezel region NA1 and an irregular bezel region NA2. The junction line between the regular bezel region NA1 and display region AA intersects only the scanning signal lines 110 or the data signal lines 120. Thus, the shift register circuit 11 for the scanning signal lines 110 or the demultiplexing circuit 12 for the data signal lines 120 may be configured in the regular bezel region NA1. The regular bezel region NA1 is generally located on two sides of the display region AA in the first direction X or the second direction Y For the irregular bezel region NA2, the junction line between the irregular bezel region NA2 and display region AA intersects the scanning signal lines 110 and the data signal lines 120, that is, the demultiplexing circuit 12 and the shift register circuit 11 need to be configured for the data signal lines 120 and the scanning signal line 110 respectively. The irregular bezel region NA2 is generally located at the junction of two types of regular bezel regions NA1. The difference between the two types of regular bezel regions NA1 is that one regular bezel region NA1 is located on one side of the display region AA in the first direction X, and the other regular bezel region NA1 is located on one side of the display region AA in the second direction Y To simplify, the irregular bezel region NA2 may be understood as a bezel region at the corner position of the display region AA.
In this embodiment of the present disclosure, for the circuit and wiring layout in the irregular bezel region NA2, the data fan-out wires 130 that provide a data signal to the demultiplexing circuit 12 are configured in a different film layer of the display panel from the shift register circuit 11 and the demultiplexing circuit 12. The projections of the data fan-out wires 130 on the light emission surface of the display panel are overlapped with the projection of the shift register circuit 11 and/or the projection of the demultiplexing circuit 12 on the light emission surface of the display panel. Actually, the data fan-out wires 130 are moved vertically above the shift register circuit 11 and/or the demultiplexing circuit 12. In
First, it is to be noted that for example, in the structural diagram shown in
It should be understood by those skilled in the art that the shift register circuit 11 needs to sequentially provide scanning signals to the scanning signal lines 110 row by row. To implement the process of row-by-row scanning, the shift register circuit 11 needs to sequentially output scanning signals through the cascaded shift registers 111. Among the cascaded shift registers 111, the first shift register 111 receives a trigger signal STV and generates a scanning signal and simultaneously outputs the scanning signal to the correspondingly connected scanning signal line 110 and the shift register 111 of the next level. The shift register 111 of the next level shifts the scanning signal to generate the second-level scanning signal and simultaneously outputs the scanning signal to the correspondingly connected scanning signal line 110 and the shift register 111 of the next level, and the rest are done in the same manner. Thus, the scanning process of all scanning signal lines 110 is implemented. The first signal wires 112 in the shift register circuit 11 may be understood as a clock signal, a level signal, and a trigger signal STV required during the working process of the shift register circuit 11. For example, the clock signal may include both CK and XCK. In other shift register circuit designs, only one clock signal CK or more clock signals may be configured. This is not limited in this embodiment. The level signal may include a high-level signal VGH and a low-level signal VGL. Thus, for multiple shift registers 111 in cascade, it is necessary to arrange the first signal wires 112 on the side facing away from the display region AA to provide clock signals, level signals, and trigger signals to the shift registers 111.
In summary, it can be seen that for the shift register circuit 11, the region in which the shift register circuit 11 is located may be divided into a region in which the shift registers 111 are located and a region in which the first signal wires 112 are located. Based on this, in an embodiment of the present disclosure, the projections of the data fan-out wires 130 on the light emission surface of the display panel is configured to are overlapped with the projections of the shift registers 111 and/or the projections of the first signal wires 112 on the light emission surface of the display panel. Essentially, the data fan-out wires 130 are configured in a region in which the shift registers 111 are located, and the data fan-out wires 130 and the shift registers 111 are vertically stacked up and down. Alternatively, the data fan-out wires 130 are configured in a region in which the first signal wires 112 are located, and the data fan-out wires 130 and the first signal wires 112 are vertically stacked up and down. Alternatively, part of the data fan-out wires 130 are configured in the region in which the shift registers 111 are located, and the part of the data fan-out wires 130 and the shift registers 111 are vertically stacked up and down. Part of the data fan-out wires 130 are configured in the region in which the first signal wires 112 are located, and the part of the data fan-out wires 130 and the first signal wires 112 are vertically stacked up and down.
The specific disposition positions of the data fan-out wires 130 and the corresponding optimized design are further described below.
The data fan-out wires 130 are electrically connected to the demultiplexing circuit 12 and are responsible for providing data signals to the demultiplexing circuit 12. The first signal wires 112 include clock signal lines and trigger signal lines and are responsible for providing pulse signals such as clock signals and trigger signals to the shift registers. Apparently, when the data fan-out wires 130 and the first signal wires 112 are configured to be vertically stacked up and down, the voltage variation of the signals on the first signal wires 112 may cause capacitive coupling with the data fan-out wires 130. The clock signal having a higher frequency and the trigger signal having a higher frequency may interfere with the data signal transmitted on the data fan-out wires 130. As a result, there is a deviation in the data signal, which causes bright and dark lines to appear on a display image, thereby affecting the accuracy of the pixel display. Based on this, in this embodiment, the data fan-out wires 130 and the first signal wires 112 are configured in different film layers of the display panel, and the signal shielding layer 201 is configured between the film layer where the data fan-out wires 130 are located and the film layer where the first signal wires 112 are located. The interference of high-frequency signals such as clock signals and trigger signals in the first signal wires 112 to the data signals transmitted on the data fan-out wires 130 may be shielded by the signal shielding layer 201. Thus, the normal transmission of the data signals on the data fan-out wires 130 may be ensured, and it is ensured that signals of the shift register circuit and signals of the data fan-out wires are independent of each other. In this manner, the accuracy of the pixel display is improved, and the problem of uneven display of a display image caused by bright and dark lines is solved, thereby ensuring the display quality of the display panel.
Further referring to
The first metal layer 210, the second metal layer 220, and the third metal layer 230 are basic metal layers for preparing circuits and wires for the display panel. The metal layers are patterned, so that wires and connection lines between circuit components may be formed. The data fan-out wires 130 are prepared in the third metal layer 230. The first signal wires are prepared in the first metal layer 210. The signal shielding layer 201 between the data fan-out wires 130 and the first signal wires 112 may be prepared in the second metal layer 220 between the third metal layer 230 and the first metal layer 210. It is to be understood that part of the second metal layer 220 is multiplexed into the signal shielding layer 201, so that the addition of a metal layer to the signal shielding layer 201 alone may be avoided. Further, the preparation process and the preparation technique of the display panel may be simplified, and on the premise that the signal shielding layer 201 is used to shield the data fan-out wires 130 from interference, the manufacturing costs can be saved.
Further referring to
Here, the first connection wires 113 are mainly responsible for providing the signals to the first signal wires 112 to the shift registers 111. Since the first signal wires 112 are configured in the first metal layer 210, the components of the shift registers 111 that receive the signals transmitted by the first signal wires 112 are generally transistors, and the source and drain or gate thereof are generally configured in the second metal layer 220. When the first signal wires 112 and the shift registers 111 are connected, it is necessary to configure the first connection wires 113 and the first via 20201 to span two metal layers. Of course, it can also be understood that to avoid the influence of the signal shielding layer 201 of the same layer, when the first signal wires 112 are configured, the first signal wires 112 need to be insulated from the signal shielding layer 201. That is, when the second metal layer 220 is prepared, the first connection wires 113 and the pattern of the signal shielding layer 201 need to be separated by patterning.
Furthermore, to implement a better shielding effect, for example, in the preceding embodiment, for the signal shielding layer 201 between the data fan-out wires 130 and the first signal wires 112, a fixed potential signal may be introduced into the signal shielding layer 201.
Specifically, referring to
In the preceding two embodiments, a fixed potential signal is introduced into the signal shielding layer 201, so that the signal shielding layer 201 may have a stable potential. Thus, the electromagnetic interference generated by a high-frequency signal is shielded, so that the signal shielding layer 201 can effectively block the electromagnetic interference generated by the first signal wires 112 to the data fan-out wires 130, and the signal interference problem caused by the capacitive coupling between signal lines can be effectively solved.
Specifically, the data fan-out wires 130 may be all configured in the second metal layer 220 as shown in
In addition, as described above, since a high-frequency clock signal or a high-frequency trigger signal needs to be transmitted on the first signal wires 112, when the data fan-out wires 130 and the first signal wires 112 are configured to be vertically stacked up and down, capacitive coupling is easily generated between the wires, and electromagnetic interference is generated to the data fan-out wires 130. Thus, when at least part of the data fan-out wires 130 are configured in the second metal layer 220, and at least part of the data fan-out wires 130 and the first signal wires 112 are vertically stacked up and down, it is also necessary to overcome the capacitive coupling problem of part of the data fan-out wires 130 and the first signal wires 112.
Specifically, further referring to
Those skilled in the art know that the capacitance formula is C=εA/d. C is directly proportional to the dielectric constant ε and inversely proportional to the thickness d of the dielectric layer between capacitor plates. In this embodiment, essentially, the thickness d of the first interlayer insulating layer 2021 between the data fan-out wires 130 in the second metal layer 220 and the first signal wires 112 in the first metal layer 210 is thickened, so that the capacitance between two wires is reduced, thereby avoiding the capacitive coupling between the two wires. Similarly, the dielectric constant ε of the first interlayer insulating layer 2021 between the data fan-out wires 130 in the second metal layer 220 and the first signal wires 112 in the first metal layer 210 is set smaller. Similarly, the capacitance between two wires is reduced, thereby avoiding the capacitive coupling between the two wires.
It is to be understood that the thickness of the first interlayer insulating layer 2021 is increased, and the dielectric constant of the first interlayer insulating layer 2021 is reduced, so that the capacitance may be better reduced, thereby avoiding the capacitive coupling between two wires. Those skilled in the art may make selections and configuration according to actual requirements. In addition, it should be added that the first interlayer insulating layer 2021 may be made of a different insulating material from the second interlayer insulating layer 2022 to implement the purpose of reducing the dielectric constant.
It is to be noted that in the actual application process, since the components in the shift register 111 may occupy the first metal layer 210 and the second metal layer 220, when part of the data fan-out wires 130 are laid out in the second metal layer 220, they may be laid above the first signal wires 112, that is, the data fan-out wires 130 in the second metal layer 220 may be configured not to are overlapped with the projections of the shift registers 111 but to are overlapped with the projections of the first signal wires 112.
Further referring to
First, it is to be noted that the extension direction of the first wire segments 1301 in the data fan-out wires 130 is parallel to the extension direction of the junction line between the irregular bezel region NA2 and the display region AA, which means that there are partial wire segments in each data fan-out wire 130 that extend in parallel and are arranged in the W direction as shown in the figure. Of course, to electrically connect the data fan-out wires 130 to the demultiplexing circuit 12, second wire segments 1302 are configured in the data fan-out wires 130. The second wire segments 1302 extend in the W direction, and two ends of a second wire segment 1302 are connected to a first wire segment 1301 and the demultiplexing circuit 12 respectively. It can be seen that multiple first wire segments 1301 arranged in the W direction may be configured to partially overlap first signal wires 112 and partially overlap shift registers 111. That is, part of the first wire segments 1301 may be configured above the region where the first signal wires 112 are located, and part of the first wire segments 1301 may be configured above the region where the shift registers are located.
It is to be understood that since the first signal wires 112 are located on the side of the shift registers 111 facing away from the display region AA, compared with the first wire segments 1301 that overlap the projections of the shift registers 111, the first wire segments 1301 that overlap the projections of the first signal wires 112 is further away from the display region AA. Since a data fan-out wire 130 needs to be connected to at least one data signal line 120 of the display region AA through the demultiplexing circuit 12, when the data fan-out wire 130 is extended to display region AA, the lengths of different data fan-out wires 130 may be different, which may be simply understood that the lengths of the second wire segments 1302 may be different. In this embodiment, a data signal line 120 connected to a data fan-out wire 130 of which the projection of a first wire segment 1301 overlaps the projection of a first signal wire 112 is configured to be a first data signal line 1201. A data signal line 120 connected to a data fan-out wire 130 of which the projection of a first wire segment 1301 overlaps the projection of a shift register 111 is configured to be a second data signal line 1202. The first data signal line 1201 is configured to be more adjacent to the irregular bezel region NA2 in the arrangement direction of the data signal lines 120, that is, the X direction, so that in the arrangement direction of the data signal lines 120, the data signal line 120 connected to the data fan-out wire 130 of which the projection of the first wire segment 1301 overlaps the projection of the shift register 111 is further away from the irregular bezel region NA2, and the data fan-out wire 130 of which the projection of the first wire segment 1301 overlaps the projection of the first signal wire 112 is more adjacent to the irregular bezel region NA2. In short, in this configuration, the data fan-out wire 1301 of which the projection of the first wire segment 1301 overlaps the projection of the shift register 111 and the data fan-out wire 130 of which the projection of the first wire segment 1301 overlaps the projection of the first signal wire 112 have connection wires of the same length when connecting to the data signal lines 120. Thus, the impedance difference caused by a large difference in the lengths of the connection wires corresponding to the two kinds of data fan-out wires 130 can be avoided. Further, it is possible to ensure that the data signals provided by the two kinds of data fan-out wires 130 to the corresponding data signal lines 120 are more balanced, thereby preventing the problem of uneven display.
The touch fan-out wires 140 are responsible for transmitting touch signals, which also need to pass through the irregular bezel region NA2. It is to be understood that due to the presence of the touch fan-out wires 140, the circuit-trace layout of the irregular bezel region NA2 needs to be rationally designed to avoid an excessive area of the irregular bezel region NA2. In this embodiment, for this purpose, the projections of the data fan-out wires 130 and the projections of the touch fan-out wires 140 are configured to be overlapped with the projection of the shift register circuit 11 and the projection of the demultiplexing circuit 12. Essentially, the two kinds of fan-out wires are configured above the shift register circuit 11 and the demultiplexing circuit 12 to implement vertical stacking, thereby alleviating the problem of excessive area of the irregular bezel region NA2 caused by the horizontal layout.
As shown in
More specifically, as shown in
Here, the overlapping of the projection regions in the third direction W means that the edges on two sides in the third direction W overlap respectively. Thus, the edges on two sides of the data fan-out wires 130 and the edges on two sides of the touch fan-out wires 140 in the third direction W are configured to be overlapped with the region of the edges on two sides of the shift register circuit 11 and the edges on two sides of the demultiplexing circuit 12 in the third direction W respectively. Actually, the space of the shift register circuit 11 and the demultiplexing circuit 12 in the third direction W is fully utilized. The data fan-out wires 130 and the touch fan-out wires 140 are configured in this region. Thus, in one aspect, as described above, the data fan-out wires 130 and the touch fan-out wires 140 are prevented from occupying the excessive horizontal area of the irregular bezel region NA2, and in another aspect, it is ensured that the data fan-out wires 130 and the touch fan-out wires 140 have sufficient horizontal wiring space. Two kinds of fan-out wires are configured to have wider line widths and line spacing. Thus, the impedance on a fan-out wire is balanced, and the problem of the excessively small impedance caused by the excessively narrow line width of a signal line is avoided. At the same time, the mutual interference problem caused by excessively close distances of signal lines may also be avoided.
A demultiplexer 121 includes a control terminal Ctrl, an input terminal IN, and at least two output terminals OUT. The control terminal Ctrl is connected to a second signal wire 122. The input terminal IN is connected to a data fan-out wire 130. An output terminal OUT is connected to a data signal line 120.
The touch fan-out wires 140 and the second signal wires 122 are located in different film layers of the display panel, and a signal shielding layer 201 is configured between the film layer where the touch fan-out wires 140 are located and the film layer where the second signal wires 122 are located.
The demultiplexer 121 is essentially a selector and may be specifically a transistor or a MOS transistor. In this embodiment, the demultiplexer 121 has two output terminals OUT, that is, connecting two data signal lines 120 is only an example. It should be understood by those skilled in the art that in the actual application process, the demultiplexer 121 may be provided with three, four, or six output terminals to implement source driving in one demultiplexer driving three data signal lines, one demultiplexer driving four data signal lines, and one demultiplexer driving six data signal lines manner.
Similarly, further referring to
The principle here is the same as the principle of the preceding embodiment in which the signal shielding layer 201 is configured between the data fan-out wires 130 and the first signal wires 112 in the shift register circuit 11. The interference of high-frequency signals such as strobe signals in the second signal wires 122 to the touch signals transmitted on the touch fan-out wires 140 is shielded by the signal shielding layer 201. Thus, the normal transmission of the touch signals on the touch fan-out wires 140 may be ensured, thereby ensuring that the touch detection is accurate. Moreover, the signal shielding layer 201 may also be configured in the second metal layer 220. Thus, the addition of a metal layer to the signal shielding layer 201 alone is avoided. Further, the preparation process and the preparation technique of the display panel may be simplified, and on the premise that the signal shielding layer 201 is used to shield the touch fan-out wires 140 from interference, the manufacturing costs can be saved.
Similarly, to implement a better shielding effect, for example, in the preceding embodiment, for the signal shielding layer 201 between the touch fan-out wires 140 and the second signal wires 122, a fixed potential signal may be introduced into the signal shielding layer 201.
Specifically, further referring to
Further referring to
One end of the fixed potential signal line 150 is electrically connected to the signal shielding layer 201, and the other end of the fixed potential signal line 150 is electrically connected to the driver chip IC through the bonding pad 13. The driver chip IC is configured to provide the fixed potential signal to the signal shielding layer 201 through the fixed potential signal line 150.
In the preceding two embodiments, a fixed potential signal is introduced into the signal shielding layer 201, so that the signal shielding layer 201 may have a stable potential. Thus, the electromagnetic interference generated by a high-frequency signal is shielded, so that the signal shielding layer 201 can effectively block the electromagnetic interference generated by the first signal wires 112 to the data fan-out wires 130.
Specifically, referring to
Further referring to
The first data fan-out wires 131 are located in the second metal layer 220. The second data fan-out wires 132 are located in the third metal layer 230. The projections of the first data fan-out wires 131 on the light emission surface of the display panel are located between the projection of the shift register circuit 11 and the projection of the demultiplexing circuit 12 on the light emission surface of the display panel and in the projections of the second data fan-out wires 132 on the light emission surface of the display panel.
The first touch fan-out wires 141 are located in the second metal layer 220. The second touch fan-out wires 142 are located in the third metal layer 230. The projections of the first touch fan-out wires 141 on the light emission surface of the display panel are between the projection of the shift register circuit 11 and the projection of the demultiplexing circuit 12 on the light emission surface of the display panel and in the projections of the second touch fan-out wires 142 on the light emission surface of the display panel.
The first data fan-out wires 131 may be understood as data fan-out wires 130 disposed in the second metal layer 220. The first touch fan-out wires 141 may be understood as touch fan-out wires 140 disposed in the second metal layer 220. The difference from the data fan-out wires 130 and the touch fan-out wires 140 disposed in the second metal layer 220 shown in
Similarly,
In addition, it is added that in the embodiment shown in
Based on the same concept, an embodiment of the present disclosure provides a display device.
It is to be noted that the preceding are only preferred embodiments of the present disclosure and the technical principles used therein. It is to be understood by those skilled in the art that the present disclosure is not limited to the embodiments described herein. For those skilled in the art, various apparent modifications, adaptations, combinations, and substitutions can be made without departing from the scope of the present disclosure. Therefore, while the present disclosure is described in detail in connection with the preceding embodiments, the present disclosure is not limited to the preceding embodiments and may include equivalent embodiments without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202311309253.2 | Oct 2023 | CN | national |
