Patent Grant
12020636
The present application claims priority to Chinese Patent Application No. 202211689960.4, filed on Dec. 27, 2022, the content of which is incorporated herein by reference in its entirety.
The present disclosure relates to the technical field of display, and in particular, to a display panel and a display device.
In conventional display panels, there is a need to introduce new connection lines into a display region to achieve a particular function. For example, data lines at two sides of the display region may be led to the middle of the display region through the connection lines. In this way, in design of fan-out lines, the fan-out lines are only required to be concentrated in a region directly facing a driver chip, so that a purpose of reducing a width of a corner bezel can be achieved.
However, after the introduction of the connection lines into the display region, the connection lines may affect light transmittance of the display panel and may also affect flatness of an anode in a light-emitting element, resulting in adverse problems such as color shift on the display panel.
In view of the above, some embodiments of the present disclosure provide a display panel and a display device, which can optimize layout design of the display panel, thereby improving light transmittance and anode flatness of the display panel.
In an aspect, some embodiments of the present disclosure provide a display panel, having a display region and including pixel circuits located in the display region, each of the pixel circuits including a drive transistor and a first reset transistor that is electrically connected to a reset signal line; first signal lines located in the display region, the first signal lines including an indirect-connection signal line and a direct-connection signal line; connection signal lines located in the display region, at least part of the connection signal lines being electrically connected to the indirect-connection signal line, the connection signal lines including a first connection signal line extending along a first direction and a second connection signal line extending along a second direction, the second direction intersecting the first direction; light-emitting elements located in the display region, each of the light-emitting elements including an anode; a pixel circuit group, the pixel circuit group including two pixel circuits at least partially symmetric with and adjacent to each other, and the first reset transistors of the two pixel circuits in the pixel circuit group being adjacent to each other and being connected to each other through a first semiconductor connection line, the first semiconductor connection line being connected to the reset signal line; and pixel columns arranged along the first direction, each pixel column of the pixel columns including pixel circuits arranged along the second direction, two sides of the drive transistors in one pixel column of the pixel columns in the first direction being provided with two first signal lines and two second connection signal lines, and in a direction perpendicular to a plane where the display panel is located, at least one of the anodes overlapping with two adjacent first signal lines, or at least one of the anodes overlapping with two adjacent second connection signal lines, or at least one of the anodes overlapping with two adjacent first signal lines while at least another one of the anodes overlapping with two adjacent second connection signal lines.
In another aspect, some embodiments of the present disclosure provide a display device, including a display panel. The display panel has a display region and includes: pixel circuits located in the display region, each of the pixel circuits including a drive transistor and a first reset transistor that is electrically connected to a reset signal line; first signal lines located in the display region, the first signal lines including an indirect-connection signal line and a direct-connection signal line; connection signal lines located in the display region, at least part of the connection signal lines being electrically connected to the indirect-connection signal line, the connection signal lines including a first connection signal line extending along a first direction and a second connection signal line extending along a second direction, the second direction intersecting the first direction; light-emitting elements located in the display region, each of the light-emitting elements including an anode; a pixel circuit group, the pixel circuit group including two pixel circuits at least partially symmetric with and adjacent to each other, and the first reset transistors of the two pixel circuits in the pixel circuit group being adjacent to each other and being connected to each other through a first semiconductor connection line, the first semiconductor connection line being connected to the reset signal line; and pixel columns arranged along the first direction, each pixel column of the pixel columns including pixel circuits arranged along the second direction, two sides of the drive transistors in one pixel column of the pixel columns in the first direction being provided with two first signal lines and two second connection signal lines, and in a direction perpendicular to a plane where the display panel is located, at least one of the anodes overlapping with two adjacent first signal lines, and/or at least another one of the anodes overlapping with two adjacent second connection signal lines.
In order to better illustrate the technical solutions in the embodiments of the present disclosure, the accompanying drawings used in the description of the embodiments will be briefly introduced below. It is apparent that the accompanying drawings in the following description are merely some embodiments of the present disclosure, and other drawings can be obtained by those of ordinary skill in the art from the provided drawings without creative efforts.
In order to better illustrate the technical solutions of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.
It should be made clear that the described embodiments are merely some of rather than all of the embodiments of the present disclosure. All other embodiments acquired by those of ordinary skill in the art without creative efforts based on the embodiments in the present disclosure fall within a protection scope of the present disclosure.
The terms used in the embodiments of the present disclosure are for the purpose of describing particular embodiments only and are not intended to limit the present disclosure. As used in the embodiments of the present disclosure and the appended claims, the singular forms of “a/an”, “the”, and “said” are intended to include plural forms, unless otherwise clearly specified in the context.
It should be understood that the term “and/or” used herein is merely an association relationship describing associated objects, indicating that three relationships may exist. For example, A and/or B indicates that there are three cases of A alone, A and B together, and B alone. In addition, the character “/” herein generally means that associated objects before and after it are in an “or” relationship.
Some embodiments of the present disclosure provide a display panel. As shown in
The pixel circuits 2 are located in the display region 1. The pixel circuits 2 each include a drive transistor M0 and a first reset transistor M1 electrically connected to a reset signal line Vref.
The first signal lines 3 are located in the display region 1. The first signal lines 3 may be electrically connected to the pixel circuits 2 to transmit signals required for displaying to the pixel circuits 2. The first signal lines 3 each include an indirect-connection signal line 5 and a direct-connection signal line 6.
The connection signal lines 4 are located in the display region 1. At least part of the connection signal lines 4 are electrically connected to the indirect-connection signal lines 5. In one arrangement, the direct-connection signal lines 6 are directly electrically connected to fan-out lines in a bezel region, and the indirect-connection signal lines 5 are indirectly electrically connected to the fan-out lines in the bezel region through the connection signal lines 4. The connection signal lines 4 include first connection signal lines 7 each extending along a first direction x and second connection signal lines 8 each extending along a second direction y. The second direction y intersects the first direction x. It is to be noted that, in some embodiments of the present disclosure, the indirect-connection signal lines 5 may only have a connection relationship with one first connection signal line 7 and one second connection signal line 8 or may have a connection relationship with at least two first connection signal lines 7 and at least two second connection signal lines 8.
The light-emitting elements 9 are located in the display region 1. The light-emitting elements 9 include anodes 10, which are electrically connected to the pixel circuits 2 and configured to receive driving currents provided by the pixel circuits 2 to realize normal light emission of the light-emitting elements 9.
In addition, referring to
The display panel further includes a plurality of pixel columns 13 arranged along the first direction x. The pixel columns 13 each include a plurality of pixel circuits 2 arranged along the second direction y. Each of two sides of each of the drive transistors M0 in the pixel column 13 is provided with two first signal lines 3 and two second connection signal lines 8. That is, if two adjacent first signal lines 3 are regarded as a first wiring group and two adjacent second connection signal lines 8 are regarded as a second wiring group, then the first wiring group and the second wiring group are arranged alternately. In a direction perpendicular to a plane where the display panel is located, at least some of the anodes 10 overlap with two adjacent first signal lines 3, and/or at least some of the anodes 10 overlap with two adjacent second connection signal lines 8.
In the related design, the pixel circuits 2 in the display region 1 are all designed in a uniform direction. In such a configuration, the first reset transistor M1 in each pixel circuit 2 is all located on a same side of the pixel circuit 2. As a result, the first reset transistors M1 in two adjacent pixel circuits 2 are far apart from each other, and the first reset transistors M1 in the pixel circuits 2 need to be led to the reset signal lines Vref through semiconductor connection lines and connected to the reset signal lines Vref through via-holes.
In some embodiments of the present disclosure, two adjacent pixel circuits 2 are designed to be at least partially symmetric to each other to enable the first reset transistors M1 in the two adjacent pixel circuits 2 to be arranged close to each other and adjacent to each other. Then, the two adjacent first reset transistors M1 can be connected to each other through a shorter first semiconductor connection line 12, which is connected to the reset signal line Vref through a via-hole, thereby realizing the connection between the two first reset transistors M1 and the reset signal line Vref. With such a configuration, the first reset transistors M1 can share a via-hole, so a number of via-holes between the first reset transistors M1 and the reset signal lines Vref can be greatly reduced.
It is to be noted that reduction of the number of connection via-holes may increase connection resistance, resulting in an increase in voltage drop. However, a reset voltage is applied to the pixel circuit 2 according to rows, for example, applied in rows one by one or two by two in turn. Whether gates of the drive transistors M0 are reset by the reset voltage to charge a storage capacitor C or the anodes 10 of the light-emitting elements 9 are reset by the reset voltage to charge capacitors of the light-emitting elements 9, this charging current is smaller than light-emitting currents of the light-emitting elements 9, so the voltage drop is also small. Moreover, the voltage drop only affects signal levels of the resetting and does not affect the light-emitting current, so brightness of the light-emitting elements 9 is not affected, and it has almost no influence on a display effect.
In addition, in the related design, when the connection lines are introduced into the display region 1 to reduce winding of a bezel region, a light transmission area of the display region 1 may be greatly reduced, which affects under-screen optical sensors such as an ambient light sensor (ALS) and a fingerprint on display (FOD). As a result, the technology cannot meet customers' specification requirements. However, according to the design in the present disclosure, even if connection signal lines 4 are introduced into the display region 1, a light transmission area released by the reduced via-holes can be utilized to compensate for an area blocked due to the introduction of the connection signal lines 4, so that the display panel still maintains high light transmittance. When a backlight side of the display panel is provided with an under-screen optical sensor, ambient light intensity detected by a photosensitive element can be increased, thereby helping to optimize effects of some auxiliary functions such as camera and fingerprint recognition.
In addition, in the related design, after the introduction of the connection signal lines 4 into the display panel, the first signal lines 3 and the second connection signal lines 8 in the connection signal lines 4 are generally arranged alternately. That is, one first connection signal line 7 and one second connection signal line 8 are arranged between the drive transistors M0 of two adjacent pixel columns 13. In this case, in the design of the anodes 10 in the light-emitting elements 9, at least part of the anodes 10 may simultaneously overlap with one first connection signal line 7 and one second connection signal line 8. Due to different functions of the first signal line 3 and the second connection signal line 8, the two may be different in layer thickness and line width, or different in a need to be connected to a via-hole. For example, if the anode 10 overlaps with one direct-connection signal line 7 and one second connection signal line 8, since the direct-connection signal line 6 is not required to be connected to the connection signal line 4 through a via-hole and the second connection signal line 8 may be required to be connected to the first connection signal line 7 through a via-hole, the anode 10 may overlap with only one via-hole. As a result, the via-hole may raise the anode 10 locally in a small area, thereby resulting in a non-flat surface of the anode 10.
Therefore, in some embodiments of the present disclosure, through further adjustment of the arrangement of the first signal lines 3 and the second connection signal lines 8, either two first connection signal lines 7 or two second connection signal lines 8 are arranged between the drive transistors M0 of two adjacent pixel columns 13. In this way, when at least part of the anodes 10 is located between two adjacent pixel columns 13, the anode may overlap with two first signal lines 3 of a same type or overlap with two second connection signal lines 8 of a same type, thereby alleviating the problem of layer non-flatness caused by the overlapping of the anode 10 with different types of signal lines. After the flatness of the film layer of the anode 10 is improved, a difference in amounts of light emitted by the light-emitting element 9 at different angles is reduced, which can effectively weaken color shift and improve a visual effect.
In some embodiments, as shown in
For clarity, in some embodiments of the present disclosure, along the first direction x, a k1th pixel column is denoted by a reference sign 13_k1. Only four pixel columns 13, i.e., a (2i−1)th pixel column 13_2i−1, a 2ith pixel column 13_2i, a (2i+1)th pixel column 13_2i+1, and a (2i+2)th pixel column 13_2i+2, are illustrated in
The first reset transistor M1 includes a first sub reset transistor M11 and a second sub reset transistor M12. The reset signal line Vref includes a first reset signal line Vref1 electrically connected to the first sub reset transistor M11 and a second reset signal line Vref2 electrically connected to the second sub reset transistor M12.
In one arrangement, as shown in
The first semiconductor connection line 12 includes a first connection line 15 and a second connection line 16.
The second sub reset transistors M12 in a (2n−1)th pixel column 13_2n−1 and a 2nth pixel column 13_2n are adjacently arranged, and the two adjacent second sub reset transistors M12 are connected to each other through the second connection line 16. The second connection line 16 is electrically connected to the second reset signal line Vref2. The first sub reset transistors M11 in the 2nth pixel column 13_2n and a (2n+1)th pixel column 13_2n+1 are adjacently arranged, and the two adjacent first sub reset transistors M11 are connected to each other through the first connection line 15. The first connection line 15 is electrically connected to the first reset signal line Vref1. Herein, n is a positive integer.
In other words, in some embodiments of the present disclosure, the second sub reset transistors M12 in the 1st pixel column 13_1 and the 2nd pixel column 13_2 are adjacently arranged, the second sub reset transistors M12 in the 3rd pixel column 13_3 and the 4th pixel column 13_4 are adjacently arranged, the second sub reset transistors M12 in the 5th pixel column 13_5 and the 6th pixel column 13_6 are adjacently arranged, and so on. The second sub reset transistors M12 in the 2nd pixel column 13_2 and the 3rd pixel column 13_3 are adjacently arranged, the second sub reset transistors M12 in the 4th pixel column 13_4 and the 5th pixel column 13_5 are adjacently arranged, the second sub reset transistors M12 in the 6th pixel column 13_6 and the 7th pixel column 13_7 are adjacently arranged, and so on.
In the above arrangement, the pixel circuits 2 are designed with symmetric columns. In this way, the second sub reset transistors M12 in the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n can be very close to each other, and the adjacent second sub reset transistors M12 in this part of the pixel columns 13 can be connected together only through a very short second connection line 16. Therefore, on the basis of sharing a via-hole, an extension length of the semiconductor connection line between the adjacent second sub reset transistors M12 is further reduced, thereby reducing the shielding of ambient light by the semiconductor connection line. At the same time, the first sub reset transistors M11 in the 2nth pixel column 13_2n and the (2n+1)th pixel column 13_2n+1 are also very close to each other, which can also reduce an extension length of the first connection line 15 between the adjacent first sub reset transistors M11 in this part of the pixel columns 13, thereby reducing the shielding of ambient light by the semiconductor connection line and thus further improving light transmittance of the display panel.
The second sub reset line Vref12 and the fourth sub reset line Vref22 are arranged alternately, the second sub reset lines Vref12 and the fourth sub reset line Vref22 that are adjacent two each other are spaced by one pixel column 13, and the fourth sub reset line Vref22 is located between the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n. The first connection line 15 is electrically connected to the second sub reset line Vref12, and the second connection line 16 is electrically connected to the fourth sub reset line Vref22.
With this arrangement, on the one hand, the first sub reset line Vref11 crosses the second sub reset line Vref12 to form a grid structure, which can effectively reduce an overall wiring load of the first reset signal line Vref1, and the third sub reset line crosses the fourth sub reset line Vref22 to form a grid structure, which can effectively reduce an overall wiring load of the second reset signal line Vref2. On the other hand, according to some embodiments of the present disclosure, the design of the arrangement of the second sub reset line Vref12 and the fourth sub reset line Vref22 is matched with the symmetric design of the pixel circuits 2. Taking the fourth sub reset line Vref22 as an example, combined with the symmetric design of the pixel circuits 2, it can be known that the second sub reset transistors M12 in the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n are very close to each other, and the second sub reset transistor M12 is connected to the second reset signal line Vref2. Therefore, through the arrangement of the fourth sub reset line Vref22 in the second reset signal line Vref2 between the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n, the second connection line 16 connected between the two adjacent second sub reset transistors M12 can be directly connected through a via-hole at a position overlapping with the fourth sub reset line Vref22. In this case, an extension length of the second connection line 16 can be further shortened, thereby further reducing the shading of the ambient light by the second connection line 16.
Further, referring to
For clarity, in the drawings in some embodiments of the present disclosure, along the second direction y, a k2th pixel row is denoted by a reference sign 17_k2. Only four pixel rows 17, i.e., a (2p−1)th pixel row 17_2p−1, a 2pth pixel row 17_2p, a (2p+1)th pixel row 17_2p+1, and a (2p+2)th pixel row 17_2p+2, are illustrated in
With such a configuration, a number of the first sub reset lines Vref11 and the third sub reset lines Vref21 can be reduced. Moreover, although one pixel row 17 only corresponds to one first sub reset line Vref11 or one third sub reset line Vref21, the first sub reset transistor M11 in this one pixel row 17 can be connected to the first sub reset line Vref11 through the second sub reset line Vref12 and the second sub reset transistor M12 in this one pixel row 17 can be connected to the third sub reset line Vref21 through the fourth sub reset line Vref22.
The first reset signal line Vref1 extends along the first direction x, and one pixel row 17 corresponds to one first reset signal line Vref1. The second reset signal line Vref2 extends along the second direction y, and the second reset signal line Vref2 is located between the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n.
In the above arrangement, each pixel row 17 corresponds to one first reset signal line Vref1 that extends horizontally. In this case, the first sub reset transistor M11 in each pixel row 17 can be connected to the first reset signal line Vref1 close thereto, and a connection distance between the first sub reset transistor M11 and the first reset signal line Vref1 is short. Based on the symmetrical design of the pixel circuits, the second sub reset transistors M12 in the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n are very close to each other. Through the arrangement of a vertically extending second reset signal line Vref2 between the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n, a connection distance between the second sub reset transistor M12 and the second reset signal line Vref2 can be short. Therefore, with the above arrangement, the extension lengths of the first connection line 15 and the second connection line 16 can be shortened, thereby further improving the light transmittance of the display panel.
In addition, in the above arrangement, there is no need to arrange the second reset signal line Vref2 between the 2nth pixel column 13_2n and the (2n+1)th pixel column 13_2n+1 which can further greatly reduce the number of the second reset signal lines Vref2 arranged between the pixel columns 13.
In one or more some embodiments, referring to
The pixel circuit 2 further includes a first light-emitting control transistor M4. The first light-emitting control transistor M4 is electrically connected to the power signal line PVDD. The power signal line PVDD extends along the second direction y. First light-emitting control transistors M4 in the 2nth pixel column 13_2n and the (2n+1)th pixel column 13_2n+1 are adjacent to each other, and two power signal lines PVDD connected to the 2nth pixel column 13_2n and the (2n+1)th pixel column 13_2n+1 are adjacent to each other.
The display panel further includes an auxiliary power connection line 18. The auxiliary power connection line 18 is located at a side of the first signal line 3 and the second connection signal line 8 facing away from a light-exit surface of the display panel. For example, the auxiliary power connection line 18 may be arranged in a same layer as the first connection signal line 7. The auxiliary power connection line 18 includes a first line segment 19 and a first bearing portion 20, a size of the first bearing portion 20 in the second direction y is greater than that of the first line segment 19 in the second direction y, and the first bearing portion 20 is electrically connected to the power signal line PVDD. In the direction perpendicular to the plane where the display panel is located, the first bearing portion 20 overlaps with two adjacent first signal lines 3.
A part of the first signal line 3 overlapping with the first bearing portion 20 is a first wiring segment 21. In the direction perpendicular to the plane where the display panel is located, part of the anodes 10 overlaps with the first wiring segments 21 in two adjacent first signal lines 3.
It is to be noted that, referring to
The first bearing portion 20 in the auxiliary power connection line 18 may support the first wiring segments 21 in the two adjacent first signal lines 3, thereby making positions of the first wiring segments 21 and surrounding positions be relatively flat. So, when the anode 10 is arranged above the first wiring segments 21, the anode 10 may also be flat. In addition, a large block metal structure formed by the first bearing portion 20 can also reduce a load of the power signal line PVDD.
A part of the second connection signal line 8 overlapping with the second bearing portion 24 is a second wiring segment 25. In the direction perpendicular to the plane where the display panel is located, part of the anode 10 overlaps with the second wiring segments 25 in two adjacent second connection signal lines 8.
Similar to the first bearing portion 20, the second bearing portion 24 in the auxiliary power connection line 18 may support the second wiring segments 25 in the two adjacent second connection lines, thereby improving layer flatness of the anode 10 above the second wiring segments 25, so that the layers of a greater number of anodes 10 in the display panel are relatively flat.
It can be understood that, in the pixel circuit 2, operational stability of the drive transistor M0 greatly affects accuracy of the driving current transferred from the pixel circuit 2 to the light-emitting element 9. In some embodiments of the present disclosure, through the further arrangement of the first protruding portion 26 overlapping with the first node N1 on the auxiliary power connection line 18, a potential of the gate of the drive transistor M0 can be stabilized by using a fixed power supply voltage transferred on the first protruding portion 26, thereby improving reliability of an operating state of the drive transistor M0.
The power signal line PVDD includes a plurality of second line segments 28. Two adjacent second line segments 28 in one power signal line PVDD are spaced apart. The first bearing portion 20 includes a main body portion 29 and a protruding portion 30. End portions of two adjacent second line segments 28 close to the protruding portion 30 are connected to each other through a first connection wire 31. The second semiconductor connection line 27 is electrically connected to the first connection wire 31 through a first via-hole 32, and the first connection wire 31 is electrically connected to the protruding portion 30 through a second via-hole 33.
In the above arrangement, while the flatness of the anode 10 is improved by using the first bearing portion 20, the first bearing portion 20 also serves as a connection portion between two adjacent second line segments 28 in the power signal line PVDD, forming a continuous signal transmission path in the power signal line PVDD.
In addition, it is to be further noted that the layer structure of the display panel includes a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer. The semiconductor layer may include structures such as a first semiconductor connection line 12 and a second semiconductor connection line 27. The first metal layer may include structures such as a first scanning signal line Scan1 and a second scanning signal line Scan2. The second metal layer may include structures such as a first reset signal line Vref1, a second reset signal line Vref2, and an electrode plate of the storage capacitor C in the pixel circuit 2. The third metal layer may include structures such as the power signal line PVDD. In an existing manufacturing process of the display panel, generally, holes are formed between the third metal layer and the second metal layer and between the third metal layer and the semiconductor layer.
Based on the above arrangement, the first connection wire 31 connected between two adjacent second line segments 28 is located in the third metal layer, therefore, when two adjacent first light-emitting control transistors M4 are connected to each other through the second semiconductor connection line 27, the first via-hole 32 connecting the second semiconductor connection line 27 with the first connection wire 31 can be formed together when a via-hole is formed between the third metal layer and the semiconductor layer. In some embodiments, when a connection via-hole is formed between the third metal layer and the semiconductor layer, an insulating layer between the third metal layer and the second metal layer, an insulating layer between the second metal layer and the first metal layer, and an insulating layer between the first metal layer and the semiconductor layer may be perforated by using a same mask, thereby saving a number of masks required.
In addition, based on the above arrangement, two adjacent first light-emitting control transistors M4 are connected together through the second semiconductor connection line 27, and then are connected to the protruding portion 30 through the first via-hole 32 and the second via-hole 33, so that the two first light-emitting control transistors M4 are not required to be connected to the power signal line PVDD respectively through separate connection via-holes. In this way, when designing the connection via-hole between the first light-emitting control transistor M4 and the power signal line PVDD, an area of the connection via-hole can be appropriately increased to alleviate voltage drop when a power signal is transmitted in the via-hole.
In some embodiments, one side of the protruding portion 30 close to the substrate may be provided with an organic film with a thickness greater than 500 nm to reduce a load of the PVDD. The thickness of the organic film may be 500 nm, 600 nm, 1 μm, or greater.
It is to be noted that
In some embodiments, referring to
The above design that the first via-hole 32 and the second via-hole 33 do not overlap with each other can prevent an extremely deep via-hole due to the overlapping of the two, thereby preventing problems such as etching residues or faults in an upper metal layer in the manufacturing process. Moreover, based on the above design, the protruding portion 30 protrudes from the second semiconductor connection line 27, thereby shielding the second semiconductor connection line 27 to a greater extent, so that a potential of the second electrode of each of the two first light-emitting control transistors M4 can be stabilized to a greater extent by using the power supply voltage transferred on the protruding portion 30, thereby optimizing the display effect.
For clarity, in the drawings in some embodiments of the present disclosure, along the second direction y, a k2th pixel row is denoted by a reference sign 17_k2. Only four pixel rows 17, i.e., a (2p−1)th pixel row 17_2p−1, a 2pth pixel row 17_2p, a (2p+1)th pixel row 17_2p+1, and a (2p+2)th pixel row 17_2p+2, are illustrated in
The first reset transistor M1 includes a first sub reset transistor M11 and a second sub reset transistor M12. The reset signal line Vref includes a first reset signal line Vref1 electrically connected to the first sub reset transistor M11 and a second reset signal line Vref2 electrically connected to the second sub reset transistor M12.
The first semiconductor connection line 12 includes a third connection line 35 and a fourth connection line 36.
The first sub reset transistors M11 in a (2n−1)th pixel row 17_2n−1 and a 2nth pixel row 17_2n are adjacently arranged, and the two adjacent first sub reset transistors M11 are connected to each other through the third connection line 35. The third connection line 35 is electrically connected to the first reset signal line Vref11. The second sub reset transistors M12 in the 2nth pixel row 17_2n and a (2n+1)th pixel row 17_2n+1 are adjacently arranged, and the two adjacent second sub reset transistors M12 are connected to each other through the fourth connection line 36. The fourth connection line 36 is electrically connected to the second reset signal line Vref2. n is a positive integer.
In other words, in some embodiments of the present disclosure, the first sub reset transistors M11 in the 1st pixel row 17_1 and the 2nd pixel row 17_2 are adjacently arranged, the first sub reset transistors M11 in the 3rd pixel row 17_3 and the 4th pixel row 17_4 are adjacently arranged, the first sub reset transistors M11 in the 5th pixel row 17_5 and the 6th pixel row 17_6 are adjacently arranged, and so on. The second sub reset transistors M12 in the 2nd pixel row 17_2 and the 3rd pixel row 17_3 are adjacently arranged, the second sub reset transistors M12 in the 4th pixel row 17_4 and the 5th pixel row 17_5 are adjacently arranged, the second sub reset transistors M12 in the 6th pixel row 17_6 and the 7th pixel row 17_7 are adjacently arranged, and so on.
In the above arrangement, the pixel circuits 2 are designed with symmetric rows. In this case, the first sub reset transistors M11 in the (2n−1)th pixel row 17_2n−1 and the 2nth pixel row 17_2n can be very close to each other, and the adjacent first sub reset transistors M11 in this part of the pixel rows 17 can be connected together only through a very short third connection line 35. Therefore, on the basis of sharing a via-hole, an extension length of the semiconductor connection line between the adjacent first sub reset transistors M11 is further reduced, thereby reducing the shielding of ambient light by the semiconductor connection line. At the same time, the second sub reset transistors M12 in the 2nth pixel row 17_2n and the (2n+1)th pixel row 17_2n+1 are also very close to each other, thereby reducing an extension length of the fourth connection line 36 between the adjacent second sub reset transistors M12 in this part of the pixel rows 17, and thus reducing the shielding of ambient light by the semiconductor connection line and further improving the light transmittance of the display panel.
In some embodiments, referring to
In some embodiments of the present disclosure, the wiring of the first reset signal line Vref1 and the second reset signal line Vref2 is also designed to match the symmetric design of the pixel circuits 2, so that the first reset signal line Vref1 is very close to the first sub reset transistor M11 connected thereto, and the second reset signal line Vref2 is very close to the second sub reset transistor M12 connected thereto, thereby reducing extension lengths of the third connection line 35 and the fourth connection line 36, and thus further improving the light transmittance of the display panel.
The display panel further includes a second connection wire 38. The second connection wire 38 is located at one side of the first reset signal line Vref1 facing a light-exit surface of the display panel. The second connection wire 38 is electrically connected to a part of the first reset signal line Vref1 located at each of two sides of the first breaking 37 through a third via-hole 39. The second connection wire 38 is further electrically connected to the third connection line 35 through a fourth via-hole 40. In the direction perpendicular to the plane where the display panel is located, the fourth via-hole 40 is located in the first breaking 37.
It can be understood that the layer structure of the display panel includes a semiconductor layer, a first metal layer, a second metal layer, and a third metal layer. The semiconductor layer may include structures such as a first semiconductor connection line 12. The first metal layer may include structures such as a first scanning signal line Scan1 and a second scanning signal line Scan2. The second metal layer may include structures such as a first reset signal line Vref1, a second reset signal line Vref2, and an electrode plate of a storage capacitor C in a pixel circuit 2. The third metal layer may include structures such as a second connection wire 38 and a power signal line PVDD.
In an existing manufacturing process of the display panel, generally, holes are formed between the third metal layer and the second metal layer and between the third metal layer and the semiconductor layer. For example, there is a need to form a via-hole between the third metal layer and the second metal layer to connect the power signal line PVDD and the electrode plate of the storage capacitor C.
In the design of a connection manner of the first reset signal line Vref1 and the third connection line 35, if a via-hole is directly formed between the second metal layer where the first reset signal line Vref1 is located and the semiconductor layer where the third connection line 35 is located, a new perforation flow is further required to be added on the basis of the original process flow. In some embodiments of the present disclosure, by use of the above “three-hole design” formed by two third via-holes 39 and one fourth via-hole 40, in the manufacturing process of the display panel, it is only required that the third via-hole 39 is synchronously formed between the second connection wire 38 and the first reset signal line Vref1 when another via-hole is formed between the third metal layer and the second metal layer, and the fourth via-hole 40 is synchronously formed between the second connection wire 38 and the third connection line 35 when another hole is formed between the third metal layer and the semiconductor layer, which does not require any additional process flow and does not increase process costs.
The display panel further includes a third connection wire 42. The third connection wire 42 is located at one side of the second reset signal line Vref2 facing a light-exit surface of the display panel. The third connection wire 42 is electrically connected to as part of the second reset signal line Vref2 located at each of two sides of the second breaking 41 through a fifth via-hole 43. The third connection wire 42 is further electrically connected to the fourth connection line 36 through a sixth via-hole 44. In the direction perpendicular to the plane where the display panel is located, the sixth via-hole 44 is located in the second breaking 41.
Similar to the above arrangement, in the design of a connection manner of the second reset signal line Vref2 and the fourth connection line 36, in some embodiments of the present disclosure, by use of “three-hole design” formed by two fifth via-holes 43 and one sixth via-hole 44, there is no need to add other perforation process flows to the manufacturing process of the display panel.
The first auxiliary reset signal line Vref1, crosses the first reset signal line Vref1 to form a grid structure, and the second auxiliary reset signal line Vref2, crosses the second reset signal line Vref2 to form a grid structure, thereby effectively reducing a wiring load of the reset signal line Vref and reducing voltage drop of the reset voltage during transmission.
In some embodiments, the first auxiliary reset signal line Vref1, and the second auxiliary reset signal line Vref2, may be located between two adjacent pixel columns 13 respectively, and the first auxiliary reset signal line Vref1, and the second auxiliary reset signal line Vref2, are arranged alternately. Only one first auxiliary reset signal line Vref1, or one second auxiliary reset signal line Vref2, may be arranged between two adjacent pixel columns 13.
In addition, it is to be further noted that, in some embodiments of the present disclosure, when the pixel circuits 2 are designed with symmetric rows, referring to
The display panel further includes a first anode group 51 and a second anode group 52 arranged alternately along the first direction x. The first anode group 51 includes anode units 53 arranged along the second direction y. The anode units 53 each include one first anode 48 and one second anode 49. Moreover, the first anodes 48 or the second anodes 49 in two adjacent anode units 53 are adjacent. The second anode group 52 includes a plurality of third anodes 50 arranged along the second direction y.
Based on the above arrangement, in two adjacent anode units 53 of the first anode group 51, either two first anodes 48 are close to each other, or two second anodes 49 are close to each other. In this case, in the manufacturing process of the display panel, light-emitting layers above the two first anodes 48 close to each other can share an aperture in the mask for evaporation, and light-emitting layers above the two second anodes 49 close to each other can share an aperture in the mask for evaporation, which, compared with the manner in which one light-emitting layer only corresponds to one opening in the mask, can increase a light-emitting area, thereby increasing an aperture ratio.
In some embodiments, referring to
For example, referring to
In some embodiments of the present disclosure, the arrangement of the anode 10 is also designed to match the arrangement of the pixel circuit 2. Referring to
When the first anode 48 does not overlap with the first connection signal line 7, the first anode 48 can avoid the via-hole between the first connection signal line 7 and the second connection signal line 8, thereby preventing an influence of the via-hole on the flatness of the first anode 48. When the second anode 49 does not overlap with the first connection signal line 7, the second anode 49 can avoid the via-hole between the first connection signal line 7 and the second connection signal line 8, thereby preventing an influence of the via-hole on the flatness of the second anode 49.
According to the above arrangement, the anodes 10 in the light-emitting elements 9 in a same color avoid the via-hole between the first connection signal lines 7 and the second connection signal lines 8, so that the flatness of the anode 10 in the light-emitting element 9 in this color is better, and color shift of this color can be ameliorated emphatically. For example, since green light is more easily visible to a human eye, the second anode 49 in the green light-emitting element 46 does not overlap with the first connection signal line 7, thereby emphatically ameliorating a color shift phenomenon of the green light.
The light-emitting elements 9 include a red light-emitting element 45, a green light-emitting element 46, and a blue light-emitting element 47. In the direction perpendicular to the plane where the display panel is located, the anodes 10 (second anodes 49) in some of the green light-emitting elements 46 overlap with the first sub connection line segments 54 of two adjacent second connection signal lines 8.
In at least part of the second connection signal lines 8, the second sub connection line segment 55 is configured to be electrically connected to the indirect-connection signal line 5 through the first connection wire 7, while the first sub connection line segment 54 is configured to improve uniformity of reflection of the display panel at different positions. Green is more visible to the human eye, compared with red and blue. Therefore, in some embodiments of the present disclosure, through the arrangement of the second anodes 49 in part of the green light-emitting elements 46 above the first connection wire 31, potentials of the second anodes 49 can be stabilized by using the fixed voltage transferred on the first connection wire 31, thereby improving stability of the potentials of the second anodes 49, and thus helping to improve stability of light emission of this part of the green light-emitting elements 46.
The pixel circuit 2 includes a threshold compensation transistor M3 and a second light-emitting control transistor M5. The second light-emitting control transistor M5 is electrically connected to the anode 10 of the light-emitting element 9 through an anode connection via-hole 56. The threshold compensation transistors M3 and the second light-emitting control transistors M5 in the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n are adjacent. Two second connection signal lines 8 are arranged between the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n.
The threshold compensation transistor M3 is electrically connected to the second light-emitting control transistor M5 through a third semiconductor connection line 57, and parts of two adjacent third semiconductor connection lines 57 extending along the second direction y are located between two adjacent second connection signal lines 8.
In the above arrangement, the second connection signal lines 8 and the parts of the third semiconductor connection lines 57 extending along the second direction y avoid each other, which can reduce mutual interference of signals transmitted on the second connection signal lines 8 and the third semiconductor connection lines 57, thereby preventing potential fluctuations on the third semiconductor connection lines 57 and improving stability of the driving current transferred from the second light-emitting control transistor M5 to the anode 10.
In addition, it is to be further noted that, under a condition that the second connection signal line 8 is located between the first gate g1 and the second gate g2 of the threshold compensation transistor M3, a distance between two adjacent second connection signal lines 8 may be equal or not equal to a distance between two adjacent first signal lines 3.
The second connection signal line 8 includes a first sub connection line segment 54 and a second sub connection line segment 55 arranged along the second direction y. A breaking exists between the first sub connection line segment 54 and the second sub connection line segment 55. The first sub connection line segment 54 is configured to receive a fixed voltage, and the second sub connection line segment 55 is electrically connected to the indirect-connection signal line 5.
The pixel circuit 2 includes a second light-emitting control transistor M5. The second light-emitting control transistor M5 is electrically connected to the anode 10 of the light-emitting element 9 through an anode connection via-hole 56. The second light-emitting control transistors M5 in the (2n−1)th pixel column 13_2n−1 and the 2nth pixel column 13_2n are adjacent to each other. In the second connection signal line 8, a distance between the first sub connection line segment 54 and the anode connection via-hole 56 is smaller than a distance between the second sub connection line segment 55 and the anode connection via-hole 56.
When the pixel circuits 2 are designed with symmetric columns, the anode connection via-hole 56 may be close to the second connection signal line 8. Since the first sub connection line segment 54 of the second connection signal line 8 is configured to receive a fixed voltage, the first sub connection line segment 54 is closer to the anode connection via-hole 56, and stability of a node potential of the anode connection via-hole 56 can be improved by using the first sub connection line segment 54, thereby improving stability of the potential on the anode 10.
In addition, it is to be noted that, after adjustment of a position of the first sub connection line segment 54 of the second connection signal line 8, in one arrangement, a distance between the second sub connection line segments 55 of two adjacent second connection signal lines 8 may be smaller than a distance between two adjacent first signal lines 3, while a distance between the first sub connection line segments 54 of the two adjacent second connection signal lines 8 may be smaller than, equal to, or greater than a distance between the two adjacent first signal lines 3.
In the direction perpendicular to the plane where the display panel is located, at least part of the anodes 10 further overlaps with at least two first structures 61, the first structures 61 is located at one side of the anode 10 facing away from a light-exit surface of the display panel, and the first structures 61 each include a second connection via-hole 59 and/or a pad metal 60. A width of the pad metal 60 in the second direction y is greater than a line width of the first connection signal line 7, and a width of the pad metal 60 in the first direction x is greater than a line width of the second connection signal line 8.
In some embodiments of the present disclosure, when at least part of the anodes 10 overlaps with the at least two first structures 61, a raised area of the anode 10 can be increased by using the at least two first structures 61, thereby weakening the non-flatness of layer in different regions, thereby effectively improving flatness of the layer of this part of the anodes 10 and effectively ameliorating the color shift phenomenon.
It is to be noted that a shape of the anode 10 shown in
In such a configuration, referring to
It is to be noted that, in an example in which the first signal line 3 is connected to a fan-out line, even if the first-type second connection signal line 91 and the second-type second connection signal line 92 are electrically connected to a same first connection signal line 7, in the design of the fan-out line, only one of the first-type second connection signal line 91 and the second-type second connection signal line 92 can be connected to the fan-out line. In this case, normal transmission of signals may not be affected.
In addition, the first-type second connection signal line 91 and the second-type second connection signal line 92 may also be connected to a plurality of first connection signal lines 7, so that more anodes 10 can overlap with two second connection via-holes 59. In this case, only one of the plurality of first connection signal lines 7 is required to have a connection relationship with the indirect-connection signal line 5. In this case, normal transmission of signals may not be affected, either.
In some embodiments, referring to
With the arrangement, on the one hand, the first pad metal 60 and the second connection signal line 8 are formed by a same patterning process, and the second pad metal 60 and the first connection signal line 7 are formed by a same patterning process, thereby simplifying the process flow; and on the other hand, when part of the anodes 10 overlaps with the second connection via-hole 59, a total layer thickness of the first pad metal 60 and the second pad metal 60 is consistent with a layer thickness of the second connection signal line 8 and the first connection signal line 7, thereby enabling the surface of this part of the anodes 10 flatter.
In one or more embodiments, referring to
It is to be noted that, the overlapping of the anode 10 with the first structures 61 illustrated in the drawings of some embodiments of the present disclosure is only a schematic illustration, which does not represent a limitation on the number of the second connection via-holes 59 and the pad metals 60 overlapping with the anode 10. In some other embodiments of the present disclosure, the anode 10 may also overlap with another number of second connection via-holes 59 and another number of pad metals 60.
The display panel further includes a plurality of pixel rows 17 arranged along the second direction y. The pixel rows 17 each include a plurality of pixel circuits 2 arranged along the first direction x. The pixel circuit group 11 includes a second pixel circuit group 34. The second pixel circuit group 34 includes two adjacent pixel circuits 2 in two adjacent pixel rows 17. The second light-emitting control transistors M5 in the 2nth pixel row 17_2n and the (2n+1)th pixel row 17_2n+1 are adjacently arranged, where n is a positive integer.
The indirect-connection signal line 5 is electrically connected to the first connection signal line 7 through the first connection via-hole 58. The first connection signal line 7 is electrically connected to the second connection signal line 8 through the second connection via-hole 59. The second connection via-hole 59 is close to a junction of the (2n−1)th pixel row 17_2n−1 and the 2nth pixel row 17_2n. In the direction perpendicular to the plane where the display panel is located, at least part of the anodes 10 does not overlap with the second connection via-hole 59.
When the pixel circuits 2 are designed with symmetric rows, the anode connection via-holes 56 between the second light-emitting control transistor M5 and the anode 10 are arranged in a relatively concentrated manner. In the design of the second connection via-hole 59, to avoid the anode connection via-hole 56, the second connection via-hole 59 is arranged at a position far away therefrom, and then at least part of the anodes 10 can avoid the second connection via-hole 59, thereby preventing an influence of the second connection via-hole 59 on the flatness of the anode 10.
In one or more embodiments, the first signal line 3 includes a data line Data and/or a power signal line PVDD. When the first signal line 3 includes the data line Data, the data line Data can adopt the connection manner shown in
It is to be noted that, when the first signal line 3 includes the data line, referring to
In some embodiments of the present disclosure, a structure and an operating principle of the pixel circuit are described by taking the circuit structure shown in
For example, the pixel circuit may include a drive transistor M0, a first sub reset transistor M11, a second sub reset transistor M12, a data write transistor M2, a threshold compensation transistor M3, a first light-emitting control transistor M4, a second light-emitting control transistor M5, and a storage capacitor C.
A gate of the first sub reset transistor M11 is electrically connected to the first scanning signal line Scan1, a first electrode of the first sub reset transistor M11 is electrically connected to the first reset signal line Vref1, and a second electrode of the first sub reset transistor M11 is electrically connected to a gate of the drive transistor M0. The first sub reset transistor M11 is configured to reset the gate of the drive transistor M0 when turned on.
A gate of the second sub reset transistor M12 is electrically connected to the second scanning signal line Scan2, a first electrode of the second sub reset transistor M12 is electrically connected to the second reset signal line Vref2, and a second electrode of the second sub reset transistor M12 is electrically connected to the anode of the light-emitting element 9. The second sub reset transistor M12 is configured to reset the anode of the light-emitting element 9 when turned on.
A gate of the data write transistor M2 and a gate of the threshold compensation transistor M3 are electrically connected to the second scanning signal line Scan2, a first electrode of the data write transistor M2 is electrically connected to the data line Data, a second electrode of the data write transistor M2 is electrically connected to a first electrode of the drive transistor M0, a first electrode of the threshold compensation transistor M3 is electrically connected to a second electrode of the drive transistor M0, and a second electrode of the threshold compensation transistor M3 is electrically connected to the gate of the drive transistor M0. The data write transistor M2 and the threshold compensation transistor M3 are configured to charge the gate of the drive transistor M0 when turned on and perform threshold compensation thereon.
A gate of the first light-emitting control transistor M4 and a gate of the second light-emitting control transistor M5 are electrically connected to a light-emitting control signal line Emit, a first electrode of the first light-emitting control transistor M4 is electrically connected to the power signal line PVDD, a second electrode of the first light-emitting control transistor M4 is electrically connected to the first electrode of the drive transistor M0, a first electrode of the second light-emitting control transistor M5 is electrically connected to the second electrode of the drive transistor M0, and a second electrode of the second light-emitting control transistor M5 is electrically connected to the anode of the light-emitting element 9. The first light-emitting control transistor M4 and the second light-emitting control transistor M5 are configured to transmit a driving current converted by the drive transistor M0 to the light-emitting element 9 when turned on, to drive the light-emitting element 9 to emit light.
Based on a same inventive concept, some embodiments of the present disclosure further provide a display device.
The above-described embodiments are merely preferred embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent substitutions and improvements made within the principle of the present disclosure shall fall into the protection scope of the present disclosure.
Finally, it should be noted that the above-described embodiments are merely for illustrating the present disclosure but not intended to provide any limitation. Although the present disclosure has been described in detail with reference to the above-described embodiments, it should be understood by those skilled in the art that, it is still possible to modify the technical solutions described in the above embodiments or to equivalently replace some or all of the technical features therein, but these modifications or replacements do not cause the essence of corresponding technical solutions to depart from the scope of the present disclosure.
| Number | Date | Country | Kind |
|---|---|---|---|
| 202211689960.4 | Dec 2022 | CN | national |
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| 10614740 | Lee | Apr 2020 | B2 |
| 10615244 | Hou | Apr 2020 | B2 |
| 10777161 | Xu | Sep 2020 | B2 |
| 10802365 | Wang | Oct 2020 | B2 |
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| 11200847 | Xiong | Dec 2021 | B2 |
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| 11355535 | Wang | Jun 2022 | B2 |
| 11393408 | Li | Jul 2022 | B2 |
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| 11508291 | Cao | Nov 2022 | B2 |
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| 11580895 | Zou | Feb 2023 | B1 |
| 11663952 | Kim | May 2023 | B2 |
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| 11721265 | Ma | Aug 2023 | B1 |
| 11735131 | Yamazaki | Aug 2023 | B2 |
| 11751450 | Shang | Sep 2023 | B2 |
| 11798468 | Cao | Oct 2023 | B2 |
| 20190206961 | Kim | Jul 2019 | A1 |
| 20190261512 | Huang | Aug 2019 | A1 |
| 20210384289 | Li | Dec 2021 | A1 |
| 20220077265 | Ma | Mar 2022 | A1 |
| 20220208130 | Park | Jun 2022 | A1 |
| 20220302238 | Zhou | Sep 2022 | A1 |
| 20220310015 | Wang | Sep 2022 | A1 |
| 20220392964 | Wu | Dec 2022 | A1 |
| 20230061191 | Oh | Mar 2023 | A1 |
| 20230209892 | Kim | Jun 2023 | A1 |
| 20230306904 | Huang | Sep 2023 | A1 |
| 20230354659 | Jung | Nov 2023 | A1 |
| 20240046828 | Oh | Feb 2024 | A1 |
| 20240046873 | Roh | Feb 2024 | A1 |
| Number | Date | Country | |
|---|---|---|---|
| 20230326402 A1 | Oct 2023 | US |
