The disclosure relates to a display panel, a display apparatus including the display panel, and a method for manufacturing the display panel.
A display apparatus is an output device that converts obtained or stored electrical information into visual information and displays the visual information to a user.
Display apparatuses include, for example, a monitor device connected to a personal computer or a server computer, a portable computer device, a navigation terminal device, a general television device, Internet Protocol television (IPTV), portable terminal devices such as a smartphone, tablet personal computer (PC), a personal digital assistant (PDA), or a cellular phone, various display apparatuses used to reproduce images such as advertisements or movies in an industrial field, or various kinds of audio/video systems.
A display apparatus includes a display panel to convert electrical information into visual information.
A liquid crystal display (LCD) is a light receiving display apparatus that requires a light source apparatus supplying light from the rear of a display panel and the display panel acting as a switch to pass/block light and changing the supplied light to a desired color.
Recently, as the size of display apparatuses increase or the shapes (e.g., curved) of the display apparatuses becomes more diverse, various types of electronic components are required to drive the display panel.
Provided are a display panel in which a number of electronic components for driving the display panel may be reduced, a display apparatus including the display panel, and a method for manufacturing the display panel.
Further, provided are a display panel in which failure of electronic components for driving the display panel may be prevented, a display apparatus including the display panel, and a method for manufacturing the display panel.
Further still, provided are a display panel in which an increase in a cost of the display apparatus due to electronic components for driving the display panel may be prevented, a display apparatus including the display panel, and a method for manufacturing the display panel.
Additional aspects will be set forth in part in the description which follows and, in part, will be apparent from the description, or may be learned by practice of the presented embodiments.
According to an aspect of the disclosure, a display panel includes: a substrate including an active area including a plurality of pixels, and an outer lead bonding (OLB) area: a first Chip On Film (COF) coupled to the OLB area: a second COF coupled to the OLB area and adjacent to the first COF: a first printed circuit board (PCB) coupled to the first COF; and a second PCB coupled to the second COF, wherein the OLB area may include a first area to which the first COF is coupled, a second area to which the second COF is coupled, and a dummy area between the first area and the second area, and the dummy area may include a conductive pattern electrically connecting the first COF and the second COF.
Each of the first COF and the second COF may include: a plurality of signal pins configured to output signals for driving the plurality of pixels; and a plurality of dummy pins, and the plurality of dummy pins of the first COF may be electrically connected to the plurality of dummy pins of the second COF through the conductive pattern.
Each of the plurality of signal pins may be provided between the plurality of dummy pins.
The first COF may be configured to transmit a power signal to the second COF through the conductive pattern, and the second COF may be configured to transmit the power signal to the second PCB.
The first COF may be configured to transmit a data signal to the second COF through the conductive pattern, and the second COF may be configured to transmit the data signal to the second PCB.
The display panel may further include a third COF coupled to the OLB area and the first PCB, the substrate may include a gate line configured to transmit a gate signal to the plurality of pixels, and the gate line may be electrically connected to the third COF.
The display panel may further include: a third PCB; a third COF coupled to the OLB area and the second PCB; and a fourth COF coupled to the OLB area and the third PCB, the OLB area may include a third area to which the third COF is coupled, a fourth area to which the fourth COF is coupled, and the dummy area between the third area and the fourth area, and the dummy area may include a conductive pattern electrically connecting the third COF and the fourth COF.
Each of the first COF and the second COF may include a source integrated circuit (IC) chip.
The second PCB may be configured to receive a signal from the first PCB through the first COF, the conductive pattern and the second COF.
According to an aspect of the disclosure, a display apparatus includes: a first substrate including a timing controller: a second substrate including an active area including a plurality of pixels, and an outer lead bonding (OLB) area: a first chip on film (COF) coupled to the OLB area: a second COF coupled to the OLB area and adjacent to the first COF: a first printed circuit board (PCB) coupled to the timing controller and the first COF; and a second PCB coupled to the second COF, wherein the OLB area may include a first area to which the first COF is coupled, a second area to which the second COF is coupled, and a dummy area between the first area and the second area, and the dummy area may include a conductive pattern electrically connecting the first COF and the second COF.
Each of the first COF and the second COF may include: a plurality of signal pins configured to output signals for driving the plurality of pixels; and a plurality of dummy pins, and the plurality of dummy pins of the first COF may be electrically connected to the plurality of dummy pins of the second COF through the conductive pattern.
Each of the plurality of signal pins may be provided between the plurality of dummy pins.
The first substrate may further include a power board coupled to the first PCB, the power board may be configured to transmit a power signal to the first PCB, the first COF may be configured to transmit the power signal to the second PCB through the conductive pattern, and the second COF may be configured to transmit the power signal to the second PCB.
The timing controller may be configured to transmit a data signal to the first PCB, the first COF may be configured to transmit the data signal to the second COF through the conductive pattern, and the second COF may be configured to transmit the data signal to the second PCB.
The display apparatus may further include a third COF coupled to the OLB area and the first PCB, the second substrate may include a gate integrated circuit (IC) configured to transmit a gate signal to the plurality of pixels, and the gate IC may be electrically connected to the third COF.
According to an aspect of the disclosure, a method for manufacturing a display panel, includes: disposing a plurality of pixels in an active area of a substrate; coupling a plurality of chip on films (COFs) to a fan-out area in an outer lead bonding (OLB) area; forming a conductive pattern in a dummy area surrounded by the fan-out area in the OLB area; coupling a first printed circuit board (PCB) to a first COF, coupled to one side of the fan-out area based on the dummy area, among the plurality of COFs; and coupling a second PCB to a second COF, coupled to another side of the fan-out area based on the dummy area, among the plurality of COFs.
The OLB area may include a plurality of fan-out areas coupled to the plurality of COFs.
The plurality of COFs may be configured to output signals corresponding to a data values of the plurality of pixels through a conductive pattern formed in the fan-out area.
The conductive pattern may be electrically connected to the first COF.
The second COF may be formed in the dummy area between the fan-out area corresponding to the first COF.
The above and other aspects, features, and advantages of certain embodiments of the present disclosure will be more apparent from the following description taken in conjunction with the accompanying drawings, in which:
Embodiments described in the specification and configurations shown in the accompanying drawings are merely examples of the disclosure, and various modifications may replace the embodiments and the drawings of the disclosure at the time of filing of the application.
The terms used herein are only for the purpose of describing particular embodiments and are not intended to limit to the disclosure.
For example, a singular form of a noun corresponding to an item may include one item or a plurality of the items unless context clearly indicates otherwise.
Further, it should be further understood that the terms “include,” and/or “have,” specify the presence of stated features, integers, steps, operations, elements, components, and/or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
Further, it should be understood that, although the terms “first,” “second,” etc. may be used herein to describe various elements, the elements are not restricted by the terms, and the terms are only used to distinguish one element from another.
Further, the terms such as “˜part”, “˜device”, “˜block”, “˜member”, “˜module”, and the like may refer to a unit for processing at least one function or act. For example, the terms may refer to at least one process processed by at least one hardware, such as field-programmable gate array (FPGA/application specific integrated circuit (ASIC, software stored in memories or processors.
Hereinafter, embodiments of the disclosure is described in detail with reference to the accompanying drawings. Like reference numerals or symbols denoted in the drawings of the specification represent members or components that perform the substantially same functions.
Referring to
In an embodiment, the display apparatus 10 may be a large format display (LFD) installed either outdoors or indoors.
Further, the display apparatus 10 may be a Curved Display Apparatus curved display apparatus in which at least a portion of an edge with a curvature.
The display apparatus 10 may receive content including a video signal and an audio signal from various content sources, and output video and audio corresponding to the video signal and the audio signal, respectively. For example, the display apparatus 10 may receive content data through a broadcast reception antenna or a wired cable, receive content data from a content playback apparatus, or receive content data from a content-providing server of a content provider.
As shown in
The body 11 forms an exterior of the display apparatus 10. The interior of the body 11 may provide components of the display apparatus 10 for displaying the image I and performing various functions. In the embodiment shown in
The screen 12 is formed on a front surface of the body 11, and display the image I. For example, the screen 12 may display a still image or a video, as well as a two-dimensional (2D) plane image or a three-dimensional (3D) stereoscopic image using binocular parallax of a user.
The screen 12 may include a display panel capable of transmitting or blocking light emitted by a light source apparatus, or the like.
A plurality of pixels P may be formed on the screen 12, and the image I displayed on the screen 12 may be formed by light emitted from each of the plurality of pixels P. For example, the image I may be formed on the screen 12 by combining light emitted from the plurality of pixels P like a mosaic.
Each of the plurality of pixels P may emit light of various brightness and various colors. In order to emit light of various colors, each of the plurality of pixels P may include sub-pixels PR, PG, and PB.
The sub-pixels PR, PG, and PB may include a red sub-pixel PR capable of emitting red light, a green sub-pixel PG capable of emitting green light, and a blue sub-pixel PB capable of emitting blue light. For example, the red light may represent light having a wavelength of approximately 700 nm (nanometers, one billionth of a meter) to 800 nm, the green light may represent light having a wavelength of approximately 500 nm to 600 nm, and the blue light may represent light having a wavelength of approximately 400 nm to 500 nm.
By combining the red light of the red sub-pixel PR, the green light of the green sub-pixel PG, and the blue light of the blue sub-pixel PB, each of the plurality of pixels P may emit light of various brightness and various colors.
As shown in
For example, the body 11 may include a light source apparatus 100, a display panel 20 blocking or transmitting light emitted from the light source apparatus 100, a control board 50 controlling operations of the light source apparatus 100 and the display panel 20, and a power board 60 supplying power to the light source apparatus 100 and the display panel 20. In addition, the body 11 may include a bezel 13, a frame middle mold 14, a bottom chassis 15, and a rear substrate 16 for supporting the display panel 20, the light source apparatus 100, the control board 50, and the power board 60.
The rear substrate 16 may include a rear cover forming a rear of the display apparatus 10.
According to one or more embodiments, the light source apparatus 100 may include a point light source that emits white light, and may refract, reflect, and scatter the light to convert the light emitted from the point light source into a uniform surface light. As described above, the light source apparatus 100 may refract, reflect, and scatter the light emitted from the point light source to emit a uniform surface light in a forward direction.
The display panel 20 may be provided in front of the light source apparatus 100, and may block or transmit light emitted from the light source apparatus 100 to form the image I.
A front surface of the display panel 20 may form the screen 12 of the display apparatus 10 described above, and the display panel 20 may form the plurality of pixels P. The plurality of pixels P of the display panel 20 may independently block or transmit the light emitted from the light source apparatus 100. The light transmitted through the plurality of pixels P may form the image I to be displayed on the screen 12.
According to an embodiment, as shown in
The first substrate 22 and the second substrate 28 may be transparent.
The first substrate 22 and the second substrate 28 may fixedly support the pixel electrode 23, the thin-film transistor 24, the liquid crystal layer 25, the common electrode 26, and the color filter 27. The first and second transparent substrates 22 and 28 may be formed of tempered glass or transparent resin.
The first polarizing film 21 and the second polarizing film 29 may be provided on outer sides of the first and second substrates 22 and 28, respectively. The first polarizing film 21 and the second polarizing film 29 may each transmit specific polarized light and block (reflect or absorb) the other polarized light. For example, the first polarizing film 21 may transmit light polarized in a first direction and block, reflect, or absorb the other polarized light. In addition, the second polarizing film 29 may transmit light polarized in a second direction and block, reflect, or absorb the other polarized light. In this instance, the first direction and the second direction may be orthogonal to each other. Thus, the polarized light passing through the first polarizing film 21 may not directly pass through the second polarizing film 29.
The color filter 27 may be provided on an inner side of the second substrate 28. The color filter 27 may include, for example, a red filter 27R transmitting red light, a green filter 27G transmitting green light, and a blue filter 27B transmitting blue light. In addition, the red filter 27R, the green filter 27G, and the blue filter 27B may be provided parallel to each other. A region occupied by the color filter 27 may correspond to the pixel P described above. A region occupied by the red filter 27R may correspond to the red sub-pixel PR, a region occupied by the green filter 27G may correspond to the green sub-pixel PG, and a region occupied by the blue filter 27B may correspond to the blue sub-pixel PB.
The pixel electrode 23 may be provided on the first substrate 22, and the common electrode 26 may be provided on an inner side of the second substrate 28. The pixel electrode 23 and the common electrode 26 may be formed of a metal material through which electricity is conducted and may generate an electric field for changing the arrangement of liquid crystal molecules 115a constituting the liquid crystal layer 25 to be described below.
The TFT 24 may be provided on the first substrate 22. The thin-film transistor 24 may be turned on (closed) or off (opened) by image data provided from a Chip On Film (COF) 20a including a printed circuit board (PCB) 30 and/or a source integrated circuit (IC). In addition, by turning the thin-film transistor 24 on (closing) or off (opening), an electric field may be formed or removed from between the pixel electrode 23 and the common electrode 26.
The liquid crystal layer 25 may be formed between the pixel electrode 23 and the common electrode 26 and may be filled with liquid crystal molecules 25a. The liquid crystal may represent an intermediate state between a solid crystal and a liquid. The liquid crystal may exhibit optical properties depending on a change of the electric field. For example, an arrangement direction of the molecules constituting the liquid crystal may change depending on the change of the electric field. As a result, optical properties of the liquid crystal layer 25 may change according to the presence or absence of the electric field passing through the liquid crystal layer 25. For example, the liquid crystal layer 25 may rotate a polarization direction of light about an optical axis according to the presence or absence of the electric field. Accordingly, the polarized light that has passed through the first polarizing film 21 may be changed in polarization direction while passing through the liquid crystal layer 25 and may pass through the second polarizing film 29.
In one side of the display panel 20, the COF 20a outputting signals for driving a plurality of pixels P to the display panel 20, and the PCB 30 transmitting the signal to the COF 20a may be provided.
According to one or more embodiments, the PCB 30 may be a source PCB including a data driver.
The COF 20a and/or the PCB 30 may include a Display Driver Integrated Circuit (DDIC) that processes digital image data and outputs an analog image signal.
According to one or more embodiments, the display panel 20 may include a plurality of COFs 20a and a plurality of PCBs 30.
Each of the plurality of PCBs 30 may be coupled to the plurality of COFs 20a.
According to one or more embodiments, the number of COFs 20a connected to each of the plurality of PCBs 30 may vary.
The PCB 30 may be electrically coupled to the control board 50 and/or the power board 60. Accordingly, the PCB 30 may electrically connect the display panel 20 and the control board 50 and/or the power board 60.
According to one or more embodiments, the control board 50 may include a connector 50a for coupling to the PCB 30. In an embodiment, the control board 50 may be connected to the PCB 30 directly through the connector 50a, or may be connected to the PCB 30 through a control PCB connected to the connector 50a.
According to various embodiments, the power board 60 may include a connector 60a for coupling to the PCB 30. In an embodiment, the power board 60 may be connected to the PCB 30 directly through the connector 60a, or may be connected to the PCB 30 through a power PCB connected to the connector 60a.
According to one or more embodiments, only at least one PCB 30 among the plurality of PCBs 30 may be connected to the control board 50 and/or the power board 60.
The plurality of COFs 20a may each include a source IC chip, provided on a flexible film that is bendable to drive a plurality of pixels P, and a plurality of pins electrically connectable to the plurality of pixels P and the PCB 30.
The PCB 30 may receive image data and power from the control board 50/power board 60. In addition, the PCB 30 may provide a data signal and a power signal to the display panel 20 through the COF 20a. The data signal may refer to an image signal, and the power signal may refer to a driving current.
The control board 50 may include a control circuit that controls operations of the display panel 20 and/or the light source apparatus 100. For example, the control circuit may process a video signal and/or an audio signal received from an external content source, transmit image data to the display panel 20, and transmit dimming data to the light source apparatus 100.
The power board 60 may include a power supply circuit supplying power to the display panel 20 and/or the light source apparatus 100. The power supply circuit may supply power to the control board 50, the light source apparatus 100, and/or the display panel 20.
The control board 50 and the power board 60 may be implemented with various circuit boards. For example, the power board 60 may include a condenser, a coil, a resistance element, a processor, and the like and a power supply circuit board on which these elements are mounted. In addition, the control board 50 may include a memory, a processor, and a control circuit board on which these elements are mounted.
The control board 50 and the power board 60 may be coupled to at least one of the plurality of PCBs 30.
As shown in
The light source module 110 may include a plurality of light sources 111 emitting light, and a substrate 112 fixedly supporting the plurality of light sources 111.
The plurality of light sources 111 may be arranged in a predetermined pattern to allow light to be emitted with uniform luminance. The plurality of light sources 111 may be arranged to allow a distance between a single light source and each light source adjacent thereto to be the same.
For example, as shown in
According to one or more embodiment, the plurality of light sources 111 may be arranged to allow an approximately equilateral triangle to be formed by three adjacent light sources. In this instance, a single light source may be adjacent to six light sources, and a distance between the single light source and each of the six adjacent light sources may be approximately the same.
However, the arrangement of the plurality of light sources 111 is not limited to that described above, and the plurality of light sources 111 may be arranged in various patterns to allow light to be emitted with uniform luminance.
The light source 111 may employ an element capable of emitting monochromatic light (light having a specific range of wavelengths, for example, blue light) or white light (for example, mixed light of red light, green light, and blue light) in various directions by receiving power. For example, the light source 111 may include a light-emitting diode (LED). The LED may be implemented in a variety of sizes and may include, for example, mini LEDs and/or micro LEDs.
The substrate 112 may fix the plurality of light sources 111 to prevent positions of the light sources 111 from being changed. In addition, the substrate 112 may supply each light source 111 with power for the light source 111 to emit light.
The substrate 112 may fix the plurality of light sources 111. The substrate 112 may include a synthetic resin and/or tempered glass and/or a circuit board on which a conductive power feed line for supplying power to the light source 111 is formed.
The reflector sheet 120 may allow light emitted from the plurality of light sources 111 to be reflected forward or in a direction close to the forward direction.
A plurality of through holes 120a corresponding respectively to the plurality of light sources 111 of the light source module 110 may be formed in the reflector sheet 120. The light sources 111 of the light source module 110 may pass through the through holes 120a and protrude forward of the reflector sheet 120.
For example, in an assembly process of the reflector sheet 120 and the light source module 110, the plurality of light sources 111 of the light source module 110 are inserted into the plurality of through holes 120a formed in the reflector sheet 120. As a result, the substrate 112 of the light source module 110 may be located on the rear of the reflector sheet 120, but the plurality of light sources 111 of the light source module 110 may be located on the front of the reflector sheet 120.
Accordingly, the plurality of light sources 111 may emit light in front of the reflector sheet 120.
The plurality of light sources 111 may emit light in front of the reflector sheet 120 in various directions. Light may be emitted from the light source 111 not only toward the diffuser plate 130, but also toward the reflector sheet 120, and the reflector sheet 120 may reflect the light emitted toward the reflector sheet 120 toward the diffuser plate 130.
The light emitted from the light source 111 may pass various objects, such as the diffuser plate 130, the optical sheet 140, and the like. When the light passes the diffuser plate 130 and the optical sheet 140, a portion of the incident light is reflected from surfaces of the diffuser plate 130 and the optical sheet 140. The reflector sheet 120 may reflect the light reflected by the diffuser plate 130 and the optical sheet 140.
The diffuser plate 130 may be provided in front of the light source module 110 and the reflector sheet 120 to uniformly disperse the light emitted from the light source 111 of the light source module 110.
As described above, the plurality of light sources 111 may be located everywhere on a rear surface of the light source apparatus 100. The plurality of light sources 111 are equidistantly arranged on the rear surface of the light source apparatus 100, but differences in luminance may exist depending on the positions of the plurality of light sources 111.
To eliminate the difference in luminance due to the plurality of light sources 111, the diffuser plate 130 may diffuse the light emitted from the plurality of light sources 111 within the diffuser plate 130. In other words, the diffuser plate 130 may uniformly emit non-uniform light forward from the plurality of light sources 111.
The optical sheet 140 may include various sheets for improving luminance or luminance uniformity. For example, the optical sheet 140 may include a diffuser sheet 141, a first prism sheet 142, a second prism sheet 143, a reflective polarizing sheet 144, and the like.
The diffuser sheet 141 diffuses light for uniformity of luminance. The light emitted from the light source 111 may be diffused by the diffuser plate 130 and then diffused again by the diffuser sheet 141 included in the optical sheet 140.
The first and second prism sheets 142 and 143 may concentrate the light diffused by the diffuser sheet 141, thereby increasing the luminance. The first and second prism sheets 142 and 143 may have triangular prism patterns arranged adjacent to each other to form a plurality of bands.
The reflective polarizing sheet 144 may be a kind of polarizing film, and may transmit a portion of the incident light, and reflect other portions to improve luminance. For example, the reflective polarizing sheet 144 may transmit light polarized in the same direction as a predetermined polarization direction of the reflective polarizing sheet 144 and reflect light polarized in a different direction from the predetermined polarization direction. In addition, the light reflected by the reflective polarizing sheet 144 may be recycled within the light source apparatus 100, and such light recycle may improve the luminance of the display apparatus 10.
The optical sheet 140 is not limited to the sheets or films shown in
The light source apparatus 100 may include the plurality of light sources 111, and may output surface light by diffusing the light emitted from the plurality of light sources 111. The display panel 20 may include a plurality of pixels, and the plurality of pixels may be controlled to allow each of the plurality of pixels to transmit and/or block light. An image I may be formed by light passing through each of the plurality of pixels.
In an embodiment, the display apparatus 10 may perform local dimming to vary a brightness of light for each region of the light source apparatus 100 in association with the output image to improve power consumption while increasing contrast.
For example, the display apparatus 10 may reduce the brightness of light of the light source 111 of the light source apparatus 100 corresponding to a dark portion of an image to make the dark portion of the image darker, and may increase the brightness of light of the light source 111 of the light source apparatus 100 corresponding to a bright portion of the image to make the bright portion of the image brighter. As a result, a contrast ratio of the image may be improved.
Referring to
The substrate 22 may include a TFT glass substrate.
In a manufacturing process of the display panel 20 according to an embodiment, a plurality of pixels P may be provided in an active area 20p of the substrate 22.
The substrate 22 may include the active area 20p in which the plurality of pixels P are positioned.
In the active area 20p, pixel electrodes 23 corresponding to the plurality of pixels P and the TFT 24 for applying an electric field to the liquid crystal layer 25 may be provided.
In the manufacturing process of the display panel 20 according to an embodiment, the plurality of chip on films (COFs) 20a may be coupled to the Outer Lead Bonding (OLB) area 20b of the substrate 22.
According to one or more embodiments, the plurality of COFs 20a may be coupled to the OLB area 20b in an anisotropic conductive film (ACF) bonding method, without being limited thereto.
The substrate 22 may include the OLB area 20b to which the plurality of COFs 20a are coupled.
According to one or more embodiments, the OLB area 20b may include fan-out areas 20c formed to be coupled to the plurality of COFs 20a.
A conductive pattern may be formed in the fan-out area 20c to electrically connect the plurality of COFs 20a and the plurality of pixels P.
The plurality of COFs 20a may output signals corresponding to data values of the plurality of pixels P through the conductive pattern formed in the fan-out area 20c.
The conductive pattern formed in the fan-out area 20c may be defined as a data line (or source line).
Each of the plurality of COFs 20a may output data signals for driving the pixels P arranged in at least one column.
In an embodiment, each of the plurality of COFs 20a may include a source IC chip 20cd for driving the plurality of substrates 22.
The source IC chip 20cd may process a signal received through the PCB 30. For example, the source IC chip 20cd may output an analog image signal based on processing digital image data.
The source IC chip 20cd may receive a power signal through the PCB 30. The source IC chip 20cd may operate based on the power signal received through the PCB 30.
In the manufacturing process of the display panel 20 according to an embodiment, a plurality of PCBs 30 may be coupled to the plurality of COFs 20a.
According to one or more embodiments, the plurality of COFs 20a may be connected to a single PCB 30.
For example, based on the drawing, the PCB 30 placed on the far left and the PCB 30 placed in the middle may each be connected to four COFs 20a, and the PCB 30 placed on the far right may be connected to three COFs 20a, but the connection relationship between the PCB 30 and the COFs 20a is not limited thereto.
According to an embodiment, in the manufacturing process of the display panel 20, at least one COF 20a of the plurality of COFs 20a may be connected to any one PCB 30, and at least one other COF 20a of the plurality of COFs 20a may be connected to another PCB 30.
For example, a first COF 20al of the plurality of COFs 20a may be coupled to a first PCB 30-1, and a second COF 20a2 of the plurality of COFs 20a may be coupled to a second PCB 30-2.
In another example, a third COF 20a3 of the plurality of COFs 20a may be coupled to the second PCB 30-2, and a fourth COF 20a4 of the plurality of COFs 20a may be coupled to a third PCB 30-3.
In the disclosure, a relationship between the COFs 20a, which are adjacent to each other but are connected to different PCBs 30, is defined as a ‘pair of COFs’.
According to an embodiment, in the manufacturing process of the display panel 20, a conductive pattern 20bpd (see
According to one or more embodiments, the OLB area 20b formed between the pair of COFs may be defined as a dummy area 20bd (see
For example, the OLB area 20b between the fan-out areas 20c of each of the pair of COFs may be defined as the dummy area 20bd.
Conventionally, because a COF is not coupled to a dummy area, no conductive pattern is formed. Accordingly, conventionally, a separate electronic component is required to electrically connect a plurality of PCBs.
According to one or more embodiments, the conductive pattern 20bpd for electrically connecting the pair of COFs may be formed in the dummy area 20bd between the fan-out areas 20c corresponding to each of the pair of COFs in the OLB area 20b.
The pair of COFs may be electrically connected to each other, and thus, the PCBs 30 connected to the pair of COFs may also be electrically connected.
For example, the conductive pattern 20bpd that may electrically connect the first COF 20a1 and the second COF 20a2 may be formed in the dummy area 20bd between the fan-out area 20c corresponding to the first COF 20al and the fan-out area 20c corresponding to the second COF 20a2 in the OLB area 20b. As a result, the first PCB 30-1 and the second PCB 30-2 may be electrically connected to each other.
In another example, the conductive pattern 20bpd that may electrically connect the third COF 20a3 and the fourth COF 20a4 may be formed in the dummy area 20bd between the fan-out area 20c corresponding to the third COF 20a3 and the fan-out area 20c corresponding to the fourth COF 20a4 in the OLB area 20b. As a result, the second PCB 30-2 and the third PCB 30-3 may be electrically connected to each other.
According to one or more embodiments, the conductive pattern 20bpd formed in the dummy area 20bd and/or the conductive pattern 20bpd formed in the fan-out area 20c may be formed on the substrate 22 in the manufacturing process of the substrate 22.
According to one or more embodiments, a conductive pattern may be formed on the substrate 22 with a copper (Cu)/copper (Cu) structure in order to reduce a resistance of the conductive pattern formed in the dummy area 20bd.
At least one PCB 30 of the plurality of PCBs 30 may be coupled to the control board 50 and/or the power board 60.
According to one or more embodiments, coupling at least one PCB 30 to the control board 50 and/or power board 60 may include physically coupling the PCB 30 to a connector of the control board 50 and/or the power board 60, as well as coupling the PCB 30 to a connector of the control board 50 and/or the power board 60 by another electronic component (e.g., Flexible Printed Circuit Board (FPCB)).
At least one PCB 30 of the plurality of PCBs 30 may not be coupled to the control board 50 and/or the power board 60.
Because only some of the plurality of PCBs 30 are coupled to the control board 50 and/or the power board 60, the PCB 30 that is not coupled to the control board 50 and/or the power board 6030 may operate by receiving an electrical signal from the PCB 30 that is coupled to the control board 50 and/or the power board 60.
According to an embodiment, as the conductive pattern 20bpd is formed between the pair of COFs, the PCBs 30 may be electrically connected without a separate electronic component for connecting the PCBs 30.
In the manufacturing process of the display panel 20 according to an embodiment, a gate line GL may be formed in one side of the substrate 22.
The gate line GL may be a conductive pattern for transmitting a scan signal to the plurality of substrates 22.
The plurality of substrates 22 may operate in response to receiving the scan signal through the gate line GL.
The scan signal may be output through the gate line GL to sequentially operate the plurality of substrates 22.
According to one or more embodiments, any one COF 20a of the plurality of COFs 20a may be electrically connected to the gate line GL.
For example, a COF 20af, disposed at an edge where the gate line GL is located, from among the plurality of COFs 20a may be electrically connected to the gate line GL.
According to one or more embodiments, an edge portion where wiring (conductive pattern) is formed on the substrate 22 may be covered in a black matrix method, thereby preventing the wiring from being exposed to the outside.
Referring to
For example, referring to
The plurality of COFs 20a may be coupled to a plurality of PCBs 30. Each of the plurality of COFs 20a may include the source IC chip 20cd.
At least a portion of the COFs 20a from among the plurality of COFs 20a may be coupled to any one PCB 30, and the remaining COFs 20a may be coupled to another PCB 30. For example, referring to
The number of pair of COFs may vary depending on the number of PCBs 30. For example, in a case where two PCBs 30 are connected to the plurality of COFs 20a, the display panel 20 may include a pair of COFs.
In another example, referring to
In still another example, referring to
The examples shown in
Referring to
The flexible film 20f may include a printed circuit board and the plurality of pins 20c1 and 20c2.
The plurality of pins 20c1 and 20c2 may include a plurality of input pins 20c2 connectable to the PCB 30 and a plurality of output pins 20c1 coupled to the OLB area 20b.
According to one or more embodiments, the plurality of output pins 20c1 may include a plurality of valid output pins 20cv electrically connected to the pixels P provided in the active area 20p, and a plurality of dummy output pins 20dv that are not electrically connected to the pixels P provided in the active area 20p.
The plurality of valid output pins 20cv may be defined as signal pins, and may each be provided between the plurality of dummy output pins 20dv.
According to one or more embodiments, the plurality of valid output pins 20cv may be electrically connected to a data line, and the like, formed on the substrate 22.
In an embodiment, a plurality of dummy output pins 20dv of at least one COF 20a of the plurality of COFs 20a may not be connected to any conductive pattern.
In an embodiment, a plurality of dummy output pins 20dv of at least one COF 20a of the plurality of COFs 20a may be connected to a gate line GL.
For example, at least a portion of the dummy output pins 20dv of the COF 20a, provided on one side of the display panel 20 where the gate line GL is formed, may be connected to the gate line GL.
In an embodiment, a plurality of dummy output pins 20dv of a pair of COFs from among the plurality of COFs 20a may be electrically connected to each other by the conductive pattern 20bpd formed in the dummy area 20bd.
For example, a right dummy output pin 20dv of the COF 20a provided on the left in a pair of COFs may be electrically connected to a left dummy output pin 20dv of the COF 20a provided on the right in the pair of COFs through the conductive pattern 20bpd.
According to one or more embodiments, a plurality of dummy input pins 20dk and the plurality of dummy output pins 20dv may be connected to each other through the source IC chip 20cd. The source IC chip 20cd may be designed to transmit signals received from the plurality of dummy input pins 20dk to the plurality of dummy output pins 20dv, or to output signals received from the plurality of dummy output pins 20dv to the plurality of dummy input pins 20dk.
According to an embodiment, a dummy pin of a COF that is not used conventionally may be used, thereby achieving electrical connection between a pair of COFs. According to an embodiment, electrical connection between the PCBs 30 may be made without additional electronic components.
According to one or more embodiments, the plurality of input pins 20c2 may include a plurality of valid input pins 20ck that are electrically connected to the PCB 30 and receive significant signals (e.g., power signals and/or data signals).
According to one or more embodiments, the plurality of input pins 20c2 may include the plurality of dummy input pins 20dk that are not electrically connected to the PCB 30, or that are electrically connected to the PCB 30 but do not receive any signal.
The plurality of valid input pins 20ck may be defined as signal pins, and may each be provided between the plurality of dummy input pins 20dk.
According to one or more embodiments, the plurality of valid input pins 20ck may be electrically connected to a signal output pin of the PCB 30. The signal output pin of the PCB 30 may output a data signal and/or a power signal.
In an embodiment, a plurality of dummy input pins 20dk of at least one COF 20a of the plurality of COFs 20a may be connected to the signal output pin of the PCB 30 and/or a signal reception pin of the PCB 30, but may not receive any signal from the signal output pin of the PCB 30, or may not output any signal to the signal reception pin of the PCB 30.
In an embodiment, a plurality of dummy input pins 20dk of a pair of COFs from among the plurality of COFs 20a may receive significant signals (e.g., data signal and/or power signal) from the signal output pin of the PCB 30, or may transmit significant signals (e.g., data signal and/or power signal) to the signal reception pin of the PCB 30.
For example, a right dummy input pin 20dk of the COF 20a provided on the left in a pair of COFs may receive a significant signal (e.g., data signal and/or power signal) from the PCB 30, and a left dummy input pin 20dk of the COF 20a provided on the right in the pair of COFs may transmit a significant signal (e.g., data signal and/or power signal) received from another PCB 30 to the PCB 30.
According to an embodiment, a pair of COFs may transmit and receive signals to and from each other using dummy pins.
Referring to
The fan-out area 20c is an area to which each of the plurality of COFs 20a is coupled, and the fan-out areas 20c may be formed alternately with the dummy areas 20bd at a predetermined interval.
According to an embodiment, the fan-out area 20c may include a plurality of fan-out areas 20c separated from each other.
A single COF 20a may be coupled to each of the plurality of fan-out areas 20c.
The dummy area 20bd may be formed between each of the plurality of fan-out areas 20c formed alternately.
Accordingly, the dummy area 20bd may include a plurality of dummy areas 20bd separated from each other.
According to one or more embodiments, the conductive pattern 20bpd connected to the fan-out areas 20c provided on both sides may be formed in at least one dummy area 20bd of the plurality of dummy areas 20bd.
According to one or more embodiments, the conductive pattern 20bpd may be formed in the dummy area 20bd formed between a pair of fan-out areas 20c, coupled to a pair of COFs, from among the plurality of dummy areas 20bd.
According to an embodiment, an electrical path between a pair of COFs may be formed by forming the conductive pattern 20bpd in a portion of the dummy areas 20bd in the OLB area 20b of the substrate 22.
Referring to
According to an embodiment, the first COF 20al and the second COF 20a2 may be coupled to the OLB area 20b.
The first COF 20al and the second COF 20a2 may form a pair COF relationship with each other.
For example, the first COF 20a1 and the second COF 20a2 may be provided in the OLB area 20b, be provided adjacent to each other, and be coupled to different PCBs 30-1 and 30-2.
The OLB area 20b may include a first area (fan-out area 20c) to which the first COF 20a1 is coupled, a second area (fan-out area 20c) to which the second COF 20a2 is coupled, and a dummy area 20bd between the first area and the second area.
The first COF 20a1 may be connected to the first PCB 30-1. The second COF 20a2 may be connected to the second PCB 30-2.
The first PCB 30-1 or the second PCB 30-2 may be coupled to the control board 50 and/or the power board 60.
The plurality of valid input pins 20ck of the first COF 20al may receive a data signal and/or power signal from the first PCB 30-1.
The data signal and/or power signal may correspond to a signal received by the first PCB 30-1 through the control board 50 and/or power board 60.
According to one or more embodiments, the plurality of valid input pins 20ck of the first COF 20a1 may receive data signals corresponding to data values of pixels P provided in at least one column corresponding to the first COF 20a1.
The source IC chip 20cd of the first COF 20al may output a signal for driving the plurality of substrates 22 through the plurality of valid output pins 20cv, based on processing the signal received through the plurality of valid input pins 20ck.
The plurality of valid output pins 20cv may be connected to a data line and/or a power line formed in the active area 20p.
The plurality of dummy input pins 20dk of the first COF 20a1 may receive a data signal and/or a power signal from the first PCB 30-1.
According to one or more embodiments, the plurality of dummy input pins 20dk of the first COF 20a1 may receive data signals corresponding to data values of the pixels P provided in at least one column corresponding to the second PCB 30-2.
The data signal and/or power signal received from the first PCB 30-1 through the plurality of dummy input pins 20dk may be output through the plurality of dummy output pins 20dv.
The plurality of dummy output pins 20dv may be connected to the plurality of dummy output pins 20dv of the second COF 20a2 through the conductive pattern 20bpd formed in the dummy area 20bd.
The plurality of dummy output pins 20dv of the second COF 20a2 may output the data signal and/or power signal, received through the conductive pattern 20bpd, through the plurality of dummy input pins 20dk.
Based on processing the data signal and/or power signal output by the plurality of dummy input pins 20dk of the second COF 20a2, the second PCB 30-2 may transmit the data signal and/or power signal to the source IC chip 20cd of the second COF 20a2 through the plurality of valid input pins 20ck.
Based on processing the signal received through the plurality of valid input pins 20ck, the source IC chip 20cd of the second COF 20a2 may output a signal for driving the plurality of substrates 22 through the plurality of valid output pins 20cv. The plurality of valid output pins 20cv may be connected to a data line and/or a power line formed in the active area 20p.
According to an embodiment, the power signal and/or data signal may be transmitted to the second PCB 30-2 without a separate electronic component for connecting the first PCB 30-1 and the second PCB 30-2.
Referring to
The second PCB 30-2 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the second PCB 30-2 may include the second COF 20a2 closest to the plurality of COFs 20a coupled to the first PCB 30-1.
A signal transmitted through the control board 50 and/or the power board 60 may be transmitted to the second PCB 30-2 through the dummy pins 20dk and 20dv of the first COF 20a1, the conductive pattern 20bpd formed in the dummy area 20bd, and the dummy pins 20dk and 20dv of the second COF 20a2.
According to one or more embodiments, the second PCB 30-2 may be coupled to the third COF 20a3 provided on one side of the substrate 22 adjacent to a gate line GL.
The third COF 20a3 may transmit a scan signal to the gate line GL.
In an embodiment, the source IC chip 20cd of the third COF 20a3 may output the scan signal through the plurality of dummy output pins 20dv.
Referring to
The second PCB 30-2 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the second PCB 30-2 may include the second COF 20a2 closest to the plurality of COFs 20a coupled to the first PCB 30-1.
The second PCB 30-2 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the second PCB 30-2 may include the third COF 20a3 closest to a plurality of COFs 20a coupled to the third PCB 30-3.
The third PCB 30-3 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the third PCB 30-3 may include the fourth COF 20a4 closest to the plurality of COFs 20a coupled to the second PCB 30-2.
A signal transmitted through the control board 50 and/or the power board 60 may be transmitted to the second PCB 30-2 through the dummy pins 20dk and 20dv of the first COF 20a1, the conductive pattern 20bpd formed in the dummy area 20bd between the fan-out area 20c corresponding to the first COF 20a1 and the fan-out area 20c corresponding to the second COF 20a2, and the dummy pins 20dk and 20dv of the second COF 20a2.
The signal transmitted through the control board 50 and/or the power board 60 may be transmitted to the third PCB 30-3 through the second PCB 30-2, the dummy pins 20dk and 20dv of the third COF 20a3, the conductive pattern 20bpd formed in the dummy area 20bd between the fan-out area 20c corresponding to the third COF 20a3 and the fan-out area 20c corresponding to the fourth COF 20a4, and the dummy pins 20dk and 20dv of the fourth COF 20a4.
According to one or more embodiments, the third PCB 30-3 may be coupled to a fifth COF 20a5 provided on one side of the substrate 22 adjacent to the gate line GL.
The fifth COF 20a5 may transmit the scan signal to the gate line GL.
In an embodiment, the source IC chip 20cd of the fifth COF 20a5 may output the scan signal through the plurality of dummy output pins 20dv.
Referring to
The second PCB 30-2 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the second PCB 30-2 may include the second COF 20a2 closest to the plurality of COFs 20a coupled to the first PCB 30-1.
The second PCB 30-2 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the second PCB 30-2 may include the third COF 20a3 closest to a plurality of COFs 20a coupled to the third PCB 30-3.
The third PCB 30-3 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the third PCB 30-3 may include the fourth COF 20a4 closest to the plurality of COFs 20a coupled to the second PCB 30-2.
The third PCB 30-3 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the third PCB 30-3 may include the fifth COF 20a5 closest to a plurality of COFs 20a coupled to the fourth PCB 30-4.
The fourth PCB 30-4 may be coupled to the plurality of COFs 20a, and the plurality of COFs 20a coupled to the fourth PCB 30-4 may include a sixth COF 20a6 closest to the plurality of COFs 20a coupled to the third PCB 30-3.
A signal transmitted through the control board 50 and/or the power board 60 may be transmitted to the second PCB 30-2 through the dummy pins 20dk and 20dv of the first COF 20a1, the conductive pattern 20bpd formed in the dummy area 20bd between the fan-out area 20c corresponding to the first COF 20a1 and the fan-out area 20c corresponding to the second COF 20a2, and the dummy pins 20dk and 20dv of the second COF 20a2.
The signal transmitted through the control board 50 and/or the power board 60 may be transmitted to the third PCB 30-3 through the second PCB 30-2, the dummy pins 20dk and 20dv of the third COF 20a3, the conductive pattern 20bpd formed in the dummy area 20bd between the fan-out area 20c corresponding to the third COF 20a3 and the fan-out area 20c corresponding to the fourth COF 20a4, and the dummy pins 20dk and 20dv of the fourth COF 20a4.
The signal transmitted through the control board 50 and/or the power board 60 may be transmitted to the fourth PCB 30-4 through the third PCB 30-3, the dummy pins 20dk and 20dv of the fifth COF 20a5, the conductive pattern 20bpd formed in the dummy area 20bd between the fan-out area 20c corresponding to the fifth COF 20a5 and the fan-out area 20c corresponding to the sixth COF 20a6, and the dummy pins 20dk and 20dv of the sixth COF 20a6.
According to one or more embodiments, the fourth PCB 30-4 may be coupled to a seventh COF 20a7 provided on one side of the substrate 22 adjacent to the gate line GL.
The seventh COF 20a7 may transmit the scan signal to the gate line GL.
In an embodiment, the source IC chip 20cd of the seventh COF 20a7 may output the scan signal through the plurality of dummy output pins 20dv.
According to an embodiment, in a case where the display panel 20 includes a plurality of PCBs 30, the plurality of PCBs 30 may be electrically connected using the dummy area 20bd of the OLB area 20b without a separate electronic component.
According to one or more embodiments, although it is assumed in
In an embodiment, the PCB 30 connected to the control board 50 and/or the power board 60 may transmit a signal to an adjacent PCB 30 through the COF 20a that is located outermost among the plurality of COFs 20a connected thereto, and through the conductive pattern 20bpd formed in the dummy area 20bd located next to the fan-out area 20c corresponding to the COF 20a located outermost.
For example, in a case where the PCB 30 connected to the control board 50 and/or the power board 60 is the second PCB 30-2, the second PCB 30-2 may transmit a signal to the first PCB 30-1 through the conductive pattern 20bpd formed in the dummy area 20bd between the fan-out area 20c corresponding to the second COF 20a2 and the fan-out area 20c corresponding to the first COF 20al, and may transmit the signal to the third PCB 30-3 through the conductive pattern 20bpd formed in the dummy area 20bd between the fan-out area 20c corresponding to the third COF 20a3 and the fan-out area 20c corresponding to the fourth COF 20a4.
Referring to
The rear substrate 16 (see
The control board 50 may include a timing controller 55. For example, the control board 50 may include a control PCB including the timing controller 55.
The power board 60 may include a power supply 65. The power supply 65 may supply power supplied from an external power source to the display apparatus 10. For example, the power supply 65 may process (e.g., rectify, reduce noise) a voltage supplied from an external power source and transmit the processed voltage to an electronic component (e.g., the PCB 30) included in the display apparatus 10.
The substrate 22 of the display panel 20 may include the active area 20p and the OLB area 20b.
The display apparatus 10 may include a tuner and a receiving terminal for receiving content including a video signal and/or an audio signal from content sources.
The receiving terminal may receive the video signal and audio signal from content sources through a cable. For example, the receiving terminal may include a component (YPbPr/RGB) terminal, a Composite Video Blanking and Sync (CVBS) terminal, an audio terminal, a High-Definition Multimedia Interface (HDMI) terminal, and a Universal Serial Bus (USB) terminal.
The tuner may receive a broadcast signal from a broadcast reception antenna or a wired cable. In addition, the tuner may extract a broadcast signal of a channel selected by a user from among broadcast signals. For example, the tuner may pass a broadcast signal having a frequency corresponding to the channel selected by the user among a plurality of broadcast signals received through the broadcast reception antenna or wired cable, and may block a broadcast signal having a different frequency.
As described above, a content receiver may receive the video signal and/or audio signal from the content sources through the receiving terminal and/or the tuner. The content receiver may output the video signal and/or audio signal received through the receiving terminal and/or the tuner to an image processor. Based on processing the video signal and/or audio signal from the content receiver, the image processor may transmit image data to the timing controller 55.
The timing controller 55 may receive the image data from the image processor. The timing controller 55 may output the image data and a driving control signal to the first PCB 30-1. The driving control signal may include a scan control signal and a data control signal. The scan control signal and the data control signal may be used to control operations of a scan driver and a data driver, respectively.
The first PCB 30-1 may receive the scan control signal and the data control signal from the timing controller 55.
The first PCB 30-1 may receive a power signal from the power supply 65.
The first PCB 30-1 may include a signal processor 35 for processing the data control signal and the scan control signal received from the timing controller 55 and/or the power signal received from the power supply 65.
For example, the signal processor 35 may have a configuration for improving an electromagnetic interface (EMI) of the data control signal and the scan control signal received from the timing controller 55 and/or for converting a digital signal into an analog signal.
For example, the signal processor 35 may include a power IC for processing the power signal received from the power supply 65.
The first PCB 30-1 may output the processed signal to the plurality of COFs 20a connected to the first PCB 30-1, and the source IC chip 20cd included in each of the plurality of COFs 20a 20cd may output signals for driving a plurality of pixels P based on the signal output from the first PCB 30-1.
According to one or more embodiments, the first PCB 30-1 may transmit, to the second PCB 30-2, the scan control signal and the data control signal received from the timing controller 55 through the first COF 20a1.
According to one or more embodiments, the first PCB 30-1 may transmit the power signal received from the power supply 65 to the second PCB 30-2 through the first COF 20a1.
For example, the first PCB 30-1 may transmit, to the second PCB 30-2, the scan control signal, the data control signal and/or the power signal through the first COF 20a1, the conductive pattern 20bpd between the first COF 20al and the second COF 20a2, and the second COF 20a2.
The second PCB 30-2 may process the data control signal and the scan control signal received from the first PCB 30-1, and may output the processed signal to the plurality of COFs 20a connected to the second PCB 30-2.
The second PCB 30-2 may operate based on the power signal received from the first PCB 30-1.
In an embodiment, where the display apparatus 10 includes three or more PCBs 30, the second PCB 30-2 may also transmit, to the third PCB 30-3, the scan control signal, data control signal and/or power signal through the third COF 20a3.
According to an embodiment, a separate electronic component for connecting the PCBs 30 is not required, thereby reducing a cost of the display apparatus.
Further, according to an embodiment, economic loss caused by damage to a separate electronic component for connecting the PCBs 30 may be prevented.
According to an embodiment, the display panel may include the substrate 22 including the active area 20p including a plurality of pixels P, and the OLB area 20b; the first COF 20a1 coupled to the OLB area: the second COF 20a2 coupled to the OLB area and be adjacent to the first COF: the first PCB 30-1 coupled to the first COF; and the second PCB 30-2 coupled to the second COF, wherein the OLB area may include a first area to which the first COF is coupled, a second area to which the second COF is coupled, and the dummy area 20bd between the first area and the second area, and the dummy area may include the conductive pattern 20bpd for electrically connecting the first COF and the second COF.
According to an embodiment, each of the first COF and the second COF may include: a plurality of signal pins configured to output signals for driving the plurality of pixels; and a plurality of dummy pins, and the plurality of dummy pins of the first COF may be configured to be electrically connected to the plurality of dummy pins of the second COF through the conductive pattern.
According to an embodiment, each of the plurality of signal pins may be configured to be provided between the plurality of dummy pins.
According to an embodiment, the first COF may be configured to transmit a power signal to the second COF through the conductive pattern, and the second COF may be configured to transmit the power signal to the second PCB.
According to an embodiment, the first COF may be configured to transmit a data signal to the second COF through the conductive pattern, and the second COF may be configured to transmit the data signal to the second PCB.
According to an embodiment, the display panel may further include a third COF coupled to the OLB area and the first PCB, and the substrate may include a gate line for transmitting a gate signal to the plurality of pixels, and the gate line may be configured to be electrically connected to the third COF.
According to an embodiment, the display panel may further include a third PCB; a third COF coupled to the OLB area and the second PCB; and a fourth COF coupled to the OLB area and the third PCB, wherein the OLB area may include a third area to which the third COF is coupled, a fourth area to which the fourth COF is coupled, and the dummy area between the third area and the fourth area, and the dummy area may include a conductive pattern for electrically connecting the third COF and the fourth COF.
According to an embodiment, each of the first COF and the second COF may include a source IC chip.
According to an embodiment, the second PCB may be configured to receive a signal from the first PCB through the first COF, the conductive pattern and the second COF.
According to an embodiment, the display apparatus 10 may include the first substrate 16 including the timing controller 55; the second substrate 22 including the active area 20p including a plurality of pixels P and the OLB area 20b; the first COF 20a1 coupled to the OLB area: the second COF 20a2 coupled to the OLB area and be adjacent to the first COF; the first PCB 30-1 coupled to the timing controller and the first COF; and the second PCB 30-2 coupled to the second COF, wherein the OLB area may include a first area to which the first COF is coupled, a second area to which the second COF is coupled, and the dummy area 20bd between the first area and the second area, and the dummy area may include the conductive pattern 20bpd for electrically connecting the first COF and the second COF.
According to an embodiment, each of the first COF and the second COF may include: a plurality of signal pins configured to output signals for driving the plurality of pixels; and a plurality of dummy pins, and the plurality of dummy pins of the first COF may be configured to be electrically connected to the plurality of dummy pins of the second COF through the conductive pattern.
According to an embodiment, each of the plurality of signal pins may be configured to be provided between the plurality of dummy pins
According to an embodiment, the first substrate may further include a power board coupled to the first PCB, the power board may be configured to transmit a power signal to the first PCB, the first COF may be configured to transmit the power signal to the second PCB through the conductive pattern, and the second COF may be configured to transmit the power signal to the second PCB.
According to an embodiment, the timing controller may be configured to transmit a data signal to the first PCB, the first COF may be configured to transmit the data signal to the second COF through the conductive pattern, and the second COF may be configured to transmit the data signal to the second PCB.
According to an embodiment, the display apparatus may further include a third COF coupled to the OLB area and the first PCB, wherein the second substrate may include a gate line for transmitting a gate signal to the plurality of pixels, and the gate line may be configured to be electrically connected to the third COF.
According to an embodiment, the display apparatus may further include a third PCB; a third COF coupled to the OLB area and the second PCB; and a fourth COF coupled to the OLB area and the third PCB, wherein the OLB area may include a third area to which the third COF is coupled, a fourth area to which the fourth COF is coupled, and the dummy area between the third area and the fourth area, and the dummy area may include a conductive pattern for electrically connecting the third COF and the fourth COF.
According to an embodiment, each of the first COF and the second COF may include a source IC chip.
According to an embodiment, the first PCB may be configured to receive a control signal from the timing controller, and the second PCB may be configured to receive the control signal from the first PCB through the first COF, the conductive pattern and the second COF.
According to an embodiment, the first substrate may further include a power board coupled to the first PCB, the first PCB may be configured to receive a power signal from the power board, and the second PCB may be configured to receive the power signal from the first PCB through the first COF, the conductive pattern and the second COF.
According to an embodiment, a method for manufacturing the display panel 20 may include: disposing a plurality of pixels P in the active area 20p of the substrate 22: coupling a plurality of COFs 20a to the fan-out area 20c in the OLB area 20b; forming the conductive pattern 20bpd in the predetermined dummy area 20bd surrounded by the fan-out area in the OLB area: coupling the first PCB 30-1 to the first COF 20a1, coupled to one side of the fan-out area based on the predetermined dummy area, among the plurality of COFs; and coupling the second PCB 30-2 to the second COF 20a2, coupled to another side of the fan-out area based on the predetermined dummy area, among the plurality of COFs.
Although certain embodiments the disclosure has been shown and described in relation to specific embodiments, it would be appreciated by those skilled in the art that changes and modifications may be made in these embodiments without departing from the principles and scope of the disclosure, the scope of which is defined in the claims and their equivalents.
Number | Date | Country | Kind |
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10-2023-0025402 | Feb 2023 | KR | national |
This application is a by-pass continuation application of International Application No. PCT/KR2023/018579, filed on Nov. 17, 2023, which is based on and claims priority to Korean Patent Application No. 10-2023-0025402, filed on Feb. 24, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated by reference herein in their entireties.
Number | Date | Country | |
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Parent | PCT/KR23/18579 | Nov 2023 | WO |
Child | 18391148 | US |