Patent Grant
7382343
1. Field of the Invention
The present invention relates to a display panel driving method, a display panel driver circuit, and a liquid crystal display device, which are capable of inverting a polarity of a data signal which is applied to respective picture elements of a display panel every predetermined time, i.e., executing the alternating current drive and, more particularly, an active matrix type liquid crystal display panel driving method, a liquid crystal panel driver circuit, and a liquid crystal display device.
2. Description of the Related Art
In recent years, as a display for OA devices such as the notebook computer (mobile PC), etc. as well as various devices such as the digital video camera, the telephone, etc., the liquid crystal display device is rapidly spreading. Such liquid crystal display device is still inferior in screen size, picture quality, cost, etc. to the displaying means such as the CRT (cathode ray tube), etc., nevertheless its excellent features such as low power consumption, light weight, space saving, etc. are watched with interest.
The active matrix type liquid crystal display panel has such a structure that a liquid crystal is sealed between two glass substrates. A plurality of picture element electrodes, which are arranged in the horizontal direction and the vertical direction, and a plurality of switching elements, which turn ON/OFF the voltage applied to the picture element electrodes, are formed on one glass substrate. As the switching element, a thin film transistor (abbreviated as a “TFT” hereinafter) is often employed.
Also, color filters and opposing electrode are formed on the other glass substrate. These two glass substrates are arranged such that a face on which the picture element electrodes are formed and a face on which the opposing electrode are formed are opposed to each other. Three color filters, i.e., red (R), green (G), blue (B) filters are formed as the color filters. The R, G, B color filters are arranged in predetermined sequence to correspond to respective picture element electrodes. The substrate having the TFTs thereon is called a TFT substrate, and the substrate having the opposing electrode thereon is called an opposing substrate.
In addition, a pair of polarizing plates are arranged so as to put the TFT substrate and the opposing substrate, between which the liquid crystal is sealed, between them. Normally, polarizing axes of a pair of polarizing plates are arranged to intersect orthogonally with each other.
A plurality of picture elements (not shown) which are arranged in a matrix, a plurality of data bus lines 502a and a plurality of gate bus lines 503a, and a plurality of TFTs (not shown) which are connected between the picture elements and the data bus lines 502a and the gate bus lines 503a respectively are provided to the liquid crystal display panel 501. The data driver 502 outputs data signals (display data) to the data bus lines 502a. The gate driver 503 outputs a predetermined scanning signal to the gate bus lines 503b in sequence at timings which are in synchronism with the horizontal synchronizing signal. The TFTs are turned ON when the predetermined scanning signal is supplied to the gate bus lines 503a to transmit the data signals, which are supplied to the data bus lines 502a, to picture element electrodes.
The input controlling portion 505 receives signals such as image signals, synchronizing signals, operating clocks, etc. from a display control information source (referred to as a “personal computer” hereinafter) 504 such as a personal computer, and then outputs the image signals to the data driver 502 at predetermined timings and also supplies the clock signals to the gate driver 503. The reference voltage power supply 506 supplies reference voltages, which is applied to the picture elements, to the data driver 502.
The input controlling portion 505 is composed of an input interface (I/F) portion 511, an input data latch circuit 512, and a data output circuit 513. The input. I/F portion 511 receives display control information (the image signal, the horizontal, and vertical synchronizing signal, the operation control signal, etc.) from the personal computer 504, and transmits predetermined signals to the input data latch circuit 512, the data output circuit 513, etc. The input data latch circuit 512 holds temporarily the image signals (R, G, B). Also, the data output circuit 513 performs timing control, waveform shaping, etc. of the image signal, and then outputs them to the data driver 502.
In such configuration, the image data which are received via the input I/F portion 511 are output to the data driver 502 at a predetermined timing via the input data latch circuit 512 and the data output circuit 513. Based on an inverting period of the reference voltage supplied from the reference voltage power supply 506, the data driver 502 inverts the polarity of the data signal, which is applied to the picture element, at a predetermined period.
Where the wording “inverting period of the reference voltage” means such an inverting period that the reference voltage being applied between the picture element electrode and the opposing electrode in the liquid crystal display panel repeats a positive polarity voltage and a negative polarity voltage invertedly relative to a common voltage alternatively. Normally, such inverting period of the reference voltage is set to a constant inverting period.
As described above, the active matrix type liquid crystal display panel can be driven by the alternating current voltage. For example, the voltage whose polarity can be changed into a positive polarity (+) and a negative polarity (−) every predetermined time interval with respect to the voltage, which applied to the opposing electrode, is supplied to the picture element electrode. It is preferable that the voltage being applied to the liquid crystal should have a positive voltage waveform and a negative voltage waveform symmetrically. However, even if the alternating current voltage which has the positive voltage waveform and the negative voltage waveform symmetrically is applied to the picture element electrodes, the positive voltage waveform and the negative voltage waveform which are applied actually to the liquid crystal are not formed in a symmetrical manner. Therefore, a transmittance of light obtained when the positive voltage is applied and a transmittance of light obtained when the negative voltage is applied become different. As a result, a luminance is varied in a period of the alternating current voltage being applied to the picture element electrode to thus cause a flicker. This phenomenon is called a flicker.
In the prior art, a method of changing the voltage applied to the opposing electrode, a method of setting the polarity of the voltage applied to the adjacent picture element electrodes differently in the horizontal direction and the vertical direction, and a method of increasing the frequency of the polarity inversion are known as a method of suppressing such flicker. For example, such technologies have been disclosed in Patent Application Publication (KOKAI) Sho 62-113129, Patent Application Publication (KOKAI) Hei 2-34818, Patent Application Publication (KOKAI) Hei 6-149174, Patent Application Publication (KOKAI) Hei 7-175448, and Patent Application Publication (KOKAI) Hei 9-204159.
In case the voltages which has the different polarity are applied to the adjacent picture element electrodes, there may be considered (i) a method by which the voltage with the same polarity is applied to the picture element electrodes being aligned in the vertical direction while the voltage with the opposite polarity is applied to the neighboring picture element electrodes being aligned in the horizontal direction, (ii) a method by which the voltage with the same polarity is applied to the picture element electrodes being aligned in the horizontal direction while the voltage with the opposite polarity is applied to the neighboring picture element electrodes being aligned in the vertical direction, (iii) a method by which the voltages with mutually different polarities are applied to the picture element electrodes being adjacent in the vertical direction and the horizontal direction, etc. Where the pattern indicating the polarity of the voltage, which is applied to the picture element electrodes of the liquid crystal display panel, is called the polarity pattern.
The inventors of the present invention have concluded that the above prior art contains following problems. That is, the flicker becomes conspicuous when the vertical-striped pattern (display pattern) is displayed in the polarity pattern (i), when the lateral-striped pattern is displayed in the polarity pattern (ii), and when the mosaic pattern (checker pattern) is displayed in the polarity pattern (iii). These patterns (display patterns) are relatively often used in the display for the computer system.
Also, according to the method of changing the voltage applied to the opposing electrode, the control becomes complicated and also the circuit scale is increased. In addition, according to the method of increasing the inverting frequency, the circuit configuration becomes complicated.
It is an object of the present invention to provide a display panel driving method, a display panel driver circuit, and a liquid crystal display device, which are capable of reducing or preventing generation of flickers with a relatively simple circuit configuration.
The above subjects can be overcome by providing, for example, as shown in
In this case, as shown in
In the present invention, the image data which are to be displayed adjacently are extracted and monitored in sequence by the image data extracting means 512a and the pattern detecting means 514a, and then the reference voltage is supplied from the inverting period controlling means 514b at a different polarity inverting period, which is previously prepared, when a particular display pattern which generates the flicker or an increase of power consumption is decided.
Therefore, according to the liquid crystal display device of the present invention, in the event that the polarity inversion of the image data being applied to the picture elements is performed based on the polarity inverting period which is set as the initial state, the polarity inverting period can be switched to the different polarity inverting period when the image data which need to display the particular pattern causing the flicker or the increase in the power consumption on the display screen are input. As a result, the flicker or the increase of power consumption of the liquid crystal display device can be suppressed by avoiding the synchronization between the polarity inverting period of the image data and the display pattern.
Embodiments of the present invention will be explained with reference to the accompanying drawings hereinafter.
The liquid crystal display panel 40 comprises a TFT substrate 10 and an opposing substrate 20 which are arranged to face to each other, and a liquid crystal 30 which is sealed between the TFT substrate 10 and the opposing substrate 20.
The TFT substrate 10 includes a glass substrate 11, gate bus lines 12 formed on the glass substrate 11, data bus lines 13, picture element electrodes 14, TFTs 15, etc. The gate bus lines 12 and the data bus lines 13 are intersected perpendicularly with each other, and are isolated electrically by an insulating film (not shown) which is formed between them. The gate bus lines. 12 and the data bus lines 13 are formed of metal such as aluminum, etc.
Rectangular regions which are partitioned by the gate bus lines 12 and the data bus lines 13 act as the picture elements respectively. Transparent picture element electrodes 14 which are formed of indium-tin oxide (abbreviated as an “ITO” hereinafter) are formed on the picture elements respectively. The TFT 15 consists of a gate electrode 12a connected to the gate bus line 12, a silicon film 16 formed over the gate electrode 12a via a gate insulating film (not shown), and a drain electrode 13a and a source electrode 13b formed over the silicon film 16. The drain electrode 13a is connected to the data bus line 13, and the source electrode 13b is connected to the picture element electrodes 14. Also, a storage capacitance electrode (not shown) is formed so as to overlap with a part of the picture element electrodes 14.
An orientation film 17 formed of polyimide, for example, is formed on the picture element electrodes 14. Orientation treatment is applied to a surface of the orientation film 17 to decide the alignment direction of liquid crystal molecules when the voltage is not applied. As the representative method of the orientation treatment, there is known a rubbing method in which a surface of the orientation film is rubbed in one way by a cloth roller.
While, the opposing substrate 20 includes a glass substrate 21, color filters 22 which are formed on a lower surface side of the glass substrate 21, a black matrix 23, opposing electrode 24, an orientation film 25, etc. Three types of the color filters, i.e., red (R), green (G), and blue (B) filters are provided as the color filters 22. The color filter 22 is opposed to the picture element electrodes 14 one by one. In the first embodiment, the color filters 22 are aligned in the order of R, G, B along the horizontal direction. The black matrix 23 is provided between the color filters 22. This black matrix 23 is formed of a metal thin film such as chromium (Cr), which does not transmit the light.
A transparent opposing electrode 24 formed of ITO is formed below the color filters 22 and the black matrix 23. An orientation film 25 is formed below the opposing electrode 24. The orientation treatment is also applied to a surface of the orientation film 25.
Spherical spacers (not shown) are provided between the TFT substrate 10 and the opposing substrate 20, whereby a constant distance between the TFT substrate 10 and the opposing substrate 20 can be maintained. Also, polarizing plates (not shown) are arranged on the TFT substrate 10 and the opposing substrate 20 respectively. These polarizing plates are arranged such that their polarizing axes intersect with each other.
When the data signal is supplied to the data bus lines 13 and the scanning signal is supplied to the gate bus lines 12, the TFTs 15 are turned ON and thus the data signal is supplied to the picture element electrodes 14. Accordingly, an electric field is generated between the picture element electrodes 14 and the opposing electrode 24. The direction of liquid crystal molecules in the liquid crystal 30 is changed by this electric field, so that the light transmittance of the picture element is changed. A desired-image can be displayed on the liquid crystal display panel 40 by controlling the voltage applied to the picture element electrodes 14 picture element by picture element.
The timing controller 31 is connected to a personal computer 37 or other device for outputting the image signals RGB (referred simply to as the “personal computer” hereinafter). A horizontal synchronizing signal H-sync, a vertical synchronizing signal V-sync, a data clock DCLK, and the image signals RGB are input from the personal computer 37 to the timing controller 31.
The image signals RGB are three digital signals (referred to as “RGB signal” hereinafter) consisting of an R signal indicating a red luminance, a G signal indicating a green luminance, and a B signal indicating a blue luminance. Normally, the bit number of the RGB signal is often set to 8 bit respectively. However, for simplicity of explanation, assume that the RGB signal are formed of a 3-bit signal respectively. These RGB signal are signals which are synchronism with the data clock DCLK.
The timing controller 31 receives the horizontal synchronizing signal H-sync, the vertical synchronizing signal V-sync, and the data clock DCLK, and then generates a shift clock SCLK, a data start signal DSTIN, a strobe signal STB, a gate start signal GSTR, and a gate clock GCLK based on these signals.
As shown in
The strobe signal STB is a signal to synchronize with the horizontal synchronizing signal H-sync. The shift clock SCLK is a signal to synchronize with the data clock DCLK.
The polarity pattern controlling portion 32 receives the horizontal synchronizing signal H-sync, the vertical synchronizing signal V-sync and the shift clock SCLK, and then outputs the polarity pattern signal POL. The data driver 33 receives the image signal RGB, the shift clock SCLK, the data start signal DSTIN, and the strobe signal STB from the timing controller 31 and also receives the polarity pattern signal POL from the polarity pattern controlling portion 32, and then outputs data signals O1 to On to the data bus lines 13 for the liquid crystal display panel 40. The polarity of these data signals 01 to On is inverted at a predetermined period.
The gate driver 34 receives the gate start signal GSTR and the gate clock GCLK from timing controller 31, and supplies the scanning signal SCAN to the gate bus lines 11 of the liquid crystal display panel 40 in sequence.
In the case of the driver circuit of the TFT type liquid crystal display panel, the data driver 33 and the gate driver 34 may be formed on the TFT substrate of the liquid crystal display panel 40.
The reference voltage generator circuit 35 generates a reference voltage which is applied to the opposing electrode 24 of the liquid crystal display panel 40. This reference voltage can be set according to a center voltage of the data signals O1 to On and an amount of the voltage shift due to the capacitance component of the picture element. Also, the reference voltage generator circuit 35 generates predetermined voltages necessary for operations of the data driver 33, and the gate driver 34, and then supplies these voltages to respective circuits via wirings (not shown).
In the above example, the case where the driver circuit is connected to the computer 37 is explained. However, also the driver circuit of the liquid crystal display panel of the present invention can be connected to a video signal outputting device such as a TV tuner, etc. In this case, respective circuits for generating the RGB signal, the horizontal synchronizing signal H-sync, and the vertical synchronizing signal V-sync from the video signal are required, but well-known circuits may be employed as these circuits.
The polarity pattern controlling portion 32 comprises a control circuit 32a, and a ROM 32b for storing polarity patterns.
The polarity pattern stored in the ROM 32b is composed of a combination of “0” and “1”. For example, “0” means that the voltage with the positive polarity (+) is applied to the picture element electrodes 14, and “1” means that the voltage with the negative polarity (−) is applied to the picture element electrodes 14. In the first embodiment, the polarity of the data signals O1 to On which are supplied to the liquid crystal display panel 40 is inverted frame by frame. Therefore, the polarity patterns which are output to the odd-numbered frame and the polarity patterns which are output to the even-numbered frame must have just opposite combinations of “0” and “1” respectively. The ROM 32b stores the polarity patterns of two frames, i.e., the polarity patterns having the bit number which is twice the picture element number of the liquid crystal display panel 40 as a set of data.
The control circuit 32a receives the horizontal synchronizing signal H-sync, the vertical synchronizing signal V-sync, and the shift clock SCLK to set addresses of the ROM 32b. In other words, the control circuit 32a sets an initial value of the address of the ROM 32b in synchronism with a leading edge of the odd-numbered vertical synchronizing signal V-sync, and then increments the address in synchronism with the shift clock SCLK. Therefore, the polarity pattern signal POL is output from the ROM 32b bit by bit in synchronism with the shift clock SCLK. In this case, the control circuit 32a stops its operation once when it increments the address of the ROM 32b during one period of the horizontal synchronizing signal H-sync by the same number as the picture element number (n) of the display panel 40 in the horizontal direction, and then starts to increments the address at the leading edge of the horizontal synchronizing signal H-sync again.
The data driver 33 comprises shift register circuit portions 41, 42, a data register circuit portion 43, a latch circuit portion 44, a level shift circuit portion 45, a D/A converter circuit portion 46, and a voltage follower portion 47.
The shift register circuit portion 41 starts to read the polarity pattern signal POL from the polarity pattern controlling portion 32 in synchronism with the horizontal synchronizing signal H-sync. Then, the shift register circuit portion 41 shifts the polarity pattern signal POL in synchronism with the shift clock SCLK, and then outputs the n-bit polarity pattern signal POL in parallel. The signals which are output from the shift register circuit 41 in parallel are referred to as the polarity signals P1 to Pn hereinafter.
The data register circuit portion 43 consists of n registers 43a. The shift register circuit portion 42 receives the data start signal DSTIN, the data clock DCLK, and the strobe signal STB to then set the address of the register 43a of the data register circuit portion 43. That is to say, the data register circuit portion 43, when receives the data start signal DSTIN, sets a head address of the register 43a and increments the address in synchronism with the data clock DCLK. The data register circuit portion 43 receives the image signal RGB, and then holds the R signal, the G signal, or the B signal in the register 43a having the address which is designated by the shift register circuit portion 42.
The latch circuit portion 44 consists of n latch circuits 44a. Respective latch circuits 44a latch outputs of the data register circuit portion 43 and outputs of the shift register circuit portion 41 in synchronism with the strobe signal STB. At this time, respective latch circuits 44a adds the polarity signal P1 to Pn to the most significant bit of the 3-bit R signal, the 3-bit G signal, or the 3-bit B signal to form 4-bit signals.
The level shift circuit portion 45 converts a level of the signal which is output from the latch circuit portion 44. In the first embodiment, the level shift circuit portion 45 converts the signal, which is output from the latch circuit portion 44 and whose peak value is 3.3 V, into a signal whose peak value is 12 V, and then outputs such signal to the D/A converter circuit portion 46.
The D/A converter circuit portion 46 consists of n D/A converters 46a. These D/A converters 46a receive the 4-bit R signal, the 4-bit G signal, and the 4-bit B signal, to which the polarity signal P1 to Pn are added, and then outputs analogue data signals O1 to On with the positive polarity (+) or the negative polarity (−). The voltage follower portion 47 consists of n voltage followers 47a. These voltage followers 47a supplies the data signals O1 to On, which are output from the D/A converter circuit portion 46, to the data bus lines 13 of the liquid crystal display panel 40 in synchronism with the strobe signal STB.
The D/A converter 46a consists of a decoder 51, 17 resistor elements 52, 16 voltage followers 53, and 16 switching elements 54. The resistor elements 52 are connected in series between the high potential power supply line (+12 V) and the low potential power supply line (+0 V). Inputs of the voltage followers 53 are connected to connecting points (nodes) of the resistor elements 52 respectively. Outputs of the voltage followers 53 are connected to one ends of the switching elements 54 respectively. All other ends of the switching elements 54 are connected to an output terminal 55.
The switching element 54 is turned ON when “1” is supplied from the decoder 51, and is turned OFF when “1” is supplied from the decoder 51. The decoder 51 receives the 4-bit signals in which 1-bit polarity signal P is added to the 3-bit R signal, the 3-bit G signal, or the 3-bit B signal, and then outputs a 16-bit signal.
The data signal has the positive polarity (+) if the voltage of the signal (data signals O1 to On) being output from the output terminal 55 is higher than the reference voltage (V1 to V7), while the data signal has the negative polarity (−) if the voltage of the signal being output from the output terminal 55 is lower than the reference voltage (−V1 to −V7). In other words, the data signals O1 to On being output from the voltage follower portion 47 have the positive polarity if the most significant bit (polarity signal) being input into the decoder 51 is “0”, while the data signals O1 to On have the positive polarity if the most significant bit being input into the decoder 51 is “1”.
In
In
In
In
In three types of the polarity patterns (
In the first embodiment, such a polarity pattern that generation of the flicker can be suppressed extremely small in the usually employed display pattern is employed as the polarity pattern. For example, as shown in
An operation of the liquid crystal display panel driver circuit according to the first embodiment will be explained hereinbelow.
As shown in
The control circuit 32a of the polarity pattern controlling portion 32 shown in
In the first embodiment, the polarity of the picture element electrodes is inverted frame by frame. Thus, the ROM 32b stores the polarity patterns by the two-frame bit number, and “1” and “0” combinations of the polarity patterns in the odd-numbered frame are exactly opposite to those of the polarity patterns in the even-numbered frame. Then, the control circuit 32a returns the read address of the ROM 32b to the head address every two vertical synchronization periods. Also, the polarity pattern signal POL for one frame may be stored in the ROM 32b and then the output of the ROM 32b may be inverted frame by frame. In this case, a switch for switching the output destination of the ROM 32b every vertical synchronization period and an inverter for inverting the output signal of the ROM 32b are needed.
The shift register circuit portion 41 of the data driver 33 shown in
Meanwhile, the shift register circuit portion 42 receives the data start signal DSTIN, the data clock DCLK, and the strobe signal STB from the timing controller 31, and then starts the address setting of the data register circuit portion 43. That is to say, when the data start signal DSTIN is changed from “0” to “1”, the shift register circuit portion 42 sets the initial address of the data register circuit portion 43, and then increments the address in synchronism with the data clock DCLK. Accordingly, the R signal, the G signal, or the B signal are held in sequence into the registers 43a of the data register circuit portion 43. More particularly, the first R signal (D1), the first G signal (D2), the first B signal (D3) are held into the first to third registers 43a of the data register circuit portion 43 in response to the first data clock DCLK. Then, the second R signal (D4), the second G signal (D5), the second B signal (D6) are held into the fourth to sixth registers 43a of the data register circuit portion 43 in response to the second data clock DCLK. In this manner, the R signal, the G signal, and the B signal for one horizontal synchronization period are held in the data register circuit portion 43.
Respective latch circuits 44a of the latch circuit portion 44 generate the 4-bit data by adding the 1-bit polarity signal P1 to Pn being output from the shift register circuit portion 41 to the 3-bit R, G, B signals being output from the data register circuit portion 43, and then output them to the level shift circuit portion 45 in synchronism with the strobe signal STB. The level shift circuit portion 45 converts a level of the signal which is output from the latch circuit portion 44. In the first embodiment, the level shift circuit portion 45 converts the voltage level of these 4-bit signals to output them.
The D/A converter circuit portion 46 D/A-converts i the 4-bit signals being output from the level shift circuit portion 45, and then outputs the analogue data signals O1 to On. In this case, according to
Meanwhile, when receives the gate start signal GSTR from the timing controller 31, the gate driver 34 supplies the scanning signal SCAN sequentially to the uppermost gate bus line 12 to the lowermost gate bus line 12 one by one in synchronism with the gate clock GCLK. As a result, the TFT 15 connected to the gate bus line 12 to which the scanning signal SCAN is supplied is turned ON, and therefore the data signals O1 to On being output from the data driver 33 are supplied to the picture element electrodes 14. Thus, the electric field is generated between the picture element electrodes 14 and the opposing electrode 24. Since the alignment of the liquid crystal molecules is changed by the electric field, the optical transmittance of the picture elements can be changed in response to the applied voltage. In this case, the polarity of the signal applied to the picture element electrodes 14 is decided according to the polarity pattern stored in the ROM 32b, and the polarity is inverted every frame.
In the first embodiment, since the polarity of the signal being supplied to the picture element electrodes is decided according to the polarity pattern stored in the ROM 32b, the polarity patterns in which the flicker is hard to occur can be generated by the simple circuit configuration without the complicated process of the image signals, etc. For example, if the present invention is applied to the liquid crystal display panel driver circuit for the computer, the flicker can be reduced extremely in normal use by setting the polarity patterns, as shown in
As shown in
A plurality of picture elements (see
The input controlling portion 555 receives signals such as image signals, synchronizing signals, operating clocks, etc. from the personal computer 504, and then outputs the predetermined signals to the data driver 502 and the gate driver 503. The input controlling portion 555 always monitors the correlation between the change period of the display pattern and the polarity inverting period of the reference voltage. Then, if the synchronization between them is detected and also the polarity inverting period is decided as the particular display patterns which are previously set, the input controlling portion 555 outputs the polarity inverting period, which is different from the polarity inverting period of the original period, to a reference voltage generating portion 556, and then supplies the reference voltage to the data driver 502 at any inverting period.
As shown in
The input data extracting portion 512a is provided in the input data latch circuit 512. The input data extracting portion 512a extracts sequentially the image signals, which are supplied to two adjacent picture elements, from the continuous image signals to output them as the extracted signal.
The display pattern detecting portion 514a counts mutual change between two extracted image signals (extracted signals), e.g., an amount of change from white to black and the number of times of the change, and then detects the particular display pattern. Where the wording “particular display pattern” means the pattern which increases the flicker in display or the increase in the power consumption during the polarity inverting period of the reference voltage in the initial state. Such particular display patterns are patterns which are a checker pattern, a pattern in which horizontal lines are displayed on the green background, etc.
In case the particular display pattern is detected based on the detection result of the display pattern detecting portion 514a, the inverting period circuit group 514b and the switching group 514c can switch the polarity inverting signal (polarity inverting period) which is to be output to the reference voltage generating portion 556. For example, as shown in
Then, the reference voltage generating potion 556 supplies the polarity inverting signal to the data driver 502, based on the inverted period which is provided by the inverting period circuit B.
As the configuration of the inverting period controlling means, there is shown such a configuration that controls to switch two pairs of switches SW11, SW21 and SW12, SW22 to select one of a plurality of inverting period circuits A, B based on the detection result of the display pattern detecting portion 514a. However, the inverting period controlling means is not limited to the above if it can vary freely the polarity inverting period for the reference voltage generating portion 556 and then output it.
Next, an inverting period controlling operation of the above timing control circuit will be explained with reference to a flowchart shown in
In the timing control circuit shown in
First, the input data extracting portion 512a always monitors the image signals which are input into the input data latch circuit 512 via the input I/F portion 511 and held there, then extracts the image signals which are to be supplied to two adjacent picture elements every R, G, B data (step S1).
Then, the display pattern detecting portion 514a counts an amount of change in the image data extracted by the input data extracting portion 512a and the number of times of change, then detects display patterns which causes the conspicuous flicker of the display screen or the increase in the power consumption during the polarity inverting period of the inverting period circuit A which is set as the initial state, and then detects the particular display pattern (step S2).
Then, if the particular display pattern is detected, the switches SW 11, SW 12 are turned OFF and also switches SW21, SW 22 are turned ON so as to select other inverting period circuit B which has the different inverting period from that of the currently selected inverting period circuit A (step S3).
Then, the polarity inverting period being provided by the newly selected inverting period circuit B is output as the polarity inverting signal to the reference voltage generating portion 556, and then the reference voltage is generated to have the polarity inverting period different from that in the initial state (step S4). Then, the reference voltage is supplied to the data driver 502 (step S5).
In contrast, if the image data being extracted by the input data extracting portion 512a are not decided as the particular display pattern being set in the display pattern detecting portion 514a, or if the display pattern which causes the conspicuous flicker on the display screen or the increase in the power consumption relative to the polarity inverting period which is provided by the switched inverting period circuit B is detected, the switch group 514c is controlled to be switched to the inverting period circuit A which has been selected in the initial state.
According to such inverting period switching method, when the image data having the display pattern, in which only the picture elements with either the positive polarity or the negative polarity out of the picture elements of the liquid crystal display panel are brought into their ON state, are input, the polarity inverting period of the reference voltage which is applied to the picture elements can be varied. Therefore, the alignment of the positive polarity picture elements and the negative polarity picture elements can be varied. Here, preferably, it should be provided by the varied alignment of the picture elements that half the number of overall picture elements are in their ON states even in the same display pattern.
More particularly, as shown in
Under such condition, as shown in
As described above, the patterns being displayed on the display screen are always monitored by the input data extracting portion 512a and the display pattern detecting portion 514a. Then, if the display pattern to cause the conspicuous flicker is detected, the switch group 514c is controlled to switch the inverting period circuit group 514b based on the detection result supplied from the display pattern detecting portion 514a.
For this reason, the other inverting period circuit B can be selected and then, for example, the period at which the polarity inversion is performed in unit of the horizontal line at random, as shown in
Accordingly, if a series of image data having the display patterns which cause the flicker on the display screen and the increase in the power consumption are input, the polarity inverting period of the reference voltage being applied to the picture elements can be switched immediately. Therefore, improvement of the display quality and reduction in the power consumption can be achieved.
As shown in
Where, as shown in
In this manner, with the use of the predetermined logic outputs which receive the input data and the output data of the flip-flops FRb, FGb, FBb of the input data latch circuit 512, the mutual change states between the continuously neighboring image data can always be extracted every R, G, B data.
Also, as shown in
Next, an example of the display pattern detecting portion 514a which is applied to the liquid crystal display device of the present invention will be explained with reference to
An shown in
In this case, any inverting period circuits may be employed if they can output the predetermined polarity inverting signal to the reference voltage generating portion 556 located at the succeeding stage and also, for example, the inverting period circuit A can be selected in the initial state and then such inverting period circuit A is switched into another inverting period circuit B or C if the particular display pattern which causes the flicker on the display screen is detected. As shown in.
Also, as shown in
In this way, the particular display patterns can be monitored/discriminated by extracting the continuously adjacent image data with the use of the input data extracting portion 512a and the display pattern detecting portion 514a, then counting an amount of change in the image data and the number of times of the change, and then comparing them with predetermined specified values. Thus, the synchronization between the period of the display pattern which is displayed on the liquid crystal display panel 501 and the polarity inverting period of the reference voltage which is applied to the picture elements can be avoided, and also the flicker on the screen and the increase in the power consumption can be suppressed.
In addition, according to such drive controlling method, even when the inverting system is employed in unit of one dot, two dots, horizontal line, or vertical line, for example, as the polarity inverting system of the reference voltage applied to the picture elements, the period of the polarity inversion can be set appropriately so as to avoid the synchronization state between the period of the polarity inversion and the period of the display pattern.
A liquid crystal display panel driver circuit according to a third embodiment of the present invention will be explained hereunder. A different respect between the third embodiment and the first embodiment resides in that a configuration of the polarity pattern controlling portion is different from each other. Since remaining configurations are similar to those in the first embodiment, redundant explanations of the overlapping constituting portions will be omitted.
Two sets of polarity patterns are stored in the ROM 62. Respective polarity patterns have two-frame bit numbers, and are set such that the polarity is inverted frame by frame. The control circuit 61 selects one set out of two sets of polarity patterns, then sets the initial address of the ROM 62, and then increments the address of the ROM 62 in synchronism with the shift clock SCLK. Therefore, a set of the polarity patterns are read from the ROM 62 bit by bit, and then output as the polarity pattern signal POL.
The comparator 63 compares the polarity pattern signal POL being read out from the ROM 62 with the image signal RGB being output from the timing controller 31. Then, for example, the comparator 63 outputs “1” in synchronism with the shift clock SCLK if the most significant bit of the image signal RGB coincides with the polarity pattern signal POL, whereas the comparator 63 outputs “0” in synchronism with the shift clock SCLK if the most significant bit of the image signal RGB does not coincide with the polarity pattern signal POL. The counter circuit 64 monitors the output of the comparator 63 to count the number of times of the output “1” of the comparator 63 for a unit time or every predetermined data number (unit data number). The comparator 65 outputs a selection signal SEL of “1” if a counted value being output from the counter circuit 64 exceeds a value set by the threshold setting portion 66, while the comparator 65 outputs the selection signal SEL of “0” if the counted value does not exceed the value set by the threshold setting portion 66.
The control circuit 61 continues to read the polarity pattern which is now being read out when the selection signal SEL is “0”, while the control circuit 61 starts to read other patterns by adding an offset to the address of the ROM 62 when the selection signal SEL is “1”.
The polarity pattern in which the polarity is different every two bits, as shown in
In the third embodiment, as described above, two sets of polarity patterns are stored in the ROM 62, and then it is decided by the comparator 63, the counter circuit 64, the comparator 65, and the threshold setting portion 66 whether or not the polarity pattern signal POL output from the ROM 62 is similar to the image signal RGB. Then, if it is decided that both signals are similar to each other, there is such a possibility that the flicker is generated, so that the polarity pattern which is read from the ROM 62 can be changed. Therefore, the polarity pattern can be switched automatically in response to the display image, and thus generation of the flicker can be prevented without fail. In addition, in the third embodiment, the liquid crystal display device which is able to switch the polarity pattern by the simple circuit configuration in response to the image signal can be achieved.
A liquid crystal display panel driver circuit according to a fourth embodiment of the present invention will be explained hereunder. A different respect between the fourth embodiment and the first embodiment resides in that configurations of the polarity pattern controlling portion and the data driver are different from each other. Since remaining configurations are similar to those in the first embodiment, redundant explanations of the overlapped constituent portions will be omitted.
The polarity pattern controlling portion 70 comprises a control circuit 71, a ROM 72, D-type flip-flop circuits 73, 74, and an exclusive-OR (XOR) circuit 75. The polarity patterns in which data corresponding to the horizontal picture element number (n) of the liquid crystal display panel 40 are compiled as a set are stored in the ROM 72.
The control circuit 71 receives the horizontal synchronizing signal H-sync, the vertical synchronizing signal V-sync, and the shift clock SCLK, sets the address of the ROM 72, and generates the loading signal LOAD which takes a value “1” only for the first horizontal synchronization period after the power supply has been turned ON and then takes a value “0” thereafter. The polarity pattern signal POL1 is output from the ROM 72 bit by bit in synchronism with the shift clock SCLK.
The D-type flip-flop circuit 73 receives the horizontal synchronizing signal H-sync at its clock terminal CLK, and feeds back an output of its inverted output terminal /Q (Where “/” denotes an inverting signal. This is also true hereinafter.) to its input terminal D. Also, the vertical synchronizing signal V-sync is input into a clock terminal CLK of the D-type flip-flop circuit 74. An output of an inverted output terminal /Q of the D-type flip-flop circuit 74 is fed back to an input terminal D. Signals being output from the inverted output terminals /Q of the D-type flip-flop circuits 73, 74 are input into the XOR circuit 75. Then, the XOR circuit 75 outputs the exclusive-OR of two input signals as an inverting signal POL2.
The inverting signal POL2 output from the XOR circuit 75 is inverted every one period of the horizontal synchronizing signal H-sync and also inverted every one period of the vertical synchronizing signal V-sync.
An AND circuit 76 transmits the shift clock SCLK to a shift register circuit portion 77 only in a period when the loading signal LOAD is “1”.
The shift register circuit portion 77 shifts the polarity pattern signal POL1 which is input from the polarity pattern controlling portion 70 in synchronism with the-shift clock SCLK, and then outputs the polarity pattern signal POL1 for one horizontal synchronization period in parallel. The signals which are output parallelly from the shift register circuit portion 77 are referred to as polarity signals A1 to An hereinafter.
An exclusive-OR circuit portion 78 consists of n exclusive-OR circuits 78a. The exclusive-OR circuits 78a output the exclusive OR of the polarity signals A1 to An and the inverting signal POL2 as the polarity signals P1 to Pn. In other words, the exclusive-OR circuits 78a outputs the polarity signals A1 to An, which are output from the shift register circuit portion 77, as the polarity signals P1 to Pn when the inverting signal POL2 is “1”, while the exclusive-OR circuits 78a outputs the inverted signals of the polarity signals A1 to An as the polarity signals P1 to Pn when the inverting signal POL2 is “0”.
An operation of the liquid crystal display panel driver circuit according to the fourth embodiment will be explained hereunder.
The control circuit 71 of the polarity pattern controlling portion 70 sets the loading signal LOAD to “1” in synchronism with the leading edge of the first horizontal synchronizing signal H-sync after the power supply has been turned ON. Also, the control circuit 71 sets the-initial address of the ROM 72 in synchronism with the horizontal synchronizing signal H-sync, and then increments the address in synchronism with the shift clock SCLK. Accordingly, the polarity pattern signal POL1 is output from the ROM 72 bit by bit in synchronism with the shift clock SCLK.
The XOR circuit 75 outputs the inverting signal POL2 which is inverted every one horizontal synchronization period and every one vertical synchronization period.
The AND circuit 76 of the data driver 79 shown in
As shown in
Meanwhile, the inverting signal POL2 output from the XOR circuit 75 is inverted every one horizontal synchronization period. Hence, as shown in
In addition, the inverting signal POL2 output from the XOR circuit 75 is inverted every one vertical synchronization period. As a result, the polarity of the picture element electrodes is inverted frame by frame.
In the fourth embodiment, since only the polarity pattern for one horizontal synchronization period should be stored in the ROM 72, an amount of memory cell of the ROM 72 can be reduced smaller than the ROM 62.
Also, in the fourth embodiment, like the third embodiment, plural sets of polarity patterns may be stored previously in the ROM 72, then the similarity between the data signal TADA and the polarity pattern signal POL1 may be estimated by comparing them by using the comparator, and then the polarity pattern signal read out from the ROM 72 may be switched if there is such a possibility that the flicker is generated.
A liquid crystal display panel driver circuit according to a fifth embodiment of the present invention will be explained hereinafter. A difference of the fifth embodiment from the first embodiment resides in that configurations of the polarity pattern controlling portion and the data driver are different. Since other configurations are similar to those of the first embodiment, redundant explanations of overlapped constituent portions will be omitted.
The polarity pattern controlling portion 80 comprises D-type flip-flops circuits 81, 82, an exclusive-OR circuit 83, and a change-over switch 84. The D-type flip-flops circuit 81 receives the horizontal synchronizing signal H-sync at its clock terminal CLK, and an output of the inverted output terminal /Q is fed back to an input terminal D. Also, the vertical synchronizing signal V-sync is input into the clock terminal CLK of the D-type flip-flops circuit 82. An output of the inverted output terminal /Q of the D-type flip-flops circuit 82 is fed back to an input terminal D. Signals being output from the inverted output terminals /Q of the D-type flip-flops circuits 81, 82 are input into the exclusive-OR circuit 83. This exclusive-OR circuit 83 outputs the exclusive-OR of two input signals as the inverting signal POL2. This inverting signal POL2 output from the exclusive-OR circuit 83 is inverted every one period of the horizontal synchronizing signal H-sync and every one period of the vertical synchronizing signal V-sync. The change-over switch 84 is connected to any one of the high potential side wiring and the low potential side wiring, and outputs “1”, or “0”.
The data driver 89 includes n logic circuits 85, and an exclusive-OR circuit portion 86. As shown in
In the fifth embodiment, as shown in
The exclusive-OR circuit portion,86 consists of n exclusive-OR circuits 86a. The inverting signal POL2 is input into one input terminal of each exclusive-OR circuit 86a, while the other input terminal of each exclusive-OR circuit 86a is connected to an output terminal Q of the logic circuit 85.
For example, the selection signal SEL is set to “0” by switching the change-over switch 84. Then, the inverted signals shown in
In the fifth embodiment, the polarity pattern can be changed by the selection signal SEL. In addition, in the fifth embodiment, unlike the first to third embodiments, the ROM for storing the polarity pattern can be omitted.
In the sixth embodiment, such an operation can be achieved that, as shown in
The liquid crystal display panel driver circuit according to the sixth embodiment comprises a timing controller 101, a drive mode detecting portion 102, a data driver 109, a gate driver (not shown), and a reference voltage generation circuit (not shown). Then, the drive mode detecting portion 102 includes a display data converting portion 103, a flicker detecting portion 104, a dynamic range designating portion 105, a flicker information storing portion 106, a flicker information amount detecting portion 107, and a drive mode selecting portion 108. Because configurations of the timing controller 101, the gate driver, and the reference voltage generation circuit are basically similar to those in the first embodiment, their explanation will be omitted herein. Also, assume that the R, G, B signals being output from the timing controller 101 are composed of a 6-bit signal respectively in the following explanation.
As shown in
More particularly, upper 4-bits (R02 to R05) of the R signal of the odd-numbered picture elements are input into the OR gate 111a. Then, an output signal DRO is set to “1” if at least one bit of these bits R02 to R05 is “1”, while the output signal DRO is set to “0” if all the bits R02 to R05 are “0”. The signal DRO of “1” indicates that the picture element is turned ON, and the signal DRO of “0” indicates that the picture element is not turned ON. Operations of the OR gates 111b, 111c are similar to the above operation of the OR gate 111a. That is, upper 4-bits G02 to G05, B02 to B05 of the G signal, the B signal of the odd-numbered picture elements are input into the OR gates 111b, 111c respectively. Then, output signals DGO, DBO are set to “1” respectively if at least one bit of these four bits is “1”, while the output signals DGO, DBO are set to “0” respectively if all four input bits are “0”.
Similarly, upper 4-bits of the R, G, B data of the even-numbered picture elements are input into the OR gates 111d, 111e, 111f respectively. Then, output signals DRE, DGE, DBE are set to “1” respectively if at-least one bits of these four input bits (RE2 to RE5, GE2 to GE5, BE2 to BE5) are “1” respectively, while the output signals DRE, DGE, DBE are set to “0” respectively if all four input bits are “0”.
As shown in
More particularly, the adder 112a receives the signals DRO, DBO, DGE which are output from the display data converting portion 103, and then outputs added signals (2-bit signals) of these signals. Also, the adder 112b receives the signals DGO, DRE, DBE which are output from the display data converting portion 103, and then outputs added signals (2-bit signals) of these signals. A NOR gate 113a outputs “0” if at least one bit of the 2-bit signals output from the adder 112a is “1”, and outputs “1” if all bits of the 2-bit signals are “0”. An OR gate 113b outputs “1” if at least one of the 2-bit signals output from the adder 112bis “1”, and outputs “0” if all bits of the 2-bit signals are “0”. An AND gate 114a sets an output signal FLDEL to “1” if both outputs of the NOR gate 113a and the OR gate 113b are “1”, and sets an output signal FLDEL to “0” if at least one output of the NOR gate 113a and the OR gate 113b is “0”. If the output signal FLDEL of the AND gate 114a is “1”, the data arrangement shows the even-number flicker pattern, as shown in
The adder 112c receives the signals DRO, DBO, DGE which are output from the display data converting portion 103, and then outputs added signals (2-bit signals) of these signals. Also, the adder 112d receives the signals DGO, DRE, DBE which are output from the display data converting portion 103, and then outputs added signals (2-bit signals) of these signals. An OR gate 113c outputs “1” if at least one of the 2-bit signals output from the adder 112c is “1”, and outputs “0” if all bits of the 2-bit signals are “0”. A NOR gate 113d outputs “0” if at least one bit of the 2-bit signals output from the adder 112d is “1”, and outputs “1” if all bits of the 2-bit signals are “0”. An AND gate 114b sets an output signal FLDOL to “1” if both outputs of the OR gate 113c and the NOR gate 113d are “1”, and sets an output signal FLDOL to “0” if at least one output of the OR gate 113c and the NOR gate 113d is “0”. If the output signal FLDOL of the AND gate 114b is “1”, the data arrangement shows the odd-number flicker pattern, as shown in
As shown in
The counter 115 counts the pulse of the horizontal synchronizing signal H-sync, and is cleared by the vertical synchronizing signal V-sync. Then, when a counted value reaches 128, 256, 384, 512, 640, or 768, the counter 115 sets a corresponding one of output signals 128L, 256L, . . . , 768L to “H”. When any one of the output signals 128L, 256L, . . . , 768L of the counter 115 is set to “H”, the OR gate 116 sets an output signal CONTCLR to “H”. Accordingly, the signal CONTCLR which is set to “H” every 128 lines can be output.
The counter 117 is cleared by the horizontal synchronizing signal H-sync, and then counts the data clock DCLK. Then, when the counted value is 0 (i.e., the counter 117 is cleared), or when the 64-th, 128-th, 192-th, 320-th, 384-th, 448-th, or 512-th data clock DCLK is counted, a corresponding one of output signals 0D, 64D, . . . , 512D is set to “H”.
The RS latch circuit 118a is set by the output signal OD of the counter 117, and is reset by the signal 64D. An output signal 1/8H becomes “H” during when the RS latch circuit 118a is set. The RS latch circuit 118b is set by the output signal 64D of the counter 117, and is reset by the signal 128D. An output signal 2/8H becomes “H” during when the RS latch circuit 118b is set. Operations of other RS latch circuits 118c to 118h are similar to the above operation.
The selector 119 selects any one of the output signals output from the RS latch circuits 118a to 118h in sequence every time when the vertical synchronizing signal V-sync is input into the selector 119, and then outputs the signal DE which defines the dynamic range. In this manner, the signal DE which is set to “H” in a period when the predetermined block is being selected is output from the selector 119.
As shown in
More particularly, the AND 120 receives the data clock DCLK, and then output the clock PCLK only in a period when the signal for defining the dynamic range is “H”. The 64-stage shift register 121a receives the even-numbered flicker pattern signal FLDEL, which is output from the flicker detecting portion 104, at timings in synchronism with the clock PCLK, and then shifts the signal FLDEL sequentially. Then, a value of the final stage register is output as the signal FLDEF. Similarly, the 64-stage shift register 121b receives the odd-numbered flicker pattern signal FLDOL, which is output from the flicker detecting portion 104, at timings in synchronism with the clock PCLK, and then shifts the signal FLDOL sequentially. Then, a value of the final stage register is output as the signal FLDOF.
The AND gate 122a outputs “H” when both the even-numbered flicker pattern signal FLDEL and the output signal FLDEL of the 64-stage shift register 121a are “H”. Similarly, the AND gate 122b outputs “H” when both the odd-numbered flicker pattern signal FLDOL and the output signal FLDOL of the 64-stage shift register 121b are “H”. The OR gate 123 sets an output signal FLSED to “H” when at least one of the output signals of the AND gate 122a and the AND gate 122b is “H”. In other words, the flicker information storing portion 106 sets the output signal FLSED to “H” when the picture elements being aligned in the vertical direction show the flicker pattern.
As shown in
More particularly, the counter 124 is cleared when the-output signal CONTCLR of the OR gate 116 of the dynamic range designating portion 105 becomes “H”. The counter 124 fetches a value of the output signal FLSED of the OR gate 123 of the flicker information storing portion 106 at timings which are in synchronism with the clock PCLK being output from the AND gate 120 of the flicker information storing portion 106, and then increments the counted number. Then, if the counted value is in excess of 6144, the output of the counter 124 becomes “H”. When the counter 124 exceeds its dynamic range in the vertical direction, it is cleared by the output CNTCLR of the OR gate 116 of the dynamic range designating portion 105. The RS latch 125 is set by the output of the counter 124, and is reset by the vertical synchronizing signal V-sync. It is shown that, when the output signal FLJD of the RS latch 125 is “H”, 6144 flicker patterns are present in the dynamic range (64×3×128 picture elements).
As shown in
More particularly, the AND gate 126 receives the inverted signal of the output FLJD of the RS latch 125 of the dynamic range designating portion 105 and a signal FRM. The signal FRM is a signal which is in synchronism with the vertical synchronizing signal V-sync, and has a pulse which becomes “H” in an image data blank period prior to the pulse of the vertical synchronizing signal V-sync. The AND gate 126 outputs the signal GCLK which becomes “H” when the output signal FLJD of the RS latch circuit 125 is “L” and the signal FRM is “H”.
The counter 127 counts the output signal GCLK of the AND gate 126, and then sets the output signal FLRST to “H” to clear the value of the counter when the counted value reach a predetermined value. In other words, the counter 127 counts the flickerless frames, and then sets the output signal FLRST to “H” when the flickerless frames are continued over a predetermined period (e.g., 15 to 30 frame period).
The RS latch-circuit 128 is set when the output signal FLJD of the RS latch circuit 125 in
The polarity pattern selecting portion 191 changes the polarity of the polarity signals P1, P2, . . . , Pn every one horizontal synchronization period in a time period when the output signal FMODE of the latch circuit 128 is “L”, and also changes the polarity of the polarity signals P1, P2, . . . , Pn every two horizontal synchronization periods in a time period when the output signal FLPT of the latch circuit 128 is “H”. The polarity of the data signals O1 to On which are output from the data driver according to the polarity signals P1, P2, . . . , Pn (see
In the sixth embodiment, since the polarity pattern can be automatically changed from the first polarity pattern to the second polarity pattern by detecting the presence of the flicker pattern by the circuit consisting of the logic circuits when the flicker becomes conspicuous, the event that it becomes hard to watch the screen due to the flicker can be prevented. Also, in the sixth embodiment, since the drive mode detecting portion 102 is formed only by the logic circuit and no ROM is incorporated, such an advantage can be achieved that a production cost can be reduced.
In the above sixth embodiment, the case is explained where the screen is partitioned into a plurality of blocks and then the polarity pattern is changed when the flicker pattern is detected from at least one block by the predetermined number or more. In this case, if a rate of the blocks, in which the flicker pattern is detected to exceed a preselected number (e.g., 25%), to all block number is detected and then such rate of the blocks exceeds a previously set value (e.g., 20% of all block number), the polarity pattern may be changed.
In addition, in order to detect generation of the flicker on the boundary between the partitioned blocks, for example, the block range may be shifted in the vertical direction or the horizontal direction by half of the block every frame. In this case, an offset value may be set in the counters 115, 117 in the dynamic range designating portion 105 every one frame.
A seventh embodiment of the present invention will be explained hereunder. In the seventh embodiment, the flicker patterns are set in more detail rather than the sixth embodiment.
The flicker is generated when the polarity of turn-ON picture elements is deviated every R, G, B. Therefore, as for one color of R, G, B of two picture elements which are adjacent in the horizontal direction, the pattern in which one picture element is turned ON and the other picture element is not turned ON (turned off) is counted and then such pattern is assumed as the flicker pattern if the number of counted patterns exceed a predetermined value.
In the meanwhile, an amount of light transmitted through the picture elements of the liquid crystal display panel is associated with a product of a transmitted amount of light and a corrected value of a color filter. The corrected value of the R, G, B color filters are not uniform, and are set to 20%, 70%, 10% respectively. Consequently, if only one of G picture elements in two pixels being aligned in the horizontal direction is turned ON and the other is not turned ON, the flicker becomes conspicuous. Therefore, in the seventh embodiment, in case merely the G picture element in one pixel of two pixels being aligned in the horizontal direction is turned ON and the G picture element in the other pixel is not turned ON, such pattern is deemed as the flicker pattern, regardless of the situation that the R picture element and the B picture element are turned ON or not.
According to the above method, since the flicker pattern is detected only in the horizontal direction, the patterns in which no flicker is generated, such as the vertical-striped pattern, as shown in
In addition, special patterns such as a checker pattern in which two picture elements are displayed in the vertical direction, as shown in
Because the flicker is generated due to difference between the-luminance of the positive polarity and the luminance of the negative polarity, it is hard to recognize the flicker in the low luminance area. Further, because change in the transmittance relative to the applied voltage is small, it is also hard to recognize the flicker in the high luminance area. Moreover, an appearance of the flicker is changed depending upon the luminance of the backlight. Therefore, the turning ON or OFF of the picture elements may be set appropriately according to the above conditions.
In order to except the pattern shown in
The optimum detection of the flicker pattern to mate with the polarity pattern can be attained by employing appropriately the above flicker pattern detecting method and the exception pattern detecting method in combination. For example, if the polarity pattern is the dot inversion pattern shown in
Further, when the polarity pattern corresponds to a vertical line inverted polarity pattern shown in
Furthermore, when the polarity pattern corresponds to a horizontal line inverted polarity pattern shown in
The AND gate 143 outputs the “H” signal when both the signal DE which is output from the dynamic range designating portion 105 to define the dynamic range and the signal GFP which is output from the XOR gate 141 are “H”, and outputs the “L” signal when the signal DE and the signal GFP take other conditions. The counter 144 counts an output of the AND gate 143 at timings in synchronism with the clock DCLK. Then, the counter 144 outputs the “H” signal when the counted value comes up to 2048 (¼ of the G picture element in the block). The counter 144 is cleared by the signal DCNTCLR which is output from the D-type flip-flop 142. The RS latch circuit 145 is set by the output of the counter 144 and is reset by the signal DCNTCLR.
The circuits shown in
In circuits shown in
In shift registers 149 to 152, the output signal GOCNT of the RS latch 148 is input into a first-stage shift register 149 which shifts the data according to the signal LP. In this case, the signal LP is a signal which becomes “H” after the valid data range of the horizontal synchronizing signal H-sync. An AND gate 153 receives outputs of the shift registers 149, 150 and inverted outputs of the shift registers 151, 152, and then outputs a signal G02DOT which becomes “H” when all outputs are “H”. An AND gate 154 receives the outputs of the shift registers 149, 150, and then outputs a signal GOT which becomes “H” when both outputs are “H”.
In circuits shown in
In shift registers 159 to 162, the output signal GECNT of the RS latch 158 is input into a first-stage shift register 159 which shifts the data according to the signal LP. An AND gate 163 receives outputs of the shift registers 159, 160 and inverted outputs of the shift registers 161, 162, and then outputs a signal GE2DOT which becomes “H” when all outputs are “H”. An AND gate 164 receives the outputs of the shift registers 159, 160, and then outputs a signal GET which becomes “H” when both outputs are “H”.
The circuits shown in
In circuits shown in
The circuits shown in
In circuits shown in
In circuits shown in
A counter 184 counts an output of the AND gate 183 at a timing which is given by the signal DLP output from the D-type flip-flop 171 shown in
An output of an AND gate 186 becomes “H” only when both the signal RBF being output from the circuits shown in
In the seventh embodiment, in addition to the similar advantage achieved by the fifth embodiment, such an advantage can be attained by setting appropriately the flicker patterns and the flicker exception-patterns that finer adjustment can be implemented.
In the above first to sixth embodiments, the timing controller 31 is connected to the personal computer, but the present invention is not limited to such embodiments. As devices being connected to the timing controller, there are a TV tuner, other video devices, etc.
Also, the above first to seventh embodiments show an example of the present invention respectively. The present invention is not limited to the scopes given by the above-mentioned embodiments.
| Number | Date | Country | Kind |
|---|---|---|---|
| 10-304923 | Oct 1998 | JP | national |
| 10-355875 | Dec 1998 | JP | national |
| 11-217333 | Jul 1999 | JP | national |
This is a Divisional of application Ser. No. 09/428,324 filed Oct. 27, 1999 now U.S. Pat. No. 6,680,722.
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| Number | Date | Country | |
|---|---|---|---|
| 20040070581 A1 | Apr 2004 | US |
| Number | Date | Country | |
|---|---|---|---|
| Parent | 09428324 | Oct 1999 | US |
| Child | 10669863 | US |
