Display with vias for concealed printed circuit and component attachment

Information

  • Patent Grant
  • 9805643
  • Patent Number
    9,805,643
  • Date Filed
    Friday, September 25, 2015
    9 years ago
  • Date Issued
    Tuesday, October 31, 2017
    7 years ago
Abstract
An electronic device may include a display. The display may be an organic light-emitting diode display. The organic light-emitting diode display may have a substrate layer, a layer of organic light-emitting diode structures, and a layer of sealant. Vias may be formed in the substrate layer by laser drilling. The vias may be filled with metal using electroplating or other metal deposition techniques. The vias may be connected to contacts on the rear surface of the display. Components such as flexible printed circuits, integrated circuits, connectors, and other circuitry may be mounted to the contacts on the rear surface of the display.
Description
BACKGROUND

This relates generally to electronic devices, and more particularly, to displays for use in electronic devices.


Electronic devices such as portable computers and other electronic equipment may have displays. Driver circuitry may be used to control operation of the displays. In some displays, such as liquid crystal displays, a layer such as a thin-film transistor layer may have a ledge portion on which a display driver integrated circuit is mounted. The minimum size needed for the ledge is at least partly dictated by the size of the driver integrated circuit. In some device designs, such as designs for compact portable devices, the inclusion of this type of driver ledge may give rise to a border region for a liquid crystal display that is larger than desired. In other displays, driver circuitry may be coupled to the display using a flexible printed circuit cable. The attachment structures needed to accommodate attachment of the flexible printed circuit cable to the display may consume more area than desired, particularly in compact devices and in arrangements where thin display borders are desired.


It would therefore be desirable to provide improved ways to interconnect displays with associated circuitry such as display driver circuitry.


SUMMARY

An electronic device may include a display. The display may be an organic light-emitting diode display. The organic light-emitting diode display may, for example, have a substrate layer, a layer of organic light-emitting diode structures, and a layer of sealant.


Vias may be formed in a display substrate layer by laser drilling or other via hole formation techniques. The vias may be filled with a conductive material such as metal using electroplating or other metal deposition techniques. The vias may be connected to contacts on the rear surface of the display. Components such as flexible printed circuits, integrated circuits, connectors, and other circuitry may be mounted to the contacts on the rear surface of the display. Conductive materials such as solder and conductive adhesive may be used in mounting components to the contacts.


Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description.





BRIEF DESCRIPTION OF THE DRAWINGS


FIGS. 1 and 2 are cross-sectional side views of illustrative electronic devices with displays in accordance with embodiments of the present invention.



FIG. 3 is a top view of an illustrative display showing how vias may be used in distributing signals for the display in accordance with an embodiment of the present invention.



FIG. 4 is a cross-sectional side view of a portion of a display showing how a via may be formed through the rear surface of the display in accordance with an embodiment of the present invention.



FIG. 5 is a diagram showing how a display may be provided with vias so that circuitry can be attached to the rear of the display in accordance with an embodiment of the present invention.



FIG. 6 is a diagram showing how a display may be formed from a substrate such as a flexible printed circuit substrate that has backside contacts in accordance with an embodiment of the present invention.





DETAILED DESCRIPTION

Electronic devices may be provided with displays having vias. An illustrative electronic device of the type that may be provided with a display having vias is shown in FIG. 1. Electronic device 10 of FIG. 1 may be a computer, a personal computer, a tablet computer, a cellular telephone, a media player, a gaming device, a navigation device, or other electronic equipment. As shown in the cross-sectional view of device 10 in FIG. 1, electronic device 10 may include housing 12, a display such as display 14, and internal components such as components 16.


Housing 12 may be formed from plastic, metal, fiber-composite materials, glass, ceramic, other materials, or combinations of these materials. Display 14 may be a liquid crystal display, an organic light-emitting diode display, a plasma display, an electrochromic display, an electrophoretic ink display, an electrowetting display, or other suitable display. Examples in which display 14 is implemented as an organic light-emitting diode display are sometimes described herein as an example. This is, however, merely illustrative. Display 14 may be formed using any suitable display if desired. If desired, display 14 may be covered with a cover layer of glass or plastic or other protective display layer. In the example of FIG. 1, the cover layer has been omitted.


Internal components 16 may include printed circuits such as rigid printed circuit boards (e.g., fiberglass-filled epoxy printed circuit boards), flexible printed circuits (“flex circuits”) formed from flexible sheets of polymers such as polyimide, “rigid flex” printed circuits (e.g., printed circuit boards including rigid printed circuit portions with integral flex circuit tails), or other printed circuit structures. As an example, device 10 may include a printed circuit such as printed circuit board 18 on which one or more components such as electrical components 20 or other internal components 16 have been mounted. Components 20 may include switches, connectors, discrete components such as capacitors, resistors, and inductors, integrated circuits, and other electronic components.


As shown in FIG. 1, display 14 may have multiple layers. For example, display 14 may be an organic light-emitting diode display having a substrate layer such as substrate layer 22, a layer of thin-film transistor structures (e.g., polysilicon transistors and/or amorphous silicon transistors) and organic emissive material such as layer 24, and a sealant layer such as layer 26. Substrate layer 22 may be formed from a rigid or flexible dielectric such as glass, ceramic, or plastic. As an example, substrate 22 in display 14 may be formed from a flexible sheet of polymer such as a layer of polyimide.


Vias such as vias 28 may be formed in display 14. As shown in FIG. 1, for example, vias 28 may be formed through substrate layer 22 so that electrical contacts may be formed on the rear (inner) surface of substrate 22 and display 14. Vias 28 may be formed by laser drilling and electroplating or using other fabrication techniques. Conductive material in vias 28 such as metal (e.g., gold plated copper) may be used to form signal paths in display 14. The signal paths may, for example, be used to route signals between the circuitry of layer 24 (e.g., thin-film transistors) and external circuitry such as display driver circuitry.


In the example of FIG. 1, display driver circuitry for display 14 has been provided using display driver integrated circuit 30. Display driver integrated circuit 30 (in the FIG. 1 example) has been mounted on printed circuit 32. Printed circuit 32 may be a rigid printed circuit board or a flex circuit. For example, printed circuit 32 may be a flex circuit that includes one or more layers of patterned interconnect lines such as traces 34. Traces 34 may be electrically connected between one or more vias in substrate layer 22 of display 14 and driver integrated circuit 30. If desired, traces 34 may be connected to a communications path formed from flex circuit 36 (e.g., a flex circuit that is connected to printed circuit board 18 directly or, as shown in FIG. 1, a flex circuit that is connected to components 20 on printed circuit board 18 via flex circuit connector 20′).


The connection between flex circuit 36 and printed circuit 32 may be formed using a connector or by directly attaching flex circuit 36 to traces 34 on printed circuit 32.


By using vias 28 in layer 22, the need to form flex circuit attachments or driver circuit attachments to the front (upper/exterior) surface of display 14 may be avoided, allowing the edge regions surrounding the active display pixels in display 14 to be minimized. More area in display 14 may therefore be available for forming the array of pixels that displays images to a user.


If desired, a jumper structure such as structure 38 may be attached to vias on the backside of substrate 22 and may be used to route signals between two or more different locations in display 14. Structure 38 may be formed from a printed circuit such as a flex circuit or rigid printed circuit board. Traces 40 in structures 38 may be used to help distribute signals for display 14. Any suitable signals may be routed through flex circuits or other jumper structures on the rear of display 14. For example, structures 38 may be used to carry gate line signals, data line signals, power supply signals, or other information or power signals associated with operating display 14. By implementing at least some of the interconnect resources associated with display 14 using structures located on the rear surface of display 14, more room may be made available on the front surface of display 14 for active pixel structures and the size of any inactive border regions on the front side of display 14 may be minimized.


In the illustrative arrangement of FIG. 1, flex circuit 32 is being used to support display driver integrated circuit 30 and a separate flex circuit such as flex circuit 36 is being used to couple flex circuit 32 to printed circuit board 18 (using connector 20′). Other arrangements may be used if desired. For example, flex circuit 32 may be connected directly to traces on printed circuit board 18 (e.g., using anisotropic conductive film or solder connections) or flex circuit 32 may be connected directly to connector 20′. There may be more than one flex circuit such as flex circuit 32 that is interconnected between rear surface vias 28 on display 14 and circuitry such as circuitry in components 20 on printed circuit board 18. Supplemental interconnection pathways such as traces 40 of flex circuit 38 may be provided on one or more, two or more, or three or more integrated circuits. Flex circuits such as flex circuit 32 may include mounted circuits such as display driver integrated circuit 30 for controlling the operation of display 14 and may, if desired, include supplemental interconnect lines for forming gate line paths, data line paths, power lines paths, or other signal paths in device 10. Supplemental interconnect lines for forming gate line paths, data line paths, power lines paths, or other signal paths in device 10 may also be formed using jumper structures 38.


As shown in FIG. 2, a printed circuit such as flex circuit 42 may have traces such as traces 44 that form a path between vias 28 in substrate 22 of display 14 and circuitry on printed circuit board 18. A connector such as connector 20′ of FIG. 2 or a direct attachment scheme (e.g., using solder or anisotropic conductive film) may be used to interconnect traces 44 to traces on printed circuit board 18 such as traces 46. Display driver circuitry 30 (e.g., a display driver integrated circuit) may, if desired, be mounted on printed circuit 18 and may be coupled to traces 44 in printed circuit 42 via traces 46.


An arrangement that may be used for providing vias 28 in display 14 is shown the top view of illustrative display 14 of FIG. 3. As shown in FIG. 3, display 14 may display pixels such as display pixels 48. Display pixels 48 may each contain an organic light-emitting diode structure for emitting light for display 14. Display pixels 48 may be organized in an array such as array 50. Array 50 may contain any suitable number or rows and columns of display pixels 48. For example, array 50 may have hundreds of rows and/or hundreds of columns of display pixels 48 (as an example). Vertical and horizontal control lines may be used in supplying control signals to display pixels 48. For example, signals may be applied to respective columns of display pixels 48 using vertical signal lines such as lines 52 and may be applied to respective rows of display pixels 48 using horizontal signal lines such as lines 54.


If desired, signal lines such as lines 52 may be coupled to vias in substrate layer 22 of display 14 such as vias 28A. Signal lines such as lines 54 may be coupled to vias in substrate layer 22 of display 14 such as vias 28B. Vias in substrate layer 22 such as vias 28C may be formed within array 50 (e.g., at intermediate locations in the rows or columns of display pixels 48). Edge vias such as vias 28D may also be formed in substrate 22 and may be used for handling signals associated with operating display pixels 48 (e.g., signals for lines 52 and/or 54).


A cross-sectional side view of a portion of display 14 containing a via is shown in FIG. 4. Via 28 may be one of vias 28 of FIGS. 1 and 2, one of vias 28A, 28B, 28C, or 28D of FIG. 3, or other vias formed through substrate 22 of display 14. As shown in FIG. 4, via 28 may include tubular metal sidewalls such as sidewalls 60 that coat the cylindrical inner surface of a through hole in layer 22. Sidewalls 60 may be formed by any suitable fabrication technique. For example, sidewalls 60 may be formed using electrodeposition (e.g., formation of a thin seed layer followed by electroplating of a metal such as copper and, if desired, a subsequent coating of a metal such as gold). With a via structure of the type shown in FIG. 4, via 28 is formed from a hole (e.g., a cylindrical hole) in substrate 22 and is lined with a tubular layer of metal. Other types of vias may be formed in layer 22 if desired (e.g., via holes that are plugged with solid metal, etc.).


If desired, traces may be formed on the surface of substrate 22. As shown in FIG. 4, for example, contact pad 62 may be formed on rear surface 64 of display 14. Contact 62 may be formed from a metal trace that is electrically shorted to sidewalls 60 of via 28. Additional patterned conductive structures may be formed on surface 64 of substrate 22 if desired. The example of FIG. 4 is merely illustrative.



FIG. 5 is a diagram showing how a display may be provided with vias. Initially, a display substrate such as substrate 22 may be provided. Substrate 22 may be, for example, a layer of polymer such as a layer of polyimide.


Via hole formation equipment 70 such as laser drilling equipment may be used to form one or more via holes such as via hole 72 in substrate 22.


Following formation of via holes such as via hole 72, conductive material deposition equipment such as metal plating equipment 74 may be used to form conductive structures for vias 28 such as conductive sidewalls 60. Traces such as contact trace 62 may also be formed on lower surface 64 of substrate 22.


Organic light-emitting diode (OLED) fabrication equipment 76 or other display fabrication equipment may be used to complete display 14. For example, OLED fabrication equipment 76 may be used to form thin-film transistor structures and interconnects in layer 24. Layer 24 may include organic emissive material and light-emitting diode structures that are used to form display pixels such as display pixels 48 of FIG. 3. A sealant layer such as sealant layer 26 (e.g., a polymer layer) may then be formed over the front (upper) surface of display 14 to protect the structures of layer 24.


Additional processing equipment 78 may then be used to form electrical connections to additional circuitry 84. As shown in FIG. 5, conductive material 82 may be used in forming electrical connections between contacts such as contact 62 on display 14 (e.g., contacts on surface 64 of substrate 22) and associated contacts such as contact 80 on additional circuitry 84. Conductive material 82 may be solder, metal associated with a weld, part of a connector, conductive adhesive (e.g., anisotropic conductive film), or other suitable material for forming an electrical connection between via 28 and additional circuitry 84. Additional circuitry 84 may be a printed circuit or other circuitry. For example, additional circuitry 84 may be a flex circuit on which integrated circuits and/or other electrical components are mounted, a flex circuit cable that is attached to a printed circuit board with components, a rigid printed circuit board, or other suitable circuitry (see, e.g., the illustrative arrangements of FIGS. 1, 2, and 3).



FIG. 6 is a diagram showing how display 14 may be formed from a two-sided printed circuit layer that serves as substrate 22.


Initially, printed circuit processing equipment 86 may be used to produce patterned two-sided printed circuit 22. Patterned two-sided printed circuit 22 may include patterned traces 88 and patterned traces 90 on opposing first (upper) and second (lower) surfaces. If desired, one or more layers of internal printed circuit traces such as traces 92 may be used to interconnect upper surface traces 88 and lower surface traces 90 (i.e., printed circuit layer 22 may include multiple sublayers of dielectric such as polyimide and one or more corresponding sublayers of patterned traces). Traces 92 may include vias 28.


Following formation of a multilayer printed circuit such as a two-sided printed circuit substrate or a multilayer printed circuit substrate that includes one or more patterned internal layers of traces and/or one or two exposed surfaces covered with of external traces such as substrate 22, OLED processing equipment 94 may be used to complete the formation of OLED display 14 by forming organic emissive material and light-emitting diode structures in layer 24 and covering layer 24 with sealant layer 26.


Component mounting tools and other processing equipment 96 may be used to mount components 102 to substrate 22. In particular, conductive material 104 such as solder, welds, conductive material associated with connector structures, anisotropic conductive film or other conductive adhesive, or other conductive material may be used to connect traces (contacts) 100 on components 102 to corresponding traces 90 on rear surface 64 of display 14. Examples of components 102 that equipment 96 may attach to traces 90 include integrated circuits, discrete components such as resistors, capacitors, and inductors, connectors, flex circuit cables and other printed circuit structures, and other circuitry. Components 102 may be, for example, surface mount technology (SMT) components and equipment 96 may be a pick-and-place tool.


The foregoing is merely illustrative of the principles of this invention and various modifications can be made by those skilled in the art without departing from the scope and spirit of the invention.

Claims
  • 1. An electronic device comprising: a housing;a display mounted in the housing, wherein the display comprises a substrate with first and second opposing surfaces, a thin-film transistor layer formed on the first surface, a via that extends from the first surface to the second surface, and a metal contact on the second surface that is electrically coupled to the via;a first printed circuit with conductive traces;a display driver integrated circuit mounted to the first printed circuit, wherein the display driver integrated circuit is electrically coupled to the metal contact through the conductive traces on the first printed circuit;a second printed circuit that is electrically coupled to the display driver integrated circuit through the conductive traces on the first printed circuit; andelectroplated metal sidewalls in the via.
  • 2. The electronic device defined in claim 1, wherein the second printed circuit comprises a flexible printed circuit that electrically couples the display driver integrated circuit to the metal contact.
  • 3. The electronic device defined in claim 2, wherein the display driver integrated circuit transmits signals to the thin-film transistor layer through the flexible printed circuit.
  • 4. The electronic device defined in claim 3, wherein the first printed circuit comprises a connector that is electrically coupled to the metal traces on the first printed circuit, wherein the flexible printed circuit has a first end that is connected to the metal contact on the substrate and a second opposing end that is connected to the connector on the first printed circuit.
  • 5. The electronic device defined in claim 1, wherein the first printed circuit is mounted to the metal contact on the second surface of the substrate.
  • 6. The electronic device defined in claim 5, wherein the second printed circuit is electrically coupled to the display driver integrated circuit through a flexible printed circuit that extends between the first and second printed circuits.
  • 7. The electronic device defined in claim 6, wherein the flexible printed circuit has first and second opposing ends, wherein the second printed circuit comprises a flex circuit connector, wherein the first end of the flexible printed circuit is attached to the flex circuit connector, and wherein the second end of the flexible printed circuit is attached to the first printed circuit board.
  • 8. The electronic device defined in claim 1, wherein the first printed circuit has first and second opposing surfaces, wherein the first surface of the first printed circuit is interposed between the second surface of the first printed circuit and the second surface of the substrate, and wherein the display driver integrated circuit is mounted on the second surface of the first printed circuit.
  • 9. The electronic device defined in claim 1, wherein the display has an active area and an inactive area, and wherein the via is formed in the inactive area of the display.
  • 10. The electronic device defined in claim 1, wherein the display has an active area and an inactive area, and wherein the via is formed in the active area of the display.
  • 11. An electronic device, comprising; a housing;a display mounted in the housing, wherein the display comprises a display substrate having first and second opposing surfaces, first and second conductive vias that extend from the first surface to the second surface, wherein the first and second conductive vias comprise conductive material that extends from the first surface to the second surface, and thin-film transistor circuitry that is formed on the first surface and electrically coupled to the first and second conductive vias; anda conductive path that routes signals from the first conductive via to the second conductive via.
  • 12. The electronic device defined in claim 11, wherein the second surface of the display substrate is interposed between the conductive path and the first surface of the display substrate.
  • 13. The electronic device defined in claim 12 further comprising a printed circuit mounted to the second surface of the display substrate, wherein the conductive path is a trace on the printed circuit.
  • 14. The electronic device defined in claim 12, wherein the conductive path comprises a gate line that routes gate line signals from the first conductive via to the second conductive via.
  • 15. The electronic device defined in claim 12, wherein the conductive path comprises a data line that routes data line signals from the first conductive via to the second conductive via.
  • 16. The electronic device defined in claim 12, wherein the first and second conductive vias have electroplated metal sidewalls.
  • 17. An electronic device, comprising: a display, comprising: a display substrate having first and second opposing surfaces;a plurality of vias that extend through the display substrate from the first surface to the second surface; andthin-film transistor circuitry formed on the first surface of the display substrate;a display driver integrated circuit that transmits signals to the thin-film transistor circuitry through a first via in the plurality of vias, wherein the second surface of the display substrate is interposed between the display driver integrated circuit and the first surface of the display substrate; anda conductive trace that routes signals between a second via in the plurality of vias and a third via in the plurality of vias, wherein the second surface of the display substrate is interposed between the conductive trace and the first surface of the display substrate.
  • 18. The electronic device defined in claim 17, further comprising: a first printed circuit board on which the conductive trace is formed, wherein the first printed circuit board is mounted to the second surface of the display substrate.
  • 19. The electronic device defined in claim 18, further comprising: a second printed circuit board on which the display driver integrated circuit is mounted, wherein the second printed circuit is mounted to the second surface of the display substrate.
  • 20. The electronic device defined in claim 17, wherein the display comprises an active area and an inactive area, wherein a first portion of the plurality of vias are formed in the active area, and wherein a second portion of the plurality of vias are formed in the inactive area.
Parent Case Info

This application is a continuation of U.S. patent application Ser. No. 13/284,096, filed on Oct. 28, 2011, which is hereby incorporated by reference herein in its entirety. This application claims the benefit of and claims priority to U.S. patent application Ser. No. 13/284,096, filed on Oct. 28, 2011.

US Referenced Citations (136)
Number Name Date Kind
2933655 Gradisar et al. Apr 1960 A
4066855 Zenk Jan 1978 A
4085302 Zenk et al. Apr 1978 A
4431270 Funada Feb 1984 A
4487993 Becker Dec 1984 A
4549174 Funada Oct 1985 A
5235451 Bryan Aug 1993 A
5276382 Stocker et al. Jan 1994 A
5436744 Arledge et al. Jul 1995 A
5483261 Yasutake Jan 1996 A
5488204 Mead et al. Jan 1996 A
5493096 Koh Feb 1996 A
5577205 Hwang et al. Nov 1996 A
5592199 Kawaguchi Jan 1997 A
5670994 Kawaguchi Sep 1997 A
5825352 Bisset et al. Oct 1998 A
5835079 Shieh Nov 1998 A
5844781 Schlotter et al. Dec 1998 A
5880411 Gillespie et al. Mar 1999 A
5880705 Onyskevych et al. Mar 1999 A
6091194 Swirbel et al. Jul 2000 A
6188391 Seely et al. Feb 2001 B1
6191435 Inoue Feb 2001 B1
6201346 Kusaka Mar 2001 B1
6239982 Bozzer et al. May 2001 B1
6310610 Beaton et al. Oct 2001 B1
6323846 Westerman et al. Nov 2001 B1
6421033 Williams et al. Jul 2002 B1
6498592 Matthies Dec 2002 B1
6560117 Moon May 2003 B2
6617177 Winer Sep 2003 B1
6690387 Zimmerman et al. Feb 2004 B2
6738263 Corisis et al. May 2004 B2
6774872 Kawada et al. Aug 2004 B1
6801174 Kayama et al. Oct 2004 B2
6815835 James Nov 2004 B2
7015894 Morohoshi Mar 2006 B2
7133037 Kim Nov 2006 B2
7184064 Zimmerman et al. Feb 2007 B2
7211738 Lee et al. May 2007 B2
7245500 Khan et al. Jul 2007 B2
7342354 Utsunomiay et al. Mar 2008 B2
7417867 Matsuda et al. Aug 2008 B1
7663607 Hotelling et al. Feb 2010 B2
7791700 Bellamy Sep 2010 B2
7796397 Yamauchi et al. Sep 2010 B2
7816721 Yamazaki et al. Oct 2010 B2
7864136 Matthies et al. Jan 2011 B2
7977170 Tredwell et al. Jul 2011 B2
8148259 Arai et al. Apr 2012 B2
8169588 Oikawa et al. May 2012 B2
8194222 Seki et al. Jun 2012 B2
8222666 Hatano et al. Jul 2012 B2
8253914 Kajiya et al. Aug 2012 B2
8258523 Lee et al. Sep 2012 B2
8269923 Yamagishi et al. Sep 2012 B2
8362488 Chaug et al. Jan 2013 B2
8395722 Mathew et al. Mar 2013 B2
8446557 Oohira May 2013 B2
8450769 Hatano et al. May 2013 B2
8456586 Mathew et al. Jun 2013 B2
8466852 Drzaic et al. Jun 2013 B2
8599353 Corrigan et al. Dec 2013 B2
8623575 Chen et al. Jan 2014 B2
8674344 Lee Mar 2014 B2
8736802 Kajiya et al. May 2014 B2
8766314 Hatano et al. Jul 2014 B2
8766858 Li et al. Jul 2014 B2
8767141 Mathew et al. Jul 2014 B2
8804347 Martisauskas Aug 2014 B2
8829790 Yee Sep 2014 B2
9195105 Kajiya et al. Nov 2015 B2
20010015788 Mandai et al. Aug 2001 A1
20020085158 Armagost et al. Jul 2002 A1
20020088986 Kayama et al. Jul 2002 A1
20030011298 Palanisamy Jan 2003 A1
20030206331 Chung et al. Nov 2003 A1
20040016568 Palanisamy Jan 2004 A1
20040245924 Utsunomiya et al. Dec 2004 A1
20040263947 Drzaic et al. Dec 2004 A1
20050072597 Lee et al. Apr 2005 A1
20060026521 Hotelling et al. Feb 2006 A1
20060125995 Tai et al. Jun 2006 A1
20060152500 Weng Jul 2006 A1
20060197753 Hotelling et al. Sep 2006 A1
20060231844 Carter Oct 2006 A1
20070002009 Pasch et al. Jan 2007 A1
20070019147 Ryu Jan 2007 A1
20070035679 Lee et al. Feb 2007 A1
20070063939 Bellamy Mar 2007 A1
20070080360 Mirsky et al. Apr 2007 A1
20070148831 Nagata et al. Jun 2007 A1
20080024060 Jonnalagadda et al. Jan 2008 A1
20080035929 Chen et al. Feb 2008 A1
20080042180 Yamazaki et al. Feb 2008 A1
20080049408 Yamauchi et al. Feb 2008 A1
20080143913 Lee et al. Jun 2008 A1
20080149731 Arai Jun 2008 A1
20090027896 Nishimura et al. Jan 2009 A1
20090122653 Seki May 2009 A1
20090191670 Heitzinger et al. Jul 2009 A1
20090278452 Kim Nov 2009 A1
20090284688 Shiraishi et al. Nov 2009 A1
20100097551 Yamagishi et al. Apr 2010 A1
20100148209 Hatano et al. Jun 2010 A1
20100265225 Han et al. Oct 2010 A1
20100315570 Mathew et al. Dec 2010 A1
20110012845 Rothkopf et al. Jan 2011 A1
20110109829 Mathew et al. May 2011 A1
20110176199 Sakurai et al. Jul 2011 A1
20110186345 Pakula et al. Aug 2011 A1
20110194063 Lee et al. Aug 2011 A1
20110204403 Kim et al. Aug 2011 A1
20110292323 Corrigan et al. Dec 2011 A1
20110317120 Kajiya et al. Dec 2011 A1
20120009973 Demuynck et al. Jan 2012 A1
20120218502 Seki Aug 2012 A1
20120235969 Burns et al. Sep 2012 A1
20120242592 Rothkopf et al. Sep 2012 A1
20120273834 Hatano et al. Nov 2012 A1
20120287386 Kajiya et al. Nov 2012 A1
20120319304 Pressel et al. Dec 2012 A1
20120320319 Chen et al. Dec 2012 A1
20130002685 Shenoy et al. Jan 2013 A1
20130082984 Drzaic et al. Apr 2013 A1
20130088671 Drzaic et al. Apr 2013 A1
20130094126 Rappoport et al. Apr 2013 A1
20130107476 Wright et al. May 2013 A1
20130228785 Hatano et al. Sep 2013 A1
20130328051 Franklin et al. Dec 2013 A1
20130342099 Weber et al. Dec 2013 A1
20140049522 Mathew et al. Feb 2014 A1
20140063393 Zhong et al. Mar 2014 A1
20140138733 Hatano et al. May 2014 A1
20140254094 Chang et al. Sep 2014 A1
20140293210 Kajiya et al. Oct 2014 A1
Foreign Referenced Citations (41)
Number Date Country
1912716 Feb 2007 CN
101430473 May 2009 CN
101636689 Jan 2010 CN
102187272 Sep 2011 CN
0474508 Mar 1992 EP
2138892 Mar 2002 EP
2141573 Jun 2010 EP
2418537 Feb 2012 EP
10-261854 Sep 1998 JP
200163031 Jun 2000 JP
2001-092381 Apr 2001 JP
2001215528 Aug 2001 JP
2002-040472 Feb 2002 JP
200293851 Mar 2002 JP
2002116454 Apr 2002 JP
2002-341785 Nov 2002 JP
2002342033 Nov 2002 JP
H05-142556 Nov 2002 JP
2003058074 Feb 2003 JP
2003-255850 Sep 2003 JP
2003-337353 Nov 2003 JP
3593975 Nov 2004 JP
200549685 Feb 2005 JP
2007220569 Aug 2007 JP
2008-033094 Feb 2008 JP
2009-098451 May 2009 JP
2009-229754 Oct 2009 JP
2009-244338 Oct 2009 JP
2010-039211 Feb 2010 JP
2011042531 Mar 2011 JP
10-2005-0093595 Sep 2005 KR
10-2010-005021 Jan 2010 KR
10-2011-0059629 Jun 2011 KR
10-2012-0020088 Mar 2012 KR
200521587 Jul 2005 TW
I297095 May 2008 TW
200839356 Oct 2008 TW
201001624 Jan 2010 TW
2006106365 Oct 2006 WO
20081114404 Sep 2008 WO
2009089105 Jul 2009 WO
Related Publications (1)
Number Date Country
20160021746 A1 Jan 2016 US
Continuations (1)
Number Date Country
Parent 13284096 Oct 2011 US
Child 14866494 US