Domino logic circuit techniques for suppressing subthreshold and gate oxide leakage

Abstract

Circuits are provided for simultaneously reducing the subthreshold and gate oxide leakage power consumption in domino logic circuits. Sleep transistors and a dual threshold voltage CMOS technology may be utilized to place idle domino logic circuits into a low leakage state. The circuits may significantly lower the total leakage power as compared to the standard dual threshold voltage domino logic circuits at both the high and low die temperatures. The energy overheads of the circuit techniques may be low, justifying the activation of the proposed sleep schemes by providing net savings in total power consumption during short idle periods.

Description

BRIEF DESCRIPTION OF THE DRAWINGS

The system may be better understood with reference to the following drawings and description. The components in the figures are not necessarily to scale, emphasis instead being placed upon illustrating the principles of the invention. Moreover, in the figures, like referenced numerals designate corresponding parts throughout the different views.

FIG. 1 is a schematic of a prior art multi-stage domino logic circuit.

FIG. 2 is a schematic of a single stage of the domino logic circuit depicted in FIG. 1.

FIG. 3 is a schematic of a single stage of the domino logic circuit depicted in FIG. 1 with a foot transistor (N3).

FIG. 4 is a schematic of a footless dual-V_t domino logic circuit, with a sleep circuit comprising NMOS/PMOS sleep switches without a sleep switch at the output node.

FIG. 5 is a schematic of a footed dual-V_t domino logic circuit, with a sleep circuit comprising NMOS/PMOS sleep switches without a sleep switch at the output node.

FIG. 6 is a schematic of a multiple stage dual-V_t domino logic circuit, with a sleep circuit comprising NMOS/PMOS sleep switch without the sleep switches at the dynamic and output nodes in the second and later stages.

FIG. 7 is a schematic of a footless PMOS-only sleep switch dual-V_t domino gate.

FIG. 8 is a 2-input dual-V_t domino OR gate with low-V_t (P1 and P2) and high-V_t (P3) PMOS sleep transistors.

FIG. 9 is a schematic of a footless PMOS-only sleep switch dual-V_t domino gate where the PMOS-only sleep switches are high-V_t.

FIG. 10 is a schematic of a footed PMOS-only sleep switch dual-V_t domino gate where the PMOS-only sleep switches are high-V_t.

FIG. 11 is a schematic of a footless PMOS-only sleep switch dual-V_t domino gate, where the sleep circuit includes only two PMOS sleep transistors.

FIG. 12 is a schematic of a footed PMOS-only sleep switch dual-V_t domino gate, where the sleep circuit includes only two PMOS sleep transistors.

FIG. 13 is a schematic of a footless PMOS-only sleep switch dual-V_t domino gate, where the sleep circuit includes only two high-V_t PMOS sleep transistors.

FIG. 14 is a schematic of a footed PMOS-only sleep switch dual-V_t domino gate, where the sleep circuit includes only two high-V_t PMOS sleep transistors.

FIG. 15 is a schematic of a multiple stage PMOS sleep switch dual-V_t domino logic circuit without the sleep switches at the dynamic and output nodes in the second and later stages.

FIG. 16 is a schematic of a multiple stage PMOS sleep switch dual-V_t domino logic circuit without the sleep switches at the dynamic and output nodes in the second and later stages, where the sleep switches are high-V_t PMOS transistors.

FIG. 17 is a schematic of a footless single stage domino logic circuit where the sleep circuit consists of a single PMOS transistor.

FIG. 18 is a schematic of a footed single stage domino logic circuit where the sleep circuit consists of a single PMOS transistor.

FIG. 19 is a schematic of a domino logic circuit having multiple stages, with a single PMOS sleep switch being used for the multiple stages.

Claims

1. A domino logic circuit comprising: a precharge circuit for precharging a dynamic node to a predetermined value;an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node; anda sleep circuit consisting of a single sleep transistor for inhibiting current to the output circuit during a sleep mode.

2. The domino logic circuit of claim 1, wherein the output circuit comprises an inverter; and wherein the sleep transistor is in a circuit path between a supply voltage and the inverter; andwherein the sleep transistor during a sleep mode inhibits a static DC current path through the inverter.

3. The domino logic circuit of claim 2, wherein the sleep transistor is directly connected to the supply voltage and to the inverter.

4. The domino logic circuit of claim 2, wherein the domino logic circuit comprises multiple stages, each stage including a precharge circuit, an input circuit, an output circuit, and a sleep circuit consisting of a single sleep transistor.

5. The domino logic circuit of claim 4, wherein the multiple stages of the domino logic circuit use the same single sleep transistor to inhibit a static DC current path in each of the output circuits of the multiple stages.

6. The domino logic circuit of claim 4, wherein the domino logic circuit further comprises an input stage, the input stage including a precharge circuit, an input circuit, an output circuit, and a sleep circuit comprising multiple sleep transistors.

7. The domino logic circuit of claim 1, further comprising a keeper circuit for keeping the dynamic node at the predetermined value after the precharge circuit precharges the dynamic node to the predetermined value, the keeper circuit including an input that is connected to the output of the output circuit.

8. The domino logic circuit of claim 7, wherein the keeper circuit consists of a single keeper transistor.

9. The domino logic circuit of claim 8, wherein the sleep transistor is in a circuit path between a supply voltage and the single keeper transistor; and wherein the sleep transistor during a sleep mode inhibits a static DC current path through the single keeper transistor.

10. The domino logic circuit of claim 9, wherein the domino logic circuit comprises multiple stages, each stage including a precharge circuit, an input circuit, an output circuit, a keeper circuit, and a sleep circuit consisting of a single sleep transistor; and wherein the multiple stages of the domino logic circuit use the same single sleep transistor to inhibit a first static DC current path through the output circuit in each of the output circuits of the multiple stages and to inhibit second static DC current path through each of the keeper circuits.

11. A domino logic circuit comprising: a precharge circuit for precharging a dynamic node to a predetermined value;an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node; anda sleep circuit consisting of one or more PMOS transistors for reducing current to the output circuit or discharging the dynamic node during a sleep mode.

12. The domino logic circuit of claim 11, wherein the sleep circuit consisting of three PMOS transistors, a first PMOS transistor connected to the dynamic node, a second PMOS transistor connected to the output of the output circuit, and a third PMOS transistor connected between the output circuit and a supply voltage.

13. The domino logic circuit of claim 13, wherein at least one of the three PMOS transistors has a higher threshold voltage than at least one remaining transistor of the three PMOS transistors.

14. The domino logic circuit of claim 13, wherein the three PMOS transistors each have a higher threshold voltage than at least one transistor in the output circuit.

15. The domino logic circuit of claim 11, wherein the sleep circuit consisting of two PMOS transistors, a first PMOS transistor connected to the dynamic node and a second PMOS transistor connected between the output circuit and a supply voltage.

16. A domino logic circuit comprising: a precharge circuit for precharging a dynamic node to a predetermined value;an input circuit having at least one input and at least one output, the at least one output in communication with the dynamic node, the input circuit comprising logic for determining a value of the dynamic node based on the at least one input;an output circuit having at least one input and at least one output, the at least one input in communication with the dynamic node;a keeper circuit for keeping the dynamic node at the predetermined value after the precharge circuit precharges the dynamic node to the predetermined value, the keeper circuit including an input that is connected to the output of the output circuit; anda sleep circuit for reducing current to at least one of the output circuit or the keeper circuit during a sleep mode.

17. The domino logic circuit of claim 16, wherein the keeper circuit consists of a single keeper transistor.

18. The domino logic circuit of claim 17, wherein the sleep circuit comprises a sleep transistor in a circuit path between a supply voltage and the single keeper transistor; and wherein the sleep transistor during a sleep mode inhibits a static DC current path through the single keeper transistor.

19. The domino logic circuit of claim 18, wherein the domino logic circuit comprises multiple stages, each stage including a precharge circuit, an input circuit, an output circuit, a keeper circuit and a sleep circuit consisting of a single sleep transistor.

20. The domino logic circuit of claim 19, wherein the multiple stages of the domino logic circuit use the same single sleep transistor to inhibit a static DC current path in each of the keeper circuits of the multiple stages.

21. The domino logic circuit of claim 17, wherein the sleep circuit comprises a sleep transistor in a circuit path between a supply voltage and the output circuit; and wherein the sleep transistor during a sleep mode inhibits a static DC current path through the output circuit.

22. The domino logic circuit of claim 17, wherein the sleep circuit consists of a single sleep transistor in a circuit path between a supply voltage and the output circuit and in a circuit path between the supply voltage and the single sleep transistor.

23. The domino logic circuit of claim 22, wherein the domino logic circuit comprises multiple stages, each stage including a precharge circuit, an input circuit, an output circuit, a keeper circuit and a sleep circuit consisting of a single sleep transistor; and wherein the multiple stages of the domino logic circuit use the same single sleep transistor to inhibit a static DC current path in each of the keeper circuits and the output circuits of the multiple stages.